WO2003096390A1 - High-k dielectric for thermodynamically-stable substrate-type materials - Google Patents
High-k dielectric for thermodynamically-stable substrate-type materials Download PDFInfo
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- WO2003096390A1 WO2003096390A1 PCT/US2002/011785 US0211785W WO03096390A1 WO 2003096390 A1 WO2003096390 A1 WO 2003096390A1 US 0211785 W US0211785 W US 0211785W WO 03096390 A1 WO03096390 A1 WO 03096390A1
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- WIPO (PCT)
- Prior art keywords
- surface material
- oxide
- dielectric
- electronics device
- germanium
- Prior art date
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- 239000000463 material Substances 0.000 title claims abstract description 191
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 113
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 112
- 239000004065 semiconductor Substances 0.000 claims abstract description 90
- 239000003989 dielectric material Substances 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims description 68
- 239000002184 metal Substances 0.000 claims description 29
- 229910052751 metal Inorganic materials 0.000 claims description 28
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 claims description 25
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 claims description 23
- 229910044991 metal oxide Inorganic materials 0.000 claims description 21
- 150000004706 metal oxides Chemical class 0.000 claims description 21
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 238000013459 approach Methods 0.000 claims description 12
- VQCBHWLJZDBHOS-UHFFFAOYSA-N erbium(iii) oxide Chemical compound O=[Er]O[Er]=O VQCBHWLJZDBHOS-UHFFFAOYSA-N 0.000 claims description 12
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 11
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 11
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 9
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 8
- 230000003287 optical effect Effects 0.000 claims description 8
- 238000002161 passivation Methods 0.000 claims description 8
- 229910001938 gadolinium oxide Inorganic materials 0.000 claims description 7
- 229940075613 gadolinium oxide Drugs 0.000 claims description 7
- CMIHHWBVHJVIGI-UHFFFAOYSA-N gadolinium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[Gd+3].[Gd+3] CMIHHWBVHJVIGI-UHFFFAOYSA-N 0.000 claims description 7
- 239000000203 mixture Substances 0.000 claims description 7
- FRWYFWZENXDZMU-UHFFFAOYSA-N 2-iodoquinoline Chemical compound C1=CC=CC2=NC(I)=CC=C21 FRWYFWZENXDZMU-UHFFFAOYSA-N 0.000 claims description 6
- WZECUPJJEIXUKY-UHFFFAOYSA-N [O-2].[O-2].[O-2].[U+6] Chemical compound [O-2].[O-2].[O-2].[U+6] WZECUPJJEIXUKY-UHFFFAOYSA-N 0.000 claims description 6
- LTPBRCUWZOMYOC-UHFFFAOYSA-N beryllium oxide Inorganic materials O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 claims description 6
- 229910003440 dysprosium oxide Inorganic materials 0.000 claims description 6
- NLQFUUYNQFMIJW-UHFFFAOYSA-N dysprosium(iii) oxide Chemical compound O=[Dy]O[Dy]=O NLQFUUYNQFMIJW-UHFFFAOYSA-N 0.000 claims description 6
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 claims description 6
- ZCUFMDLYAMJYST-UHFFFAOYSA-N thorium dioxide Chemical compound O=[Th]=O ZCUFMDLYAMJYST-UHFFFAOYSA-N 0.000 claims description 6
- 229910003452 thorium oxide Inorganic materials 0.000 claims description 6
- 229910000439 uranium oxide Inorganic materials 0.000 claims description 6
- 239000012212 insulator Substances 0.000 claims description 4
- 229910052726 zirconium Inorganic materials 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims 2
- 229910052799 carbon Inorganic materials 0.000 claims 2
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims 1
- 239000007769 metal material Substances 0.000 claims 1
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 12
- 239000000377 silicon dioxide Substances 0.000 abstract description 5
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 4
- 229910052681 coesite Inorganic materials 0.000 abstract description 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 2
- 229910052682 stishovite Inorganic materials 0.000 abstract description 2
- 229910052905 tridymite Inorganic materials 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 117
- 239000010408 film Substances 0.000 description 7
- 229910052914 metal silicate Inorganic materials 0.000 description 7
- 238000000137 annealing Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 230000004044 response Effects 0.000 description 4
- 229910005823 GeOy Inorganic materials 0.000 description 3
- -1 HfO2) Chemical compound 0.000 description 3
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000005286 illumination Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910052768 actinide Inorganic materials 0.000 description 1
- 150000001255 actinides Chemical class 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 238000003877 atomic layer epitaxy Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000007123 defense Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 229910052747 lanthanoid Inorganic materials 0.000 description 1
- 150000002602 lanthanoids Chemical class 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 150000002978 peroxides Chemical class 0.000 description 1
- 238000010587 phase diagram Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 description 1
- 150000004760 silicates Chemical class 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229910000314 transition metal oxide Inorganic materials 0.000 description 1
Classifications
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
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- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Definitions
- the present invention is directed to electronic semiconductor devices and, more specifically, to electronic semiconductor devices having capacitive structures with ultra-thin, high-permittivity (high- ⁇ ) dielectric layers.
- IGFET insulated-gate field-effect transistors
- a gate controls an underlying surface channel joining a source and a drain.
- the channel, source and drain are typically located in a semiconductor substrate material, with the source and drain being doped oppositely to the substrate material and located on either side of the channel.
- the gate is separated from the semiconductor substrate material by a thin insulating layer such as a gate oxide having a substantially uniform thickness.
- an input voltage is applied to its gate and, through the capacitive structure defined by the electrode material on either side of the gate oxide, this input voltage causes a transverse electric field in the channel. This field then modulates the longitudinal conductance of the channel to electrically couple source and drain regions.
- One advantage is the ability to increase the number of individual devices that can be placed onto a single silicon chip or die without increasing its relative size. Also, increasing the number of individual devices, especially IGFETs, leads to increased functionality. Yet another advantage is increased speed of the individual devices as well as their collective arrangements.
- MOS-type metal-oxide-semiconductor
- planar bulk Si-MOS structures is beginning to face limits to this continued progress.
- the extent to which the semiconductor industry can drive this scaling of silicon-based IGFET devices is unknown, but there is agreement that the current rate of technology evolution permits only about 4 more technological- advancement nodes of this "classical" silicon-based approach.
- Germanium Because of its very high carrier mobility.
- researchers have been trying to build MOS- type transistors and capacitors using Germanium (Ge) and silicon-Germanium (SiGe) for integrated electronic and/or optical circuit applications, due to some of its superior qualities to silicon (Si).
- Ge Germanium
- SiGe silicon-Germanium
- various problems with Ge or SiGe have frustrated these efforts. For example, the lack of a sufficiently stable native oxide for the Ge has undermined the ability to passivate the Ge or SiGe surface and form a gate dielectric material for MOS-type devices.
- the present invention is directed to the above and related types of circuit devices and their manufacture in which capacitive-like structures having a substrate- type material that avoids significant levels of unstable native oxides from undermining the thermodynamic stability between the substrate-type material and an adjacently- formed high- ⁇ dielectric that is selected to be thermodynamically stable with the substrate-type material.
- capacitive-like structures having a substrate- type material that avoids significant levels of unstable native oxides from undermining the thermodynamic stability between the substrate-type material and an adjacently- formed high- ⁇ dielectric that is selected to be thermodynamically stable with the substrate-type material.
- capacitance-based equivalent SiO 2 thickness (“To x ,Eq") of less than 10 Angstroms and in other instances less than 5 Angstroms.
- the present invention is exemplified in a number of implementations and applications, some of which are summarized below.
- a semiconductor electronics device includes a Germanium-based (Ge-based) surface material having a composition that is preponderantly Germanium, and a dielectric layer having a relatively thin Tox.Eq-
- the dielectric layer is less than 10 Angstroms To x , Eq and, in other embodiments, less than 5 Angstroms To x ,E -
- a semiconductor electronics device in another example embodiment of the present invention, includes a capacitive structure having first and second electrode layers on either side of a dielectric layer.
- the first electrode using, e.g., metal or a semiconductor-like material such as heavily-doped polysilicon, provides a gate or control node to the capacitive structure.
- the second electrode layer for the capacitive structure includes a Ge-rich surface material facing the first electrode layer, and the dielectric layer has a thickness that is sufficient to passivate the Ge-rich surface material (e.g., less than about 10 Angstroms T 0x , Eq ) and includes a i-k dielectric surface material that faces, lies against and is thermodynamically stable with the Ge- rich surface material).
- this capacitive structure includes, among others, laser-diode devices for applications such as optical-electronics, IGFETs, DRAM storage capacitors, and discrete capacitors.
- Other example embodiments of the present invention are directed to methods of manufacturing the above structures.
- One such embodiment involves passivating the Germanium surface, for example, by removing unstable native oxides of Germanium and then depositing a high- ⁇ dielectric on the Ge surface.
- Another related embodiment involves converting Germanium oxide at the surface to a stable form. In the latter approach, unstable Germanium-based oxides are converted to a stable form by combining them with a high- ⁇ dielectric such that the resulting material is thermodynamically stable with Germanium and therefore can be used, for example, as an IGFET gate dielectric material.
- FIG. 1 is capacitive structure with upper and lower conductive layers on opposite sides of a stable, high- ⁇ dielectric layer, according to an example embodiment of the present invention
- FIGs. 2A and 2B show a semiconductor device with a high- ⁇ dielectric material between a gate and a Ge-rich substrate material undergoing manufacture, according to another example embodiment of the present invention
- FIGs. 2C and 2D show a semiconductor device with a high- ⁇ dielectric material being formed on a Ge-rich substrate material, according to another example embodiment of the present invention
- FIGs. 3 A and 3B show a semiconductor device with a high- ⁇ dielectric material between a gate and a Ge-rich substrate material undergoing manufacture using metal oxides deposition on Germanium surface oxides, according to another example embodiment of the present invention
- FIGs. 4A and 4B show a semiconductor device with a high- ⁇ dielectric material between a gate and a Ge-rich substrate material undergoing manufacture using metal deposition on Germanium surface oxides, according to another example embodiment of the present invention
- FIGs. 5A and 5B show a semiconductor device with a high- ⁇ dielectric material between a gate and a Ge-rich substrate material undergoing ion implantation self-aligned to the gate, according to another example embodiment of the present invention
- FIG. 6 is a semiconductor device with a high- ⁇ dielectric material, including metal silicates and germanates, between a gate and a Ge-rich material, according to another example embodiment of the present invention
- FIG. 7 is a MOS device with a high- ⁇ dielectric material between a gate and a Ge-rich substrate material, according to another example embodiment of the present invention.
- FIG. 8 is a Germanium-on-insulator (GOI) MOSFET device with a high- ⁇ dielectric material between a gate and a Germanium substrate material, according to another example embodiment of the present invention.
- GOI Germanium-on-insulator
- FIG. 9 is a Germanium-based thin-film transistor (TFT) device with a high- ⁇ dielectric material between a gate and a Germanium substrate material, according to another example embodiment of the present invention.
- TFT thin-film transistor
- FIG. 10 is a Germanium-based transistor device with a thin channel region in a FinFET structure and having a high- ⁇ dielectric material between a gate and a Ge-rich substrate material, according to another example embodiment of the present invention.
- FIG. 11 is a Germanium-based double-gate MOSFET device with a high- ⁇ dielectric material between a gate and a Ge-rich substrate material, according to another example embodiment of the present invention.
- FIG. 12 is a Germanium-based vertical transistor device with a high- ⁇ dielectric material between a gate and a Ge-rich substrate material, according to another example embodiment of the present invention.
- FIG. 13 is a Germanium-based Schottky MOSFET device with a high- ⁇ dielectric material between a gate and a Ge-rich substrate material, according to another example embodiment of the present invention
- FIG. 14A is a Germanium-based metal-semiconductor-metal (MSM) photodetector with a high- ⁇ dielectric material on opposing sides of a Ge-rich substrate material, according to another example embodiment of the present invention
- FIG. 14B is a Germanium-based PIN photodiode with a high- ⁇ dielectric material on opposing sides of a Ge-rich substrate material, according to another example embodiment of the present invention.
- FIG. 15 is a Germanium-based optical receiver with a high- ⁇ dielectric material between a gate and a Ge-rich substrate material for a TFT and on top of an MSM, according to another example embodiment of the present invention.
- FIG. 16 shows example data including capacitance versus voltage applied to a gate for a semiconductor device with a high- ⁇ dielectric material between a gate and a Germanium substrate material, according to another example embodiment of the present invention.
- a semiconductor circuit includes a capacitive structure having electrode layers surrounding dielectric layer, such as a gate electrode and an IGFET channel that would surround a gate dielectric of a conventional MOSFET or MOSCAP.
- electrode layers surrounding dielectric layer such as a gate electrode and an IGFET channel that would surround a gate dielectric of a conventional MOSFET or MOSCAP.
- an interface between one of the electrode layers and the dielectric layer is unlike such conventional MOS technology.
- the dielectric layer includes a hi-Ar dielectric surface material and the electrode layer includes an electrode surface material that is thermodynamically stable with the hi- ⁇ : dielectric surface material.
- the dielectric layer has a thickness that is not greater than about 10 Angstroms To x,Eq (equivalent oxide thickness).
- the electrode surface material is sufficiently Ge-rich (Germanium rich) so that the interface maintains thermodynamic stability.
- the electrode surface material is a Silicon-rich material, and the process providing the interface is adequately precise to avoid unstable native oxides from interfering with the thermodynamic stability of the material at the interface.
- certain terms used in this patent document are intended to carry certain meanings.
- Capacitive structure refers to nonparasitic capacitance that is specifically designed into the circuit to provide, for example, a capacitance greater than about 32 fF/micron 2 .
- Thermodynamically stable refers to an expected useful circuit life of at least several years, stability through fabrication (including, e.g. , low temperature annealing), and to those structural interfaces that are stable because either the hi-k dielectric surface material is kinetically inhibited relative to the Ge-rich surface material or the structures are thermodynamically stable as indicated in the context of a phase diagram.
- Hi- ⁇ high permittivity refers to a dielectric constant that is at least about 12 (i.e., above aluminum oxide).
- the above- mentioned hi-k dielectric surface material of the dielectric layer is preferably present throughout the dielectric layer to maintain the advantageous characteristics of the hi-A: dielectric while minimizing the To x , E q-
- FIG. 1 illustrates such a capacitive structure 100, according to an example embodiment of the present invention and with upper and lower electrode layers 104 and 102 on opposing sides of a dielectric layer 106.
- the dielectric layer 106 includes a hi-A: dielectric material and the lower electrode layer 102 has an upwardly-directed electrode surface material that is thermodynamically stable with the i-k dielectric material.
- the dielectric layer 106 has a thickness that is not greater than about 10 Angstroms T 0x ,E q (equivalent oxide thickness).
- the dielectric layer can include one or more of a variety of high- ⁇ materials, such as Beryllium oxide, Dysprosium oxide, Erbium oxide, Gadolinium oxide, Hafnium oxide (e.g., HfO2), Lanthanum oxide (e.g., La2O3), Thorium oxide, Uranium oxide, Yttrium oxide and Zirconium oxide (e.g., ZrO2).
- the dielectric layer 106 may also include other transition metal oxides, oxides in the Lanthanide series and/or oxides in the Actinide series.
- the device 100 exhibits properties including high carrier mobility (especially when the electrode layer 102 is Ge-rich) and high permittivity in the dielectric layer 106, which makes the device 100 particularly useful in insulated gate semiconductor applications (e.g., with the lower electrode 102 implemented as a channel region that is readily switched between blocking and conducting states in response to a voltage applied to the upper electrode 104).
- properties including high carrier mobility (especially when the electrode layer 102 is Ge-rich) and high permittivity in the dielectric layer 106 which makes the device 100 particularly useful in insulated gate semiconductor applications (e.g., with the lower electrode 102 implemented as a channel region that is readily switched between blocking and conducting states in response to a voltage applied to the upper electrode 104).
- Various implementations of the capacitive structure include those discussed in connection with the figures below.
- FIGs. 2 A - 4B respectively show cross-sectional views of a capacitive structure being formed using a variety of approaches. As will be addressed in further detail below, each of these approaches is directed to mitigating potential problems due to the presence of unstable surface oxides forming on a Germanium-based substrate material.
- FIGs. 2A and 2B illustrate a semiconductor device being formed with a high- ⁇ dielectric material between a gate and a Germanium substrate material using a deposited layer of stable material.
- FIGs. 2C and 2D show a semiconductor device being formed with unstable surface oxides stripped off a Germanium substrate material and a metal layer deposited thereon.
- FIGs. 3A and 3B illustrate a semiconductor device being formed with a high- ⁇ dielectric material between a gate and a Germanium substrate material using metal oxide deposition on Germanium surface oxides.
- FIGs. 4A and 4B illustrate a semiconductor device being formed with a high- ⁇ dielectric material between a gate and a Germanium substrate material using metal deposition on Germanium surface oxides.
- a high- ⁇ dielectric material is combined with unstable Germanium- based oxides in the dielectric material (e.g., created during annealing of the device). This combination converts the unstable Germanium-based oxides (GeO y ) into a stable form, such that the resulting material is thermodynamically stable with the
- Germanium substrate material Common surface Germanium oxides (e.g., GeO and GeO 2 ) on the Germanium substrate material are rinsed off and/or sublimed via their water solubility and/or volatility. With this approach, unstable Germanium oxides are transformed into a more stable phase (GeOy) and/or to a thermodynamically stable metal germanate (M a Ge b O). Also in connection with this approach, it has been discovered that a stack of metal oxide (MO x ) on the stable GeO y or M a Ge t ,O exhibits a much higher dielectric permittivity than stacks based on conventional materials, such as silicon dioxide for silicon MOS applications that typically exhibit a permittivity (K) of about 3.9. Thus, the converted dielectric material is readily implemented in a variety of applications, including implementation as a MOS gate dielectric material where silicon dioxide has traditionally been used.
- MO x metal oxide
- FIGs. 2A and 2B show a Germanium-based semiconductor device 200 at different stages of manufacture, according to another example embodiment of the present invention.
- unstable surface oxides on a Germanium substrate material 202 have been stripped off and a high- ⁇ layer 203 is deposited thereon.
- the stable layer 203 may include, for example, metal oxide, metal silicate, metal germanate and/or other material that exhibits high permittivity while maintaining thermodynamic stability for an adequate lifetime of use.
- the device 200 is annealed and a portion of or the whole stable layer 203 may react to form a thin layer of different silicates and/or germanates 204, with a thicker portion 206 of the stable layer remaining unchanged.
- the stable layer 203 is completely reacted, with portions 204 and 206 forming one single layer.
- the thickness and composition of the thin layer 204 is such that the device 200 maintains the thermodynamic stability discussed above.
- FIGs. 2C and 2D show a Germanium-based semiconductor device 250 at different stages of manufacture, according to another example embodiment of the present invention.
- unstable surface oxides on a Germanium substrate material 252 have been stripped off and a metal layer 253 is deposited thereon.
- the device 250 is annealed and/or oxidized to form a stable high- ⁇ dielectric layer 254, as shown in FIG. 2D.
- the metal layer 253 is being oxidized to form the high- ⁇ dielectric layer 254.
- the stable high- ⁇ dielectric layer 254 is comprised solely of metal oxide. In another implementation, the stable high- ⁇ dielectric layer 254 includes metal oxide, stable Germanium oxides and/or stable metal germanates. In each of these implementations, the resulting structure exhibits stable thermodynamic behavior, as discussed above.
- FIGs. 3A and 3B show a Germanium-based semiconductor device 300 at different stages of manufacture, according to another example embodiment of the present invention.
- a stable metal oxide layer 305 is deposited on an unstable Germanium oxide layer 303, which is in turn disposed on a Germanium substrate material 302.
- the metal oxide layer 305 may include, for example, oxides of metal, metal silicates and/or metal germanates.
- the device 300 is annealed and/or oxidized to form a stable high- ⁇ dielectric layer 304, leaving a remaining portion 306 of the stable metal oxide layer 305, as shown in FIG. 3B. In one implementation, the remaining portion 306 is consumed by the high- ⁇ dielectric layer 304.
- FIGs. 4 A and 4B also show a Germanium-based semiconductor device 400 at different stages of manufacture, according to another example embodiment of the present invention.
- a metal layer 405 is deposited on an unstable Germanium oxide layer 403, which is in turn disposed on a Germanium substrate material 402.
- the metal layer 405 may include, for example, metals that are susceptible to reactions that form metal oxides that exhibit a stable phase between the metal oxides and Germanium oxides, such as Zr, Hf and La.
- the device 400 is annealed and/or oxidized to form a stable high- ⁇ dielectric layer 404 and, in one implementation, an additional metal oxide layer 406 as shown in FIG. 4B. At least a portion of the metal layer 405 reacts with the unstable Germanium oxide layer 403 to replace and/or react unstable oxides and form the high- ⁇ dielectric layer 404 and a metal oxide layer 406 (e.g., a portion of the metal layer 405 that does not react with the unstable Germanium oxide layer 403 is oxidized to form layer 406).
- the unstable Germanium oxide layer 403 is reacted to form stable Germanium oxides. In another implementation, the unstable Germanium oxide layer 403 is reacted to form stable metal germanates. In each of these implementations, the resulting structure exhibits stable thermodynamic behavior, as discussed above.
- a Germanium substrate material e.g., substrates 102, 202, 252, 302 and 402 may include a pure Germanium wafer or a deposited Germanium film layer on a conventional silicon wafer (e.g., using physical vapor deposition, chemical vapor deposition, atomic layer deposition and/or epitaxy).
- Metal and metal oxide layers may be deposited using one or more of many commonly-available methods, such as sputtering, evaporation and/or chemical vapor deposition.
- the unstable surface Germanium oxide layers (e.g., 303, 403) may include one or more of native, deposited, chemically formed, and/or thermally grown Germanium oxides. Oxidation may be carried out inside any suitable equipment, such as an oxidation furnace, rapid thermal annealer, ultra-violet oxidation chamber and/or a hot pot, with oxidizing ambient environments such as dry/wet oxygen, water, steam, peroxide solutions and/or ozone environments. Annealing may be performed inside one or more of a variety of types of annealing environments, such as in an annealing furnace or rapid thermal annealer, with ambient environments such as a forming gas, inert gases or oxygen.
- the stable dielectric layer 106 may include a stable phase of Germanium oxide, or may be formed by converting unstable Germanium oxide material into stable Germanium nitrides and/or oxynitrides (GeO x N y ). With these approaches, metals and/or metal oxides can be deposited directly on the high- ⁇ dielectric layer 106 to form layer 104. Various other approaches can be used to form the stable dielectric and overlying conductive layers discussed above. In one implementation, and referring again to FIG. 1 as an example, layers 106 and 104 are formed via co-deposition (e.g.
- the layer 106 includes directly deposited metal germanate.
- layer 104 is formed by depositing metal oxide and introducing dopants thereto.
- metal e.g. , Zirconium (Zr)
- Zr Zirconium
- a top electrode layer 104 is then formed on the UV ozone oxidized layer 106, and the capacitive structure 100 is subsequently annealed.
- a high- ⁇ dielectric material such as Zirconium oxide (ZrO 2 ) or Hafnium oxide (HfO 2 ) is deposited on a surface Germanium oxide layer (e.g., between layers 303 and 305) via atomic-layer chemical vapor deposition (ALCVD).
- An upper electrode layer 306 is then deposited on the high- ⁇ dielectric material, followed by an annealing process.
- FIGs. 5A and 5B show an insulated gate field effect transistor (IGFET) at different stages of manufacture, according to another example embodiment of the present invention.
- IGFET insulated gate field effect transistor
- FIG. 5 A a Germanium substrate material 502 and a stable dielectric layer 503 are formed in a manner not inconsistent with one or more of the example embodiments discussed above.
- a gate electrode 505 is patterned from an electrode layer (e.g., by patterning layer 104 of FIG. 1). Dopant ions 520 are directed toward the substrate material 502. As shown in FIG. 5B, the ions 520 implant source/drain regions 522 and 524 that are self-aligned to the gate electrode 505, with a channel region 526 of the substrate material 502 being masked by the gate electrode 505.
- FIG. 6 shows a capacitive structure 600 having a stable dielectric layer 603 on a Germanium substrate material 602 with metal silicates and metal germanates therein, according to another example embodiment of the present invention.
- the dielectric layer 603 may, for example, be implemented in connection with one or more of the example embodiments discussed herein.
- the stable combination of metal silicates and metal germanates is shown in the inset 650, with layer 603 comprising metal germanates and metal silicates 642 and 644, respectively, and with layer 602 comprising Germanium and Silicon atoms 632 and 634, respectively.
- the metal silicates 644 and metal germanates 642 have a mole fraction of about 50% each, without loss of generality.
- the layer 603 may include amorphous, polycrystalline and/or crystalline structures.
- an IGFET-type device 700 includes a stable gate dielectric layer
- the device 700 includes a gate 705 separated from and adapted to capacitively couple to a channel region 726 in the Germanium substrate material 702 via the stable gate dielectric layer 703.
- Source region 722 and drain region 724 are disposed on opposing sides of the channel 726 and in the substrate material 702, with elevated source/drain junctions 716 and 718 over each of source drain regions 722 and 724, respectively.
- Elevated source/drain junctions 716 and 718 are separated from the gate electrode 705 by spacers 707 and 709, respectively, and reduce the resistance of electrical contacts made to each of source/drain regions 722 and 724, respectively.
- FIG. 8 shows an IGFET with a Germanium substrate material region 802 over an insulating layer 841 that form a Germanium-on-insulator (GOI) structure, according to another example embodiment of the present invention.
- the insulating layer 841 e.g., oxide
- a thin layer of silicon 842 separates the Germanium substrate material region 802 from the insulating layer 841.
- a Germanium channel region 826 is disposed in the Germanium substrate material region 802 between doped source and drain regions 822 and 824.
- a stable dielectric material 803 is formed on the channel region 826 and separates the channel region from a gate electrode 805 having insulative spacers 807 and 809 on opposing sides thereof.
- FIG. 9 shows another semiconductor device 900, similar to the device shown in FIG. 8 but without the silicon layer 842, according to another example embodiment of the present invention.
- articles in FIG. 9 that are similar to those in FIG. 8 are similarly labeled.
- the Germanium layer 802 is formed directly on the insulating layer 841, with the resulting structure forming a Germanium-based thin film transistor (TFT).
- TFT Germanium-based thin film transistor
- FIG. 10 shows a FinFET device 1000 employing a Germanium-based channel region 1002 separated from a gate 1005 by a stable dielectric layer 1003, according to another example embodiment of the present invention.
- the FinFET is formed on an insulating layer 1041, with source and drain regions 1022 and 1024 being separated by the Germanium-based channel region 1002.
- FIG. 11 shows a double-gate MOSFET device 1100 employing a Germanium- based substrate material region 1102, according to another example embodiment of the present invention.
- a Germanium-based channel region 1126 is separated from dual gate electrodes 1105 and 1115 by a selected high- ⁇ dielectric material 1103 and 1113.
- the Germanium-based channel region 1126 separates source and drain regions 1122 and 1124 in the substrate material region 1103.
- Insulative spacers 1107 and 1109 are disposed on opposing sides of gate electrode 1105, with insulative spacers 1117 and 1119 similarly disposed on opposing sides of gate electrode 1115.
- FIG. 12 shows a vertical transistor device 1200 employing at least one
- Germanium-based channel region separated from a gate electrode by a selected high- ⁇ dielectric material Germanium-based channel region separated from a gate electrode by a selected high- ⁇ dielectric material, according to another example embodiment of the present invention.
- Source region 1222, having contact 1223, and drain region 1224, having contact 1225 are separated by a silicon oxide region 1242 with the drain region 1224 being disposed on a silicon oxide layer 1241.
- a transistor 1201 includes a channel region 1226 separated from a gate electrode 1205 by a dielectric layer 1203.
- the channel region and dielectric materials for the transistor include germanium and a stable dielectric material, respectively, as discussed in other example embodiments above.
- FIG 13 shows a Schottky source/drain MOSFET device 1300 having a Germanium-based substrate material region 1302 disposed on an insulating layer 1341, according to another example embodiment of the present invention.
- the Germanium-based substrate material region 1302 includes a Germanium-based channel region 1326 that separates source and drain regions 1322 and 1324, respectively.
- a stable dielectric material 1303 separates the Germanium-based channel region 1326 from a gate electrode 1305 having a conductive contact material 1311 formed thereon and insulative sidewall spacers 1307 and 1309 on opposite sides thereof.
- FIG. 14A is a Germanium-based metal-semiconductor-metal (MSM)-type photodetector 1400, according to another example embodiment of the present invention.
- MSM Germanium-based metal-semiconductor-metal
- the MSM-type structure includes an intrinsic Germanium substrate material region 1402 disposed between upper and lower conductive contacts 1421 and 1423.
- High- ⁇ passivation layers 1413 and 1403 are disposed on opposing sides of the intrinsic Germanium region 1402.
- Light 1460 incident upon the photodetector 1400 is absorbed in the intrinsic Germanium substrate material region 1402 and causes electron-hole pair generation, which in turn results in current flow in the MSM photodetector 1400 between the upper and lower electrodes 1421 and 1423.
- the current flow in the MSM photodetector 1400 can be used to detect the incident light, as well as characteristics thereof.
- FIG. 14B is a Germanium-based p+ doped/intrinsic/n+ doped (PIN) photodiode 1450, according to another example embodiment of the present invention.
- the PIN photodiode 1450 includes an intrinsic Ge-rich substrate material region 1412 disposed between an n-doped Germanium region 1422 and a p-doped Germanium region 1424.
- 1422 is a p-type region and 1424 is an n-type region.
- High- ⁇ passivation layers 1411 and 1414 are disposed on opposing sides of the intrinsic Germanium substrate material region 1412, with conductive contact regions 1425 and 1426 being electrically coupled to the n-doped Germanium region 1422 and conductive contact region 1427 being coupled to the p-doped Germanium region 1424.
- Light 1461 incident upon the photodetector 1450 is absorbed in the intrinsic Ge-rich substrate material region 1412 and causes electron- hole pair generation, which in turn affects current flow in the PIN photodiode 1450 between the conductive contact regions 1425 and 1426 and the conductive contact region 1427.
- the current flow in the PIN photodiode 1450 can be used to detect the incident light, as well as characteristics thereof.
- dark current e.g., current flow in the absence of the light illumination 1460 or 1461
- a current signal from the MSM photodetector 1400 or the PIN photodiode 1450 includes relatively low noise.
- the resulting cu ⁇ ent signal representing the detected light has a very high signal-to-noise ratio.
- These devices 1400 and 1450 are particularly useful for use in a highly dense array of such devices for detecting infrared (IR) light, due to the ability of the intrinsic Germanium-based substrate materials 1402 and 1412 to readily absorb the IR light.
- IR infrared
- Such high- ⁇ passivation layers can be implemented as discussed above, for example, in connection with FIGs. 2C and 2D.
- FIG. 15 shows a Germanium-based monolithically integrated optical receiver 1500, according to another example embodiment of the present invention.
- the optical receiver 1500 includes a Germanium-based photodetector 1510 and a Germanium- based TFT 1520, similar to the devices shown in FIGs. 9 and 14A, respectively.
- the device 1500 includes a Silicon substrate 1501 with an inter-layer dielectric (ILD) layer 1541 having a high- ⁇ dielectric material disposed thereon.
- An amorphous Germanium-based substrate film 1502 (formed, e.g., using low-pressure chemical vapor deposition at about 300 degrees Celsius), is disposed on the ILD layer 1541.
- Portions 1547, 1543 and 1545 of the amorphous Germanium-based substrate film 1502 have been replaced with an insulative material, such as Silicon dioxide, and portions 1522 and 1524 have been doped to form source/drain regions for the TFT 1520.
- Portions 1540 and 1526 of the amorphous Germanium-based substrate film 1502 have been crystallized using, for example, metal induced lateral crystallization at a relatively low temperature (e.g., forming an intrinsic material 1540 for the photodetector 1510 and a channel region 1526 for the TFT 1520).
- a high- ⁇ dielectric material 1542 is disposed on the crystallized Germanium portion 1540 of the
- Conductive materials 1562 and 1560 are in electrical contact with the crystallized Germanium portion 1540.
- electrons and holes generated in the crystallized Germanium portion 1540 effect current flow between the conductive materials 1562 and 1560.
- Germanium-based TFT 1520 a high- ⁇ dielectric film having portions 1511, 1503 and 1512 disposed thereon and separated by conductive material portions 1560 and 1561.
- a Germanium-based conductive electrode 1506 is disposed on high- ⁇ dielectric material portion 1503, an insulative material 1507, 1509 and 1508 is disposed on each of high- ⁇ dielectric film portions 1511, 1503 and 1512, respectively.
- Cu ⁇ ent generated in the crystallized Germanium portion 1540 is electrically coupled to the conductive material 1561 via source/drain regions 1522 and 1524, with a conductive channel being formed that channel region 1526 in response to a voltage applied to the conductive electrode 1506.
- FIG. 16 shows an example capacitance versus voltage curve 1600 as applied to a gate for a semiconductor device having a high- ⁇ dielectric material between a gate and a Germanium-based substrate material, according to another example embodiment of the present invention.
- a voltage applied to the upper electrode 104 is shown on the horizontal axis, with the resulting capacitance via the dielectric material to the lower electrode 102 shown on the vertical axis.
- an inset example capacitive structure 1660 shows an upper electrode including platinum 1604 disposed on a high- ⁇ insulative dielectric material 1606 on an N-doped germanium substrate material 1602.
- the resulting curve 1600 shows hysteresis estimation with a gate voltage (V g ) of about 1.5 mV causing a change in capacitance at about 400kHz.
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Abstract
Excellent capacitor-voltage characteristics with near-ideal hysteresis are realized in a capacitive-like structure that uses an electrode substrate-type material with a hi-k dielectric layer having a thickness of a few-to-several Angstroms capacitance-based SiO2 equivalent ('TOX,Eq'). According to one particular example embodiment, a semiconductor device structure has an electrode substrate-type material having a Germanium-rich surface material. The electrode substrate-type material is processed to provide this particular electrode surface material in a form that is thermodynamically stable with a hi-k dielectric material. A dielectric layer is then formed over the electrode surface material with the hi-k dielectric material at a surface that faces, lies against and is thermodynamically stable with the electrode surface material.
Description
HIGH-K DIELECTRIC FOR THERMODYNAMICALLY-STABLE SUBSTRATE-TYPE MATERIALS
Federally Sponsored Research or Development
This invention was made with Government support under contract MDA 972-00-1-0013 awarded by NIH U.S. Department of Defense/ Advanced Research Projects Agency. The U.S. Government has certain rights in this invention.
Field of the Invention
The present invention is directed to electronic semiconductor devices and, more specifically, to electronic semiconductor devices having capacitive structures with ultra-thin, high-permittivity (high-κ) dielectric layers.
Background
Various types of electronic semiconductor devices employ capacitive structures to effect proper circuit operation. Examples of such devices include, among others, insulated-gate field-effect transistors (IGFETs), insulated-gate thyristors, discrete capacitors and various types of optics devices. In the commonly- used IGFET, for example, a gate controls an underlying surface channel joining a source and a drain. The channel, source and drain are typically located in a semiconductor substrate material, with the source and drain being doped oppositely to the substrate material and located on either side of the channel. The gate is separated from the semiconductor substrate material by a thin insulating layer such as a gate oxide having a substantially uniform thickness. To operate the IGFET, an input voltage is applied to its gate and, through the capacitive structure defined by the electrode material on either side of the gate oxide, this input voltage causes a transverse electric field in the channel. This field then modulates the longitudinal conductance of the channel to electrically couple source and drain regions.
Various advantages can be realized by reducing the dimensions of such electronic semiconductor devices. One advantage is the ability to increase the number of individual devices that can be placed onto a single silicon chip or die without
increasing its relative size. Also, increasing the number of individual devices, especially IGFETs, leads to increased functionality. Yet another advantage is increased speed of the individual devices as well as their collective arrangements. For decades now, the semiconductor industry has been realizing these size- reduction advantages using silicon substrates at a tremendous rate, as exemplified by the electrical performance of MOS-type (metal-oxide-semiconductor) silicon-based IGFETs doubling every 2 to 3 years. However, the International Technology Roadmap for Semiconductors (ITRS) notes that "traditional scaling" of such silicon- based IGFETs (e.g. , planar bulk Si-MOS structures) is beginning to face limits to this continued progress. The extent to which the semiconductor industry can drive this scaling of silicon-based IGFET devices is unknown, but there is agreement that the current rate of technology evolution permits only about 4 more technological- advancement nodes of this "classical" silicon-based approach.
Scaling to 4 more technology nodes would lead to effective feature sizes of approximately 20 - 30 nm. However, achieving even this objective would require significant technological breakthroughs. Beyond this point, there is generally industry-wide agreement that traditional silicon-based IGFET technology would likely have to be replaced by future innovations, including new materials and devices. As such, an entirely new and different era and area of technology would have to be introduced.
One such very promising material is Germanium (Ge) because of its very high carrier mobility. In the past few decades, researchers have been trying to build MOS- type transistors and capacitors using Germanium (Ge) and silicon-Germanium (SiGe) for integrated electronic and/or optical circuit applications, due to some of its superior qualities to silicon (Si). However, various problems with Ge or SiGe have frustrated these efforts. For example, the lack of a sufficiently stable native oxide for the Ge has undermined the ability to passivate the Ge or SiGe surface and form a gate dielectric material for MOS-type devices.
Summary
The present invention is directed to the above and related types of circuit devices and their manufacture in which capacitive-like structures having a substrate-
type material that avoids significant levels of unstable native oxides from undermining the thermodynamic stability between the substrate-type material and an adjacently- formed high-κ dielectric that is selected to be thermodynamically stable with the substrate-type material. In connection with one aspect of the present invention, it has been discovered that excellent capacitor-voltage characteristics with near-ideal hysteresis can be realized in such a structure with a capacitance-based equivalent SiO2 thickness ("Tox,Eq") of less than 10 Angstroms and in other instances less than 5 Angstroms.
The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a semiconductor electronics device includes a Germanium-based (Ge-based) surface material having a composition that is preponderantly Germanium, and a dielectric layer having a relatively thin Tox.Eq- The hi-A: dielectric surface material faces, lies against and is thermodynamically stable with the Ge-based surface material. In certain specific embodiments, the dielectric layer is less than 10 Angstroms Tox,Eq and, in other embodiments, less than 5 Angstroms Tox,E -
In another example embodiment of the present invention, a semiconductor electronics device includes a capacitive structure having first and second electrode layers on either side of a dielectric layer. The first electrode, using, e.g., metal or a semiconductor-like material such as heavily-doped polysilicon, provides a gate or control node to the capacitive structure. The second electrode layer for the capacitive structure includes a Ge-rich surface material facing the first electrode layer, and the dielectric layer has a thickness that is sufficient to passivate the Ge-rich surface material (e.g., less than about 10 Angstroms T0x,Eq) and includes a i-k dielectric surface material that faces, lies against and is thermodynamically stable with the Ge- rich surface material). Specific example implementations of this capacitive structure include, among others, laser-diode devices for applications such as optical-electronics, IGFETs, DRAM storage capacitors, and discrete capacitors. Other example embodiments of the present invention are directed to methods of manufacturing the above structures. One such embodiment involves passivating the Germanium surface, for example, by removing unstable native oxides of
Germanium and then depositing a high-κ dielectric on the Ge surface. Another related embodiment involves converting Germanium oxide at the surface to a stable form. In the latter approach, unstable Germanium-based oxides are converted to a stable form by combining them with a high-κ dielectric such that the resulting material is thermodynamically stable with Germanium and therefore can be used, for example, as an IGFET gate dielectric material.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.
Brief Description of the Drawings
The invention may be more completely understood in consideration of the detailed description of various embodiments of the invention in connection with the accompanying drawings, in which: FIG. 1 is capacitive structure with upper and lower conductive layers on opposite sides of a stable, high-κ dielectric layer, according to an example embodiment of the present invention;
FIGs. 2A and 2B show a semiconductor device with a high-κ dielectric material between a gate and a Ge-rich substrate material undergoing manufacture, according to another example embodiment of the present invention;
FIGs. 2C and 2D show a semiconductor device with a high-κ dielectric material being formed on a Ge-rich substrate material, according to another example embodiment of the present invention;
FIGs. 3 A and 3B show a semiconductor device with a high-κ dielectric material between a gate and a Ge-rich substrate material undergoing manufacture using metal oxides deposition on Germanium surface oxides, according to another example embodiment of the present invention;
FIGs. 4A and 4B show a semiconductor device with a high-κ dielectric material between a gate and a Ge-rich substrate material undergoing manufacture using metal deposition on Germanium surface oxides, according to another example embodiment of the present invention;
FIGs. 5A and 5B show a semiconductor device with a high-κ dielectric material between a gate and a Ge-rich substrate material undergoing ion implantation self-aligned to the gate, according to another example embodiment of the present invention; FIG. 6 is a semiconductor device with a high-κ dielectric material, including metal silicates and germanates, between a gate and a Ge-rich material, according to another example embodiment of the present invention;
FIG. 7 is a MOS device with a high-κ dielectric material between a gate and a Ge-rich substrate material, according to another example embodiment of the present invention;
FIG. 8 is a Germanium-on-insulator (GOI) MOSFET device with a high-κ dielectric material between a gate and a Germanium substrate material, according to another example embodiment of the present invention;
FIG. 9 is a Germanium-based thin-film transistor (TFT) device with a high-κ dielectric material between a gate and a Germanium substrate material, according to another example embodiment of the present invention;
FIG. 10 is a Germanium-based transistor device with a thin channel region in a FinFET structure and having a high-κ dielectric material between a gate and a Ge-rich substrate material, according to another example embodiment of the present invention;
FIG. 11 is a Germanium-based double-gate MOSFET device with a high-κ dielectric material between a gate and a Ge-rich substrate material, according to another example embodiment of the present invention;
FIG. 12 is a Germanium-based vertical transistor device with a high-κ dielectric material between a gate and a Ge-rich substrate material, according to another example embodiment of the present invention;
FIG. 13 is a Germanium-based Schottky MOSFET device with a high-κ dielectric material between a gate and a Ge-rich substrate material, according to another example embodiment of the present invention; FIG. 14A is a Germanium-based metal-semiconductor-metal (MSM) photodetector with a high-κ dielectric material on opposing sides of a Ge-rich
substrate material, according to another example embodiment of the present invention;
FIG. 14B is a Germanium-based PIN photodiode with a high-κ dielectric material on opposing sides of a Ge-rich substrate material, according to another example embodiment of the present invention;
FIG. 15 is a Germanium-based optical receiver with a high-κ dielectric material between a gate and a Ge-rich substrate material for a TFT and on top of an MSM, according to another example embodiment of the present invention; and
FIG. 16 shows example data including capacitance versus voltage applied to a gate for a semiconductor device with a high-κ dielectric material between a gate and a Germanium substrate material, according to another example embodiment of the present invention.
While the invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not necessarily to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Detailed Description
The present invention is believed to be applicable to a variety of different types of circuit applications benefiting from ultra-thin high-κ dielectric capacitive structures, and has been found to be particularly useful for semiconductor circuits employing Germanium-based substrate materials. While the present invention is not necessarily limited to such circuit types, various aspects of the invention may be appreciated through a discussion of various examples using this context. According to an example embodiment of the present invention, a semiconductor circuit includes a capacitive structure having electrode layers surrounding dielectric layer, such as a gate electrode and an IGFET channel that would surround a gate dielectric of a conventional MOSFET or MOSCAP. However, an interface between one of the electrode layers and the dielectric layer is unlike such conventional MOS technology. At this interface, the dielectric layer includes a hi-Ar
dielectric surface material and the electrode layer includes an electrode surface material that is thermodynamically stable with the hi-λ: dielectric surface material. The dielectric layer has a thickness that is not greater than about 10 Angstroms Tox,Eq (equivalent oxide thickness). In one implementation, the electrode surface material is sufficiently Ge-rich (Germanium rich) so that the interface maintains thermodynamic stability. In another implementation, the electrode surface material is a Silicon-rich material, and the process providing the interface is adequately precise to avoid unstable native oxides from interfering with the thermodynamic stability of the material at the interface. For the sake of brevity, unless otherwise indicated, certain terms used in this patent document are intended to carry certain meanings. "Capacitive structure" refers to nonparasitic capacitance that is specifically designed into the circuit to provide, for example, a capacitance greater than about 32 fF/micron2. "Thermodynamically stable" refers to an expected useful circuit life of at least several years, stability through fabrication (including, e.g. , low temperature annealing), and to those structural interfaces that are stable because either the hi-k dielectric surface material is kinetically inhibited relative to the Ge-rich surface material or the structures are thermodynamically stable as indicated in the context of a phase diagram. "Hi-κ" (high permittivity) refers to a dielectric constant that is at least about 12 (i.e., above aluminum oxide). Further, in view of the various applications and example embodiments to be described below, it will be appreciated that the term "substrate material" is not necessarily limited to fundamental structures from which semiconductor materials are built.
In a more particular example embodiment of the present invention, the above- mentioned hi-k dielectric surface material of the dielectric layer is preferably present throughout the dielectric layer to maintain the advantageous characteristics of the hi-A: dielectric while minimizing the Tox,Eq-
In one implementation, the present invention is directed to the manufacture of the above type of capacitive structure. FIG. 1 illustrates such a capacitive structure 100, according to an example embodiment of the present invention and with upper and lower electrode layers 104 and 102 on opposing sides of a dielectric layer 106. The dielectric layer 106 includes a hi-A: dielectric material and the lower electrode
layer 102 has an upwardly-directed electrode surface material that is thermodynamically stable with the i-k dielectric material. The dielectric layer 106 has a thickness that is not greater than about 10 Angstroms T0x,Eq (equivalent oxide thickness). For example, using a Ge-rich material for layer 102, the dielectric layer can include one or more of a variety of high-κ materials, such as Beryllium oxide, Dysprosium oxide, Erbium oxide, Gadolinium oxide, Hafnium oxide (e.g., HfO2), Lanthanum oxide (e.g., La2O3), Thorium oxide, Uranium oxide, Yttrium oxide and Zirconium oxide (e.g., ZrO2). The dielectric layer 106 may also include other transition metal oxides, oxides in the Lanthanide series and/or oxides in the Actinide series. With this approach, the device 100 exhibits properties including high carrier mobility (especially when the electrode layer 102 is Ge-rich) and high permittivity in the dielectric layer 106, which makes the device 100 particularly useful in insulated gate semiconductor applications (e.g., with the lower electrode 102 implemented as a channel region that is readily switched between blocking and conducting states in response to a voltage applied to the upper electrode 104). Various implementations of the capacitive structure include those discussed in connection with the figures below.
Also according to the present invention, FIGs. 2 A - 4B respectively show cross-sectional views of a capacitive structure being formed using a variety of approaches. As will be addressed in further detail below, each of these approaches is directed to mitigating potential problems due to the presence of unstable surface oxides forming on a Germanium-based substrate material. FIGs. 2A and 2B illustrate a semiconductor device being formed with a high-κ dielectric material between a gate and a Germanium substrate material using a deposited layer of stable material. FIGs. 2C and 2D show a semiconductor device being formed with unstable surface oxides stripped off a Germanium substrate material and a metal layer deposited thereon. FIGs. 3A and 3B illustrate a semiconductor device being formed with a high-κ dielectric material between a gate and a Germanium substrate material using metal oxide deposition on Germanium surface oxides. FIGs. 4A and 4B illustrate a semiconductor device being formed with a high-κ dielectric material between a gate and a Germanium substrate material using metal deposition on Germanium surface oxides.
In a more particular implementation of the above-discussed example embodiments, a high-κ dielectric material is combined with unstable Germanium- based oxides in the dielectric material (e.g., created during annealing of the device). This combination converts the unstable Germanium-based oxides (GeOy) into a stable form, such that the resulting material is thermodynamically stable with the
Germanium substrate material. Common surface Germanium oxides (e.g., GeO and GeO2) on the Germanium substrate material are rinsed off and/or sublimed via their water solubility and/or volatility. With this approach, unstable Germanium oxides are transformed into a more stable phase (GeOy) and/or to a thermodynamically stable metal germanate (MaGebO). Also in connection with this approach, it has been discovered that a stack of metal oxide (MOx) on the stable GeOy or MaGet,O exhibits a much higher dielectric permittivity than stacks based on conventional materials, such as silicon dioxide for silicon MOS applications that typically exhibit a permittivity (K) of about 3.9. Thus, the converted dielectric material is readily implemented in a variety of applications, including implementation as a MOS gate dielectric material where silicon dioxide has traditionally been used.
FIGs. 2A and 2B show a Germanium-based semiconductor device 200 at different stages of manufacture, according to another example embodiment of the present invention. In FIG. 2A, unstable surface oxides on a Germanium substrate material 202 have been stripped off and a high-κ layer 203 is deposited thereon. The stable layer 203 may include, for example, metal oxide, metal silicate, metal germanate and/or other material that exhibits high permittivity while maintaining thermodynamic stability for an adequate lifetime of use. In Fig. 2B, the device 200 is annealed and a portion of or the whole stable layer 203 may react to form a thin layer of different silicates and/or germanates 204, with a thicker portion 206 of the stable layer remaining unchanged. In one implementation, the stable layer 203 is completely reacted, with portions 204 and 206 forming one single layer. The thickness and composition of the thin layer 204 is such that the device 200 maintains the thermodynamic stability discussed above. FIGs. 2C and 2D show a Germanium-based semiconductor device 250 at different stages of manufacture, according to another example embodiment of the present invention. In FIG. 2C, unstable surface oxides on a Germanium substrate
material 252 have been stripped off and a metal layer 253 is deposited thereon. The device 250 is annealed and/or oxidized to form a stable high-κ dielectric layer 254, as shown in FIG. 2D. Specifically, the metal layer 253 is being oxidized to form the high-κ dielectric layer 254. In one implementation, the stable high-κ dielectric layer 254 is comprised solely of metal oxide. In another implementation, the stable high-κ dielectric layer 254 includes metal oxide, stable Germanium oxides and/or stable metal germanates. In each of these implementations, the resulting structure exhibits stable thermodynamic behavior, as discussed above.
FIGs. 3A and 3B show a Germanium-based semiconductor device 300 at different stages of manufacture, according to another example embodiment of the present invention. In FIG. 3 A, a stable metal oxide layer 305 is deposited on an unstable Germanium oxide layer 303, which is in turn disposed on a Germanium substrate material 302. The metal oxide layer 305 may include, for example, oxides of metal, metal silicates and/or metal germanates. The device 300 is annealed and/or oxidized to form a stable high-κ dielectric layer 304, leaving a remaining portion 306 of the stable metal oxide layer 305, as shown in FIG. 3B. In one implementation, the remaining portion 306 is consumed by the high-κ dielectric layer 304. Specifically, a portion of the metal oxide layer 305 reacts with the unstable Germanium oxide layer 303 to replace and/or react unstable oxides and form the high-κ dielectric layer 304. In one implementation, the unstable Germanium oxide layer 303 is reacted to form stable Germanium oxides. In another implementation, the unstable Germanium oxide layer 303 is reacted to form stable metal germanates. In each of these implementations, the resulting structure exhibits stable thermodynamic behavior, as discussed above. FIGs. 4 A and 4B also show a Germanium-based semiconductor device 400 at different stages of manufacture, according to another example embodiment of the present invention. In FIG. 4A, a metal layer 405 is deposited on an unstable Germanium oxide layer 403, which is in turn disposed on a Germanium substrate material 402. The metal layer 405 may include, for example, metals that are susceptible to reactions that form metal oxides that exhibit a stable phase between the metal oxides and Germanium oxides, such as Zr, Hf and La. The device 400 is annealed and/or oxidized to form a stable high-κ dielectric layer 404 and, in one
implementation, an additional metal oxide layer 406 as shown in FIG. 4B. At least a portion of the metal layer 405 reacts with the unstable Germanium oxide layer 403 to replace and/or react unstable oxides and form the high-κ dielectric layer 404 and a metal oxide layer 406 (e.g., a portion of the metal layer 405 that does not react with the unstable Germanium oxide layer 403 is oxidized to form layer 406). In one implementation, the unstable Germanium oxide layer 403 is reacted to form stable Germanium oxides. In another implementation, the unstable Germanium oxide layer 403 is reacted to form stable metal germanates. In each of these implementations, the resulting structure exhibits stable thermodynamic behavior, as discussed above. The above example embodiments may be implemented in a variety of additional manners. For instance, a Germanium substrate material (e.g., substrates 102, 202, 252, 302 and 402) may include a pure Germanium wafer or a deposited Germanium film layer on a conventional silicon wafer (e.g., using physical vapor deposition, chemical vapor deposition, atomic layer deposition and/or epitaxy). Metal and metal oxide layers (e.g., layers 104, 203, 253, 305 and 405) may be deposited using one or more of many commonly-available methods, such as sputtering, evaporation and/or chemical vapor deposition. The unstable surface Germanium oxide layers (e.g., 303, 403) may include one or more of native, deposited, chemically formed, and/or thermally grown Germanium oxides. Oxidation may be carried out inside any suitable equipment, such as an oxidation furnace, rapid thermal annealer, ultra-violet oxidation chamber and/or a hot pot, with oxidizing ambient environments such as dry/wet oxygen, water, steam, peroxide solutions and/or ozone environments. Annealing may be performed inside one or more of a variety of types of annealing environments, such as in an annealing furnace or rapid thermal annealer, with ambient environments such as a forming gas, inert gases or oxygen.
A variety of other modifications and/or additions can be applied in connection with the example embodiments discussed above. Referring to FIG. 1 as an example, the stable dielectric layer 106 may include a stable phase of Germanium oxide, or may be formed by converting unstable Germanium oxide material into stable Germanium nitrides and/or oxynitrides (GeOxNy). With these approaches, metals and/or metal oxides can be deposited directly on the high-κ dielectric layer 106 to form layer 104.
Various other approaches can be used to form the stable dielectric and overlying conductive layers discussed above. In one implementation, and referring again to FIG. 1 as an example, layers 106 and 104 are formed via co-deposition (e.g. sputtering or CVD) of different metals and/or metal oxides, as well as Germanium and/or Germanium oxides, respectively. In another implementation, the layer 106 includes directly deposited metal germanate. In another implementation, layer 104 is formed by depositing metal oxide and introducing dopants thereto. In connection with still another implementation, it has been discovered that metal (e.g. , Zirconium (Zr)) can be sputtered directly on a Germanium wafer (102), followed by ultraviolet (UV) ozone oxidation to form layer 106. A top electrode layer 104 is then formed on the UV ozone oxidized layer 106, and the capacitive structure 100 is subsequently annealed.
In another implementation, using FIG. 3 as an example, a high-κ dielectric material, such as Zirconium oxide (ZrO2) or Hafnium oxide (HfO2), is deposited on a surface Germanium oxide layer (e.g., between layers 303 and 305) via atomic-layer chemical vapor deposition (ALCVD). An upper electrode layer 306 is then deposited on the high-κ dielectric material, followed by an annealing process.
FIGs. 5A and 5B show an insulated gate field effect transistor (IGFET) at different stages of manufacture, according to another example embodiment of the present invention. In FIG. 5 A, a Germanium substrate material 502 and a stable dielectric layer 503 are formed in a manner not inconsistent with one or more of the example embodiments discussed above. A gate electrode 505 is patterned from an electrode layer (e.g., by patterning layer 104 of FIG. 1). Dopant ions 520 are directed toward the substrate material 502. As shown in FIG. 5B, the ions 520 implant source/drain regions 522 and 524 that are self-aligned to the gate electrode 505, with a channel region 526 of the substrate material 502 being masked by the gate electrode 505. In response to a voltage applied to the gate 505, a signal is capacitively coupled across the stable dielectric layer 522 to bias the channel region 526 and electrically link source/drain regions 522 and 524. FIG. 6 shows a capacitive structure 600 having a stable dielectric layer 603 on a Germanium substrate material 602 with metal silicates and metal germanates therein, according to another example embodiment of the present invention. The
dielectric layer 603 may, for example, be implemented in connection with one or more of the example embodiments discussed herein. The stable combination of metal silicates and metal germanates is shown in the inset 650, with layer 603 comprising metal germanates and metal silicates 642 and 644, respectively, and with layer 602 comprising Germanium and Silicon atoms 632 and 634, respectively. The metal silicates 644 and metal germanates 642 have a mole fraction of about 50% each, without loss of generality. The layer 603 may include amorphous, polycrystalline and/or crystalline structures.
Each of the following examples discussed in connection with FIGs. 7 -15 may be implemented using one or more of the various approaches discussed above, as well as variations thereof. In particular, the high-κ dielectric materials are formed in a manner that facilitates thermodynamic stability with the Ge-based substrates used therein, and exhibits benefits including high carrier mobility, thermodynamic stability and others as discussed above. In FIG. 7, an IGFET-type device 700 includes a stable gate dielectric layer
703 on a Ge-based substrate material 702, according to another example embodiment of the present invention. The device 700 includes a gate 705 separated from and adapted to capacitively couple to a channel region 726 in the Germanium substrate material 702 via the stable gate dielectric layer 703. Source region 722 and drain region 724 are disposed on opposing sides of the channel 726 and in the substrate material 702, with elevated source/drain junctions 716 and 718 over each of source drain regions 722 and 724, respectively. Elevated source/drain junctions 716 and 718 are separated from the gate electrode 705 by spacers 707 and 709, respectively, and reduce the resistance of electrical contacts made to each of source/drain regions 722 and 724, respectively. By using the stable dielectric layer 703 over the Germanium channel 726, benefits including high carrier mobility in the channel region 726 with a highly stable dielectric layer 703 are realized.
FIG. 8 shows an IGFET with a Germanium substrate material region 802 over an insulating layer 841 that form a Germanium-on-insulator (GOI) structure, according to another example embodiment of the present invention. The insulating layer 841 (e.g., oxide) is disposed on a typical semiconductor substrate 801 (e.g., bulk silicon). A thin layer of silicon 842 separates the Germanium substrate material
region 802 from the insulating layer 841. A Germanium channel region 826 is disposed in the Germanium substrate material region 802 between doped source and drain regions 822 and 824. A stable dielectric material 803 is formed on the channel region 826 and separates the channel region from a gate electrode 805 having insulative spacers 807 and 809 on opposing sides thereof.
FIG. 9 shows another semiconductor device 900, similar to the device shown in FIG. 8 but without the silicon layer 842, according to another example embodiment of the present invention. For brevity, articles in FIG. 9 that are similar to those in FIG. 8 are similarly labeled. In this implementation, the Germanium layer 802 is formed directly on the insulating layer 841, with the resulting structure forming a Germanium-based thin film transistor (TFT).
FIG. 10 shows a FinFET device 1000 employing a Germanium-based channel region 1002 separated from a gate 1005 by a stable dielectric layer 1003, according to another example embodiment of the present invention. The FinFET is formed on an insulating layer 1041, with source and drain regions 1022 and 1024 being separated by the Germanium-based channel region 1002.
FIG. 11 shows a double-gate MOSFET device 1100 employing a Germanium- based substrate material region 1102, according to another example embodiment of the present invention. A Germanium-based channel region 1126 is separated from dual gate electrodes 1105 and 1115 by a selected high-κ dielectric material 1103 and 1113. The Germanium-based channel region 1126 separates source and drain regions 1122 and 1124 in the substrate material region 1103. Insulative spacers 1107 and 1109 are disposed on opposing sides of gate electrode 1105, with insulative spacers 1117 and 1119 similarly disposed on opposing sides of gate electrode 1115. FIG. 12 shows a vertical transistor device 1200 employing at least one
Germanium-based channel region separated from a gate electrode by a selected high-κ dielectric material, according to another example embodiment of the present invention. Source region 1222, having contact 1223, and drain region 1224, having contact 1225 are separated by a silicon oxide region 1242 with the drain region 1224 being disposed on a silicon oxide layer 1241. A transistor 1201 includes a channel region 1226 separated from a gate electrode 1205 by a dielectric layer 1203. The channel region and dielectric materials for the transistor include germanium and a
stable dielectric material, respectively, as discussed in other example embodiments above. For general information regarding transistor implementations, and for specific information regarding vertical transistor applications that can be benefited by the present invention, reference may be made to Kalavade & Saraswat, IEEE DRC 2000, which is fully incorporated herein by reference.
FIG 13 shows a Schottky source/drain MOSFET device 1300 having a Germanium-based substrate material region 1302 disposed on an insulating layer 1341, according to another example embodiment of the present invention. The Germanium-based substrate material region 1302 includes a Germanium-based channel region 1326 that separates source and drain regions 1322 and 1324, respectively. A stable dielectric material 1303 separates the Germanium-based channel region 1326 from a gate electrode 1305 having a conductive contact material 1311 formed thereon and insulative sidewall spacers 1307 and 1309 on opposite sides thereof. FIG. 14A is a Germanium-based metal-semiconductor-metal (MSM)-type photodetector 1400, according to another example embodiment of the present invention. The MSM-type structure includes an intrinsic Germanium substrate material region 1402 disposed between upper and lower conductive contacts 1421 and 1423. High-κ passivation layers 1413 and 1403 are disposed on opposing sides of the intrinsic Germanium region 1402. Light 1460 incident upon the photodetector 1400 is absorbed in the intrinsic Germanium substrate material region 1402 and causes electron-hole pair generation, which in turn results in current flow in the MSM photodetector 1400 between the upper and lower electrodes 1421 and 1423. The current flow in the MSM photodetector 1400 can be used to detect the incident light, as well as characteristics thereof.
FIG. 14B is a Germanium-based p+ doped/intrinsic/n+ doped (PIN) photodiode 1450, according to another example embodiment of the present invention. The PIN photodiode 1450 includes an intrinsic Ge-rich substrate material region 1412 disposed between an n-doped Germanium region 1422 and a p-doped Germanium region 1424. In another example implementation, 1422 is a p-type region and 1424 is an n-type region. High-κ passivation layers 1411 and 1414 are disposed on opposing sides of the intrinsic Germanium substrate material region 1412, with conductive
contact regions 1425 and 1426 being electrically coupled to the n-doped Germanium region 1422 and conductive contact region 1427 being coupled to the p-doped Germanium region 1424. Light 1461 incident upon the photodetector 1450 is absorbed in the intrinsic Ge-rich substrate material region 1412 and causes electron- hole pair generation, which in turn affects current flow in the PIN photodiode 1450 between the conductive contact regions 1425 and 1426 and the conductive contact region 1427. As with the MSM photodetector 1400, the current flow in the PIN photodiode 1450 can be used to detect the incident light, as well as characteristics thereof. With the approaches described above in connection with both FIGs.14A and
14B, dark current (e.g., current flow in the absence of the light illumination 1460 or 1461) is relatively low, such that a current signal from the MSM photodetector 1400 or the PIN photodiode 1450 includes relatively low noise. When the light illumination 1460 and/or 1461 is applied to the devices, the resulting cuπent signal representing the detected light has a very high signal-to-noise ratio. These devices 1400 and 1450 are particularly useful for use in a highly dense array of such devices for detecting infrared (IR) light, due to the ability of the intrinsic Germanium-based substrate materials 1402 and 1412 to readily absorb the IR light. Moreover, such high-κ passivation layers can be implemented as discussed above, for example, in connection with FIGs. 2C and 2D.
FIG. 15 shows a Germanium-based monolithically integrated optical receiver 1500, according to another example embodiment of the present invention. The optical receiver 1500 includes a Germanium-based photodetector 1510 and a Germanium- based TFT 1520, similar to the devices shown in FIGs. 9 and 14A, respectively. The device 1500 includes a Silicon substrate 1501 with an inter-layer dielectric (ILD) layer 1541 having a high-κ dielectric material disposed thereon. An amorphous Germanium-based substrate film 1502 (formed, e.g., using low-pressure chemical vapor deposition at about 300 degrees Celsius), is disposed on the ILD layer 1541. Portions 1547, 1543 and 1545 of the amorphous Germanium-based substrate film 1502 have been replaced with an insulative material, such as Silicon dioxide, and portions 1522 and 1524 have been doped to form source/drain regions for the TFT 1520. Portions 1540 and 1526 of the amorphous Germanium-based substrate film
1502 have been crystallized using, for example, metal induced lateral crystallization at a relatively low temperature (e.g., forming an intrinsic material 1540 for the photodetector 1510 and a channel region 1526 for the TFT 1520).
Referring to the Germanium-based photodetector 1510, a high-κ dielectric material 1542 is disposed on the crystallized Germanium portion 1540 of the
Germanium-based substrate film 1502. Conductive materials 1562 and 1560 are in electrical contact with the crystallized Germanium portion 1540. In response to light 1550 incident upon the Germanium-based photodetector 1510, electrons and holes generated in the crystallized Germanium portion 1540 effect current flow between the conductive materials 1562 and 1560.
Referring now to the Germanium-based TFT 1520, a high-κ dielectric film having portions 1511, 1503 and 1512 disposed thereon and separated by conductive material portions 1560 and 1561. A Germanium-based conductive electrode 1506 is disposed on high-κ dielectric material portion 1503, an insulative material 1507, 1509 and 1508 is disposed on each of high-κ dielectric film portions 1511, 1503 and 1512, respectively. Cuπent generated in the crystallized Germanium portion 1540 is electrically coupled to the conductive material 1561 via source/drain regions 1522 and 1524, with a conductive channel being formed that channel region 1526 in response to a voltage applied to the conductive electrode 1506.
EXAMPLE DATA FIG. 16 shows an example capacitance versus voltage curve 1600 as applied to a gate for a semiconductor device having a high-κ dielectric material between a gate and a Germanium-based substrate material, according to another example embodiment of the present invention. Using the device in FIG. 1 as an example, a voltage applied to the upper electrode 104 is shown on the horizontal axis, with the resulting capacitance via the dielectric material to the lower electrode 102 shown on the vertical axis. Using similar numbering, an inset example capacitive structure 1660 shows an upper electrode including platinum 1604 disposed on a high-κ insulative dielectric material 1606 on an N-doped germanium substrate material 1602. Using the inset example, the resulting curve 1600 shows hysteresis estimation with a gate voltage (Vg) of about 1.5 mV causing a change in capacitance at about 400kHz.
While the present invention has been described with reference to several particular example embodiments, those skilled in the art will recognize that many changes may be made thereto without departing from the spirit and scope of the present invention, which is set forth in the following claims.
Claims
1. A semiconductor electronics device, comprising: an electrode surface material; a dielectric layer having a thickness sufficient for passivation of the electrode surface material not greater than about 5 Angstroms Tox,Eq and including a hi-k dielectric surface material that faces, lies against and is thermodynamically stable with the electrode surface material.
2. The semiconductor electronics device of claim 1, wherein hi-k dielectric surface material is preponderantly one of: Zirconium Oxide, and Beryllium oxide.
3. The semiconductor electronics device of claim 1, wherein hi-A: dielectric surface material is preponderantly one of: Erbium oxide, Gadolinium oxide, and Hafnium oxide.
4. The semiconductor electronics device of claim 1, wherein hi -& dielectric surface material is preponderantly one of: Lanthanum oxide, and Thorium oxide.
5. The semiconductor electronics device of claim 1, wherein hi-k dielectric surface material is preponderantly one of: Uranium oxide, Dysprosium oxide, and Yttrium oxide.
6. The semiconductor electronics device of claim 1, wherein hi-A: dielectric surface material is preponderantly one of: Zirconium Oxide, Gadolinium oxide, Hafnium oxide, and Lanthanum oxide.
7. The semiconductor electronics device of claim 1, further including an optics circuit having a GaAs-based substrate material lattice-matched with and lying against the electrode surface material, the electrode surface material having a composition that is preponderantly composed of Germanium and Silicon, and wherein the hi-A: dielectric surface material is part of the optics circuit and is preponderantly one of: Zirconium oxide, Beryllium oxide, Dysprosium oxide, Erbium oxide, Gadolinium oxide, Hafnium oxide, Lanthanum oxide, Thorium oxide, Uranium oxide, and Yttrium oxide.
8. The semiconductor electronics device of claim 7, further including a metal- based material configured and arranged with the electrode surface material to provide respective electrodes for a capacitive structure in which the hi- dielectric surface material provides a capacitive-structure dielectric.
9. A semiconductor electronics device, comprising: a first electrode layer for a capacitive structure; a second electrode layer for the capacitive structure and including a Ge-rich surface material facing the first electrode layer; a dielectric layer having a thickness not greater than about 10 Angstroms Toχ,Eq and including a hi- dielectric surface material that faces, lies against and is thermodynamically stable with the Ge-rich surface material.
10. The semiconductor electronics device of claim 9, wherein hi-A: dielectric surface material contains Zirconium oxide.
11. The semiconductor electronics device of claim 9, wherein hi-A: dielectric surface material contains Lanthanum oxide.
12. The semiconductor electronics device of claim 9, wherein hi-A: dielectric surface material contains Hafnium oxide.
13. The semiconductor electronics device of claim 9, wherein the electrode surface material has a composition that is preponderantly composed of Germanium, and wherein the hi-k dielectric surface material is composed of at least one of: Zirconium oxide, Beryllium oxide, Dysprosium oxide, Erbium oxide, Gadolinium oxide, Hafnium oxide, Lanthanum oxide, Thorium oxide, Uranium oxide, and Yttrium oxide.
14. The semiconductor electronics device of claim 9, wherein the Ge-rich surface material and the hi-k dielectric surface material provides an interface that avoids unstable native oxide from forming between the Ge-rich surface material and the hi-A: dielectric surface material and from undermining their thermodynamic stability.
15. The semiconductor electronics device of claim 14, wherein the electrode surface material has a composition that is preponderantly composed of Germanium, and wherein the hi-k dielectric surface material is composed of at least one of: Zirconium oxide, Beryllium oxide, Dysprosium oxide, Erbium oxide, Gadolinium oxide, Hafnium oxide, Lanthanum oxide, Thorium oxide, Uranium oxide, and Yttrium oxide.
16. The semiconductor electronics device of claim 14, wherein the Ge-rich surface material contains at least sixty percent Germanium.
17. The semiconductor electronics device of claim 14, wherein the Ge-rich surface material is substantially pure Germanium.
18. The semiconductor electronics device of claim 9, wherein the Ge-rich surface material contains at least sixty percent Germanium.
19. The semiconductor electronics device of claim 9, wherein the Ge-rich surface material contains between fifty percent and sixty percent Germanium.
20. The semiconductor electronics device of claim 9, wherein the Ge-rich surface material contains between thirty percent and fifty percent Germanium.
21. The semiconductor electronics device of claim 9, wherein the Ge-rich surface material is substantially pure Germanium.
22. The semiconductor electronics device of claim 9, wherein the Ge-rich surface material contains Silicon.
23. The semiconductor electronics device of claim 9, wherein the Ge-rich surface material contains Nitrogen.
24. The semiconductor electronics device of claim 9, wherein the Ge-rich surface material contains Silicon, Germanium and Carbon.
25. The semiconductor electronics device of claim 9, wherein the Ge-rich surface material contains Germanium and Carbon.
26. The semiconductor electronics device of claim 9, wherein hi-A: dielectric surface material contains Zirconium.
27. The semiconductor electronics device of claim 9, further including an interface layer between the hi-A: dielectric surface material and the Ge-rich surface material.
28. The semiconductor electronics device of claim 27, wherein the interface layer, that is between the hi-A dielectric surface material and the Ge-rich surface material, contains Germanium.
29. The semiconductor electronics device of claim 9, without a Germanium oxide interface layer between the hi-A: dielectric surface material and the Ge-rich surface material.
30. The semiconductor electronics device of claim 9, wherein the hi-A dielectric surface material is directly in contact with the Ge-rich surface material.
31. The semiconductor electronics device of claim 9, wherein the Ge-rich surface material is substantially free of native oxides.
32. The semiconductor electronics device of claim 9, wherein the Ge-rich surface material is composed only of elements of the underlying second electrode layer.
33. The semiconductor electronics device of claim 9, wherein the dielectric layer is not greater than about 8 Angstroms Tox,Eq-
34. The semiconductor electronics device of claim 9, wherein the dielectric layer is not greater than about 5 Angstroms Tox,Eq-
35. The semiconductor electronics device of claim 9, wherein the dielectric layer is a gate dielectric layer for a Germanium-on-insulator IGFET structure within the device.
36. The semiconductor electronics device of claim 9, wherein the dielectric layer is a gate dielectric layer for a Germanium-ridge-on-insulator IGFET structure within the device.
37. The semiconductor electronics device of claim 9, wherein the first electrode forms a gate for an IGFET having source and drain regions, the source and drain regions being self-aligned via the gate.
38. The semiconductor electronics device of claim 9, wherein the first electrode forms a gate for an IGFET having source and drain regions, the source and drain regions being non-self-aligned via the gate.
39. The semiconductor electronics device of claim 9, wherein the capacitive structure is part of an IGFET having elevated source/drain junction regions in which the first electrode layer provides a gate structure for the IGFET.
40. The semiconductor electronics device of claim 9, wherein the capacitive structure is part of an FinFET in which the first electrode layer provides at least part of a gate structure for the FinFET.
41. The semiconductor electronics device of claim 9, wherein the capacitive structure is part of a double-gate IGFET in which the first electrode layer provides at least one of the two gates and the dielectric layer is between the two gates and a channel that includes the Ge-rich surface material.
42. The semiconductor electronics device of claim 9, wherein the capacitive structure is part of an IGFET in which the first electrode layer provides a surround gate.
43. The semiconductor electronics device of claim 9, wherein the Ge-rich surface material is a processed Ge-rich material, wherein the processed Ge-rich material has been processed to remove unstable native oxides of Germanium.
44. The semiconductor electronics device of claim 9, wherein the Ge-rich surface material is a processed Ge-rich material, wherein the processed Ge-rich material has been processed to convert it to a form that is stable with the hi-A: dielectric surface material.
45. The semiconductor electronics device of claim 9, further including an interface layer between the hi-A dielectric surface material and the Ge-rich surface material, the interface layer being a stabilized Ge-based material.
46. The semiconductor electronics device of claim 45, wherein the stabilized Ge- based material includes a metal germanate.
47. The semiconductor electronics device of claim 45, wherein the stabilized Ge- based material includes a metal oxide.
48. A semiconductor device, comprising: a Ge-based surface material having a composition that is preponderantly Ge; a surface passivation layer having a thickness sufficient for passivation of the Ge-based surface material and including a hi-A: dielectric surface material that faces, lies against and is thermodynamically stable with the Ge-based surface material.
49. The semiconductor device of claim 48, wherein the Ge-based surface material contains at least sixty percent Ge.
50. The semiconductor device of claim 48, further including an optical-electronic device including a GaAs-based substrate material lattice-matched with and lying against the Ge-based surface material.
51. The semiconductor device of claim 48, further including a bipolar device with the surface passivation layer lying against the Ge-based surface material, and wherein the surface passivation layer includes material selected from the group consisting of: Zirconium oxide, Beryllium oxide, Dysprosium oxide, Erbium oxide, Gadolinium oxide, Hafnium oxide, Lanthanum oxide, Thorium oxide, Uranium oxide, and Yttrium oxide.
52. The semiconductor device of claim 48, further including an optical device including an optical detector having a GaAs-based substrate material lattice-matched with and lying against the Ge-based surface material.
53. The semiconductor device of claim 48, further including an optical device including an optical diode emitter having a GaAs-based substrate material lattice- matched with and lying against the Ge-based surface material.
54. The semiconductor device of claim 48, further including a micro-el ectro- mechanical system (MEMS) device, wherein the Ge-based surface material contains at least sixty percent Ge.
55. A method for manufacturing a semiconductor device, comprising: providing a Ge-based surface material having a composition that is preponderantly Ge; providing a hi-A dielectric material; processing the Ge-based surface material to provide the Ge-based surface material in a form that is stable with a hi-A dielectric material; forming a dielectric layer having the hi-A: dielectric material at a surface that faces, lies against and is thermodynamically stable with the Ge-based surface material, the dielectric layer having a thickness not greater than about 10 Angstroms
56. The method of claim 55, wherein processing the Ge-based surface material includes passivating the Ge-based surface material.
57. The method of claim 56, wherein passivating the Ge-based surface material includes removing unstable native oxides of Germanium.
58. The method of claim 55, wherein processing the Ge-based surface material includes converting Ge oxide at the Ge-based surface material to a stable form. For the latter approach case, unstable Germanium-based oxides are converted to stable form by combining them with a high-permittivity dielectric such that the resulting material is thermodynamically stable with Ge.
59. The method of claim 55, wherein processing the Ge-based surface material includes converting unstable Germanium-based oxides to stable form by combining the unstable Germanium-based oxides with a high-permittivity dielectric such that the resulting material is thermodynamically stable with Ge.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| AU2002305179A AU2002305179A1 (en) | 2002-04-15 | 2002-04-15 | High-k dielectric for thermodynamically-stable substrate-type materials |
| PCT/US2002/011785 WO2003096390A1 (en) | 2002-04-15 | 2002-04-15 | High-k dielectric for thermodynamically-stable substrate-type materials |
| US10/404,876 US7271458B2 (en) | 2002-04-15 | 2003-03-31 | High-k dielectric for thermodynamically-stable substrate-type materials |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/US2002/011785 WO2003096390A1 (en) | 2002-04-15 | 2002-04-15 | High-k dielectric for thermodynamically-stable substrate-type materials |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US10/404,876 Continuation-In-Part US7271458B2 (en) | 2002-04-15 | 2003-03-31 | High-k dielectric for thermodynamically-stable substrate-type materials |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2003096390A1 true WO2003096390A1 (en) | 2003-11-20 |
Family
ID=29418027
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2002/011785 WO2003096390A1 (en) | 2002-04-15 | 2002-04-15 | High-k dielectric for thermodynamically-stable substrate-type materials |
Country Status (2)
| Country | Link |
|---|---|
| AU (1) | AU2002305179A1 (en) |
| WO (1) | WO2003096390A1 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005008778A1 (en) * | 2003-07-22 | 2005-01-27 | Innovative Silicon S.A. | Integrated circuit device, and method of fabricating same |
| DE102004040796A1 (en) * | 2004-08-23 | 2005-10-20 | Infineon Technologies Ag | Micro-electronic capacitor structure, comprises primary and secondary conducting layers, and a dielectric layer |
| US7271458B2 (en) * | 2002-04-15 | 2007-09-18 | The Board Of Trustees Of The Leland Stanford Junior University | High-k dielectric for thermodynamically-stable substrate-type materials |
| US7495313B2 (en) | 2004-07-22 | 2009-02-24 | Board Of Trustees Of The Leland Stanford Junior University | Germanium substrate-type materials and approach therefor |
| US8558282B1 (en) | 2012-09-08 | 2013-10-15 | International Business Machines Corporation | Germanium lateral bipolar junction transistor |
| CN106158934A (en) * | 2015-05-15 | 2016-11-23 | 台湾积体电路制造股份有限公司 | Semiconductor devices and transistor |
| US11037728B2 (en) | 2017-12-22 | 2021-06-15 | Samsung Electronics Co., Ltd. | Dielectric and capacitor and electronic device |
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| US4959694A (en) * | 1987-12-23 | 1990-09-25 | British Telecommunications Public Limited Company | Semiconductor heterostructures with SiGe material |
| US5646058A (en) * | 1994-07-15 | 1997-07-08 | International Business Machines Corporation | Method for fabricating a self-aligned double-gate MOSFET by selective lateral epitaxy |
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| US7271458B2 (en) * | 2002-04-15 | 2007-09-18 | The Board Of Trustees Of The Leland Stanford Junior University | High-k dielectric for thermodynamically-stable substrate-type materials |
| WO2005008778A1 (en) * | 2003-07-22 | 2005-01-27 | Innovative Silicon S.A. | Integrated circuit device, and method of fabricating same |
| US7495313B2 (en) | 2004-07-22 | 2009-02-24 | Board Of Trustees Of The Leland Stanford Junior University | Germanium substrate-type materials and approach therefor |
| US7772078B2 (en) | 2004-07-22 | 2010-08-10 | The Board Of Trustees Of The Leland Stanford Junior University | Germanium substrate-type materials and approach therefor |
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| DE102004040796A1 (en) * | 2004-08-23 | 2005-10-20 | Infineon Technologies Ag | Micro-electronic capacitor structure, comprises primary and secondary conducting layers, and a dielectric layer |
| US8558282B1 (en) | 2012-09-08 | 2013-10-15 | International Business Machines Corporation | Germanium lateral bipolar junction transistor |
| US8586441B1 (en) | 2012-09-08 | 2013-11-19 | International Business Machines Corporation | Germanium lateral bipolar junction transistor |
| CN106158934A (en) * | 2015-05-15 | 2016-11-23 | 台湾积体电路制造股份有限公司 | Semiconductor devices and transistor |
| CN106158934B (en) * | 2015-05-15 | 2019-08-09 | 台湾积体电路制造股份有限公司 | Semiconductor devices and transistor |
| US11037728B2 (en) | 2017-12-22 | 2021-06-15 | Samsung Electronics Co., Ltd. | Dielectric and capacitor and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| AU2002305179A1 (en) | 2003-11-11 |
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