WO2003088256A1

WO2003088256A1 - Quaternary cam cell

Info

Publication number: WO2003088256A1
Application number: PCT/IL2002/000293
Authority: WO
Inventors: Yves Villaret
Original assignee: Memcall L.L.C.
Priority date: 2002-04-11
Filing date: 2002-04-11
Publication date: 2003-10-23
Also published as: AU2002255240A1

Abstract

A CAM cell with four states: '0', '1', 'Don't Care' and 'Never Match', connected with two compare lines on which data codes '0', '1', 'Don't Care' and 'Never Match' can be set. The 'Never Match' data code, whether stored in the CAM cell or set on the compare lines always results in a mismatch, even where compared with a 'Don't Care' state.The CAM cell operates by connecting a Match line to a 'Virtual ground' in case there is a 'Mismatch' between the stored data and the data applied on the compare lines. During a first period, the Match Line is precharged. during a second, Compare period, the Virtual Ground is selectively connected to ground by applying a command signal.'The 'Never Match' data code can be used to mark bits of words as 'invalid'.

Description

Quaternary CAM cell

Background of the Invention:

Content Addressable Memories of the common type are often composed of unit cells (ternary CAM cells) having three states, usually designed as "0", "1" and "Don't Care". In order to store these three possible states, each ternary CAM cell comprises two memory bits, M and T. M contains the value of the bit, while T is used to mark the bit as "Don't care". When T is reset ("0"), then the CAM cell is in the "Don't care" state. A CAM cell of that type is shown in Fig 1.

In such a ternary CAM cell, whenever the T bit is reset ("0"), the state of the M bit has no importance. Therefore, one state remains unused. For example the 3 states {M=0, T=1} {M=1 , T =1} {M=0, T =0} are sufficient to operate the ternary CAM cell. The state {M=1 , T=0} is then unused. Thus it would be desirable to utilize the unused state of the ternary CAM cell, and add functionality to the CAM.

Another drawback of ternary CAM cells is that the implementation requires that both polarities of the CAM memory bit be available (D and ND of fig 1). Whenever the type of memory cell used is a SRAM type cell, this requirement does not create a problem, since SRAM memory cells always generate the two signals D and ND. However, if the memory cell is a DRAM type, the ND signal may not be available. This will thus complicate the DRAM type CAM cell, requiring a relatively large area for these CAM cells.

It is thus desirable to design a CAM cell in which all four states of the CAM cell are used. In particular, the fourth state of the CAM cell can be used to mark some words of data as "Invalid", meaning that these words, when compared, should always produce a mismatch. It is also desirable to design a CAM cell in which only one polarity of the data bit is used. CAΓ

US vl Cell implementations for a four states CAM Cell have been described in ope 5,949,696, US 5,319,590. However in these implementations, a compare As ration between a "Don't Care" and an "Invalid" state results in a "Match", not a result, applications in which a "mismatch" result would be desired are _Th enabled by the quaternary cell design of the prior art. worfs for example, a Content Addressable Memory can be used to search pat(d strings of variable length, as for example in the systems described in invεsnts PCT/IL 01/00436, and PCT/IL 01/00915. In such word strings the that»lid state may be used to separate between two consecutive records such two upon executing a string search, the invalid state placed between those sep records will prevent a string compare operation to cross over the record bitsaration. In such a system, should the string searched contain "don't care" stat or words, these don't care bits or words might be compared to the invalid cane used to separate between records, the result being a false match, thus dra\celing the separation provided by the Invalid bits. This characteristic pos/vback of the systems based on patents US 5,949,696 or US 5,319,590, whesibly resulting in a false match crossing over two consecutive records sys re the string to be searched includes "don't care" bits, is overcome by the

_Λ :em described here. Sur

.__, nmaiN of the Invention

The beir present invention relates to a CAM cell in a CAM array, the CAM cell "Νeig able to store four possible data codes, "0", "1", "Don't care", and cell,ver Match". Two compare lines B and BΝ are input to the inventive CAM can and four different data codes, "0", "1", "Don't Care" and "Never Match" CAI^ be set on these lines. The "Never Match" Data code, when stored in the func Cell of the invention or set on the compare lines, can be used to add wori_'tionality to the CAM array. In particular, it can be used to mark bits or ds of the CAM or of the data input on the compare line as "invalid". A char codcacteristic feature of the inventive CAM Cell is that the "Never Match" data rests, whether stored in the CAM cell or set on the Compare Lines, always comilts in a mismatch for the compare operation, even in the case where it is _A ipared with a "Don't Care" state.

"Alvther functionality of the inventive CAM Cell is that it can be placed in an one^/ays Match" state by means of a command signal that is associated with

_., or a number of CAM Cells. The jnpi said command signal may be generated locally or it may be an external , it to the CAM array.

"Vir inventive CAM cell operates by applying a connection of a Match line to a the tual Ground" in case there is a "Mismatch" between the Stored data and eml data applied on the compare lines. In the operation cycle of a preferred sec^odiment, two time periods are defined, a first, pre-charge period, and a virtiond, compare period. During the pre-charge period, both Match Line and the Jal ground are brought to a first potential. During the Compare period of Virt compare cycle, the pre-charging of the Match Line is stopped, and the groual Ground is selectively connected to a second potential (for example coriund). If there is a Mismatch, then the circuit of the CAM applies a of inection between the Match Line and the Virtual Ground, and the potential potthe Match Line is forced to that of the Second Potential. Finally, the it isential of the Match Line at the end of a compare cycle indicates a match if the> equal or close to the first potential and a mismatch if it is equal or close to . second potential.

Grc-ording to another aspect of the invention, the connection of the Virtual sig)und to the second potential may be activated by means of a command Cenal. This signal may be selectively activated for one or a number of CAM WHIs whenever a compare operation is to be executed on these CAM Cells, lenever this command signal is not activated during the compare cycle, then potei the Match Line and the Virtual ground will both remain at the first _τh mtial, resulting in an "Always Match" condition. addi "Always Match" condition thus defines a fifth state for the CAM Cell, _, sd to the four previously described stored states. purr. Command Signal may be generated in many ways, according to the corrJoses of the application. For example it may be generated by a logic systibination with a stored additional bit associated to a word of data and a . _f:em clock signal, so that Words of data can be marked as "Always Match". con 'AM Cell designed according to the principle of the invention requires corrnection to only one polarity of the memory bit, so that it can be used in SR ibination with memory cells of the DRAM type as well as those of the \M type.

ef Description of the Drawings:

Fig.

Fig, 1 shows a ternary CAM cell of the known type

Fig, 2 is a Truth Table for the CAM Cell of Fig 1.

. 3 shows a quaternary CAM cell according to a preferred embodiment

Fig of the invention.

Fig. 4 is a truth table for a CAM Cell designed according to the invention.

. 5 shows a row of quaternary inventive CAM Cells, where all CAM

Fig Cells of the row are connected to a common Virtual Ground.

. 6 shows an embodiment of the CAM cell of the invention in which P Channel transistors are used. Det

The ailed Description of the Invention: bein present invention relates to a CAM cell in a CAM array, the said CAM cell " e^g able to store four possible data codes, "0", "1", "Don't care", and four^er Match". Two compare lines B and B are input to this CAM cell, and set ' different data codes, "0", "1", "Don't Care" and "Never Match" can be Cell on these lines. The "Never Match" Data code, when stored in the CAM arra or set on the compare lines, can be used to add functionality to the CAM datεy. In particular, it can be used to mark bits or words of the CAM or of the invei input on the compare line as "invalid". A particular property of the CAIvntive CAM Cell is that the "Never Match" data code, whether stored in the corral cell or set on the Compare Lines, always results in a mismatch for the statipare operation, even in the case where it is compared with a "Don't Care"

Anc^e-

"Alvther functionality of the inventive CAM Cell is that it can be placed in an sigrvays Match" state by means of a command signal. The said command exteial may be generated locally for one or more CAM cells or it may be an _Th jrnal input to the CAM array.

"Vw inventive CAM cell operates by applying a connection of a Match line to a the tual Ground" in case there is a "Mismatch" between the Stored data and eml data applied on the compare lines. In the operation cycle of a preferred sec^odiment, two time periods are defined, a first, pre-charge period, and a to εond, compare period. During the pre-charge period, Match Line is brought cha* first potential. During the Compare period of the compare cycle, the pre- coπirging of the Match Line is stopped, and the Virtual Ground is selectively theinected to a second potential (for example ground). If there is a Mismatch, then the circuit of the CAM applies a connection between the Match Line and Se( Virtual Ground, and the potential of the Match Line is forced to that of the x>nd Potential. Finally, the potential of the Match Line at the end of a com a mi pare cycle indicates a match if it is equal or close to the first potential and

. smatch if it is equal or close to the second potential.

Groprding to another aspect of the invention, the connection of the Virtual signJnd to the second potential may be activated by means of a command wheal. This signal may be selectively set for one or a number of CAM Cells Whenever a compare operation is to be executed on these CAM Cells. Mat never this command signal is not set during the compare cycle, then the resu-h Line and the Virtual ground will both remain at the first potential, _Th ilting in an "Always Match" condition. addi "Always Match" condition thus defines a fifth state for the CAM Cell, _, ed to the four previously described stored states. purf Command Signal may be generated in many ways, according to the corr>oses of the application. For example it may be generated by a logic systibination with a stored additional bit associated to a word of data and a "Alv:em clock signal, so that Words of data can be stored and marked as . _rvays Match". con AM Cell designed according to the principle of this invention requires connection to only one polarity of the memory bit, so that it can be used in SR_/ibination with memory cells of the DRAM type as well as those of the The^M type. con* Compare Lines as defined herein, may be independent lines used for the andipare operation, but may also be the same lines used for the data write opel read data operations of the CAM. In the latter case, the compare . iration is disabled or discarded during a write or read operation. pric)rder to demonstrate the advantages of the inventive CAM cell over the refe>r art, a ternary CAM cell of the prior art will be described hereinbelow, with jrence to the drawings. In F bits ig. 1 a ternary CAM cell of known type is shown. It comprises two memory com M and T. The memory bit M stores a given bit value, generating two bit Mplementary signals, D and ND, where D logic value represents the stored CAIValue. The T bit, when reset ("0"), indicates a "don't care" state of the

Wh ^ ^ceiL in f sn the CAM cell is operated, a comparison is made between the bit stored is sd, and the value of data set on the two compare lines B and NB. The data st on the two lines B and NB with the following coding:

«' Line B set and NB reset represents data value "1"

«> Line B reset and NB set represents value "0"

» Line B and NB both reset represents a "Soft don't care", i.e. always

« match, not depending on the data stored in the CAM cell

► In some applications the state "B" set and "NB" set may be used for

"Soft never match", i.e. comparison will always result in a Mismatch, not depending on the data stored in the CAM cell. However, if the

A c "Don't Care" bit is reset, the comparison results will be a "Match". sufrompare cycle comprises two time periods, a pre-charge period and a the 'sequent compare period. When operating the CAM Cell for comparison, cha Match line shown in Fig 1 is pre charged to a first potential during the pre- disdrge period. During the subsequent compare period, the Match Line is cori-onnected from the first potential. The CAM Cell circuit then functions by connecting the Match line to a second potential in case a Non matching

... idition is found. We pot shall later refer to the effect of bringing the Match Line to the second potential as "discharge". Such a circuit is shown in Fig 1 , where the first

Celential is a voltage source and the second potential is ground. The CAM jmrJI is circuit is implemented with 4 transistors, Tr1 to Tr4. Different

US)lementations exist for this comparison circuit, as described for example in

5,469,378 to Albon et al., US 6,240,004 to Kuo et al and US 6,044,005 to Gibs requ>on et al., however usually both polarities D and ND of the memory bit are indie ired. The potential of the Match Line at the end of a compare cycle is eoates a match if it is equal or close to the first potential and a mismatch if it . _t ual or close to the second potential. statue circuit shown in Fig 1 , it can be seen that if B and NB have the same grots as D and ND respectively, then potential of node P is low (close to not ind). In that case, transistor Tr3 is not conducting, and the Match line is resedischarged, indicating a "Match" condition. If both Lines B and NB are onc(it ("0'), then again the potential of node P is low and Tr3 is not conducting, care3 more indicating a "Match" condition, corresponding to the "Soft don't

P is*" state of the compare lines. In the two other cases, the potential of node tran high and the transistor Tr3 is conducting. In that case if the T bit is set, a Msistor Tr4 is also conducting, and the Match line is discharged, indicating

Matismatch. If the T bit is reset, then transistor Tr4 is not conducting, and a the ch condition will be always issued, according to the "Don't care" state of _τ. CAM cell. The is "c Truth Table for such a CAM Cell is shown in Fig 2. Whenever data stored the fon't care", the result of comparison is always a match, not dependent of con state of the compare lines. Symmetrically, whenever the state of the a mipare lines is "Soft Don't care", then the result of the comparison is always

■ atch, not depending on the state of the CAM Cell. no uch a CAM cell, whenever the T bit is reset ("0"), the state of the M bit has stat importance. Therefore, one state remains unused. For example the 3 cell:es {M=0, T=1} {M=1 , T =1} {M=0, T =0} are sufficient to operate the CAM . The state {M=1 , T=0} is then unused.

CAI stalM Cell implementations for a four states CAM Cell utilizing the unused te of the CAM cell to mark some words of data as "invalid" have been desc implϊribed in patents US 5,949,696 and US 5,319,590. However these Car<ementations have the drawback of a compare operation between a "Don't whics" and an "Invalid" state resulting in a "Match". As a result, applications in qual∑h a "mismatch" result would be desired are not enabled by the _Th ternary cell design of the prior art. a qi present invention overcomes the drawbacks of the prior art by proposing undiJatemary CAM cell that will be described in detail hereinbelow. It will be emterstood that while the invention will be described in respect of a preferred froπ>odiment many changes and modifications may be made without departing are ι the invention in its broader aspects and therefore the appended claims falh to encompass within their scope all such changes and modifications as . ,. within the true spirit and scope of this invention. corrg 3, a preferred embodiment of the present invention is shown. A CAM cell bitsipπ^'ses two memory bits, ND and D. The four states of these two memory are used to store and code four states of the CAM cell:

• {ND=0, D=1} represents stored data of logic value "1"

• {ND=1 , D=0} represents stored data of logic value "0"

• {ND=0, D=0} represents a "Don't care" state for the CAM cell

• {ND=1 , D=1} represents a "Never Match" state for the CAM cell

In t stalhe same manner, the two compare lines may have one of the following :es:

• {NB=0, B=1} represents data of logic value "1"

• {NB=1 , B=0} represents data of logic value "0"

• {NB=0, B=0} represents "Soft Don't care" state

• {NB=1 , B=1} represents "Soft Never Match" state, i.e. no match will be issued for all the CAM cells that are connected to these compare lines. As f per or the common type of CAM cell, the compare cycle comprises two time Fig. 3ds, a pre-charge period and a compare period. The Match Line shown in of tι3 is pre charged to a first potential during the pre-charge period by means conransistor Tr6. The logic way of function of the CAM Cell circuit is to connect the Match Line to a node called Virtual Ground if a mismatch left Idition is verified. During the pre-charge period, this Virtual Ground is either whe loating, or set to the first potential thus preventing current flow in the case elecre a state of the stored data or of the compare lines generates an thatfrical path from the Match Line to the Virtual Ground. It will be understood pote various kind of circuits may be used to bring the Virtual Ground to the first Fig.ϊntial, or to disconnect it from the second potential. In the embodiment of pote 3, the first potential is a positive supply voltage (Vcc), and the second is t ntial is ground. However it may be understood that the only requirement opeiat first and second potential should be different, so that after a compare thatration, the Match Line potential will indicate the result of the comparison. If sec potential is close to the first potential, the result is a match. If it is close to Poεond potential, it is a Mismatch. In the particular embodiment of Fig 3, positive Logic has been chosen, such that Logic State 1 for a signal is a high thaisntial, and Logic State 0 is a lower potential (ground). It will be understood _n : negative logic may be used as well. to ε'ing the compare period, the Virtual Ground may be selectively connected than second potential (for example ground). In the embodiment shown in fig 3, Tr5t selection is done by means of the compare enable signal and a transistor a c- The Compare Enable signal is defined herein as "Active" when it applies cononnection between Virtual Ground and the second potential during the potnpare period. The circuit used to bring the Virtual ground to the second aiwential can be one of many kinds. As explained before, the Virtual Ground is ays left floating or brought to first potential during the Pre-charge period. Whe com never the Virtual Ground is connected to second potential during the follo are period, i.e. when the Compare Enable signal is active, we have the wing cases for the comparison:

• Case: {ND=0, D=1} ,

- If NB=0 and B=1 , then the comparison result is a Match: stored data and data on compare lines are both state "1". For those states, NB and ND are both at ground potential, both transistors Tr2 and Tr4 are non-conducting, and no electrical path exists between Match Line and Virtual Ground. Therefore the Match Line remains at first potential, and result of comparison is a Match.

- If NB=0 and B=0 , then comparison result is a Match: data on compare lines is "Soft don't care". As in previous case, Both transistors Tr2 and Tr4 are non conducting, and no electrical path exists between Match Line and Virtual Ground.

- in all other cases, comparison result is a Mismatch: one of the transistors Tr1 and Tr3 is conducting, and one of transistors Tr2 and Tr4 is also conducting. An electrical path is always defined

Sirr between Match Line and Virtual Ground, lilarly, it can be seen that other cases are as follows:

• If ND=1 and D=0 :

- Match if NB=1 and B=0, i.e stored data and data on compare lines are both "0"

- Match if NB=0 and B=0, i.e. data on compare lines is "Soft don't care"

- Mismatch in all other cases.

• If ND=0 and D=0:

- Match in all cases, Except case where B and NB are both "1"

• If ND=1, D=1: - Never Match. In rencase the Compare Enable signal is not active, then the Match Line will _Th lain at the first potential, resulting in a Match condition. enj3 truth Table for this CAM Cell is shown in Fig 4, for a case where compare

,-. able is active. Fig the 5 shows a row of quaternary inventive CAM Cells, where all CAM Cells of typ row are connected to a common Virtual Ground. As in CAMs of the known woe, the row of CAM Cells can be used to execute the comparison of one a <rd. A command signal is used to conditionally connect the virtual ground to corground potential. Whenever the command signal is not set during the whmpare period, the results of the comparison will always be "Match", be atever the state of the compare lines. It must be understood that there may grc any number of virtual grounds in one memory word, up to one virtual dis>und for each CAM Cell. In that way, groups of bits, or individual bits can be willabled for comparison, i.e. they will not discharge the Match Line, and thus _Th I not contribute to a Mismatch result of the comparison of the word. beie embodiment of Fig. 3 is shown with N channel transistors, first potential umng a high potential, and second potential being a low potential. It must be traderstood that P channel transistors can also be used for each of the bit nsistors Tr1 to Tr4. For each transistor used, the logic state of the memory wh or compare line connected to its gate will be said to be at logic level "1" leven this bit or compare line places that transistor in a conducting state, and tra el "0" otherwise. An implementation where all transistors are P channel poinsistors, first potential is a high potential and second potential is a low chitential is shown in Fig. 6. It must be understood that any combination of P forannel and N channel transistors can be used using the same principle as stc the preferred embodiment. In the embodiment of Fig. 6, data "1" will be •red in bit D when the output connected to transistor Tr1 is Low, thus putting that and: transistor in a conducting state. The same applies to data stored in bit ND will transistor Tr2. In this embodiment state "1" for compare lines B and NB . _^be defined as low potential. posi CAM application, it is often desired to have the capability to mark cells at thalitions in the memory that have not been loaded with data as "Invalid". In Usit case, it will be required that these cells do not issue a false "Match", be Jally, in a Ternary CAM, an additional bit of memory and a logic circuit will maiused in each word in order to disable a compare operation and prevent a invjtch for invalid words. Using the quaternary CAM cell of this invention, this invalid bit is not required. Instead a "Never Match" bit is loaded in one of the . _ralid word bits. to t'AM array using the CAM Cell of the present invention will add functionality anche CAM. In communication systems, applications such as routers, fire wall fun! any content aware routing systems will greatly benefit from the added usiictionality. The CAM cell of the invention can be implemented in a chip _Th ig the same or smaller silicon area than the common CAM cell. sof3 addition of functionality saves the need for additional circuits and tware, resulting in a faster and reduced cost system.

Claims

Claims:

1. A four state CAM cell with a logic "0" state, a logic "1 " state, a "don't care" state and a "never match" state, to be connected between a Match Line and a Virtual ground line, the said CAM cell comprising a first memory bit in logic association with a first compare line and a second memory bit in logic association with a second compare line, each memory bit being adapted to store either logic state "1" or logic state "0" and each compare line being adapted to receive one of two logic states "0" and "1", the said CAM cell further comprising an electronic circuit that creates an electric path between the said Match Line and the said Virtual Ground during a compare cycle in a case where both following logic conditions are verified: a) either the said first memory bit or the said first compare line or both are in logic state "1" AND b) either the said second memory bit or the said second compare line or both are in logic state "1".

2. A four state CAM cell according to claim 1 hereinabove wherein the said CAM cell further receives a command line that selectively inputs a command signal, the said command signal enabling the said creation of the said electrical path during the said compare cycle.

3. A CAM cell according to Claim 1 hereinabove wherein the said electronic circuit comprises: a. A first pair of transistors Tr1 , Tr2, each of the gates of the said transistors being connected to one of the said first and second memory bits respectively, the logic state of each of the said first and second memory bits being defined so as to place one of the said transistors in a conducting state whenever the respective memory bit connected to the said transistor is set to logic state "1", and b. A second pair of transistors Tr3, Tr4, each of the gates of the said transistors Tr3, Tr4 being connected to one of the said compare lines respectively, the logic state of each of the said compare lines being defined so as to place one of the said transistors Tr3, Tr4 in a conducting state whenever the respective memory bit connected to the said transistor is set to logic state "1", the said transistors Tr1 and Tr3 being connected in parallel, the said transistors Tr2 and Tr4 also being connected in parallel and the two pairs of transistors Tr1 , Tr3 and Tr2, Tr4 being connected in series between the said Match line and the said Virtual Ground such that an electrical path is created between the said Match line and the said Virtual Ground in the case that a mismatch occurs in course of the said comparison operation.

A four state Cam cell according to any of claims 1 - 3 hereinabove wherein the said electronic circuit comprises N channel transistors.

A four state Cam cell according to any of claims 1 - 3 hereinabove wherein the said electronic circuit comprises P channel transistors.

A four state Cam cell according to any of claims 1 -5 hereinabove wherein the said memory bits are static RAMs.

A four state Cam cell according to any of claims 1-5 hereinabove wherein the said memory bits are dynamic RAMs.

8. A method of executing a compare operation between data codes set on a pair of first and second compare lines and data codes stored in a pair of first and second memory bits in a four state CAM cell wherein the said first memory bit is in logic association with the said first compare line and the said second memory bit is in logic association with the said second compare line such that the state of the said compare lines may be set according to any of four different data codes, "0", "1", "don't care" or "never match" and the said memory bits can store any of the said four data codes, whereby when data are set on the said compare lines and a compare operation is executed, the following comparison results are obtained: a. A match result if code "0" of the memory bits is compared to code "0" on the compare lines; b. A match result if code "1" of the memory bits is compared to code "1" on the compare lines; c. A match result if code "don't care" of the memory bits is compared to code'O" or code "1" or code "don't care" on the compare lines; d. A match result if code "don't care" on the compare lines is compared to code'O" or code "1" or code "don't care" of the memory bits; e. A mismatch results in all remaining cases.

9. A method of operation of a four state CAM cell that is connected between a Match Line and a Virtual ground line, the said CAM cell comprising a first memory bit and a second memory bit, each memory bit being capable of storing either logic state "1" or logic state "0" and the said CAM cell receiving as input a first compare line in logic association with the said first memory bit and a second compare line in logic association with the said second memory bit, each line being adapted to receive in one of two logic states "0" and "1", the said CAM cell further comprising an electronic circuit with a plurality of transistors, connecting between the said Match line and the said Virtual ground line and the said cell having comparison results according to claim 7, the said method comprising the following steps: a. During a first pre-charge period, bringing the said Match Line to a first potential or bringing the said Match Line and the said Virtual ground to a first potential; b. Stopping the pre-charging of the said Match Line and connecting the said Virtual ground to a second potential; c. Executing a compare cycle wherein in the case of a mismatch, a connection is applied between the said Match line and the said Virtual Ground, whereby the potential of the said Match line is forced to the said second potential;

Whereby at the end of the said compare cycle a match is indicated if the potential of the said Match line is equal or close to the said first potential and a Mismatch is indicated if the potential of the said Match line is equal or close to the said second potential.

10. A method of operation of a four state CAM cell according to claim 8 hereinabove wherein the connection of the said Virtual ground to the said second potential is activated by means of a command signal, the said command signal capable of being selectively activated for the said four state CAM cell or for a number of four state CAM cells including the said four state CAM cell whenever a compare operation is to be executed for the said CAM cells, such that where the said command signal is not activated during the said compare cycle for any of the said four state CAM cells, the said Match line and the said Virtual ground of the respective four state CAM cell will both remain at the first potential, indicating a "Match" condition.

11. A row of four state CAM Cells according to any of claims 1 - 7, wherein all the said four state CAM Cells are connected to a common Virtual Ground, the said row of four state CAM cells is able to execute the comparison of one word and a command signal is used to conditionally connect the said common virtual ground to a ground potential wherein whenever the command signal is not set during the compare period, the results of the comparison will always be "Match", whatever the state of the said compare lines.

12. A row of four state CAM Cells according to any of claims 1-7, wherein all the said four state CAM Cells are connected to a common Match line, the said row of four state CAM cells enabling a comparison operation for a word of data.

13. A method of separating between strings of words of various sizes stored in a CAM memory array comprising four state CAM cells according to any of claims 1-7 hereinabove wherein between the strings to be separated one or more four state CAM cells storing a "never match" state are inserted.