WO2003085813A2

WO2003085813A2 - Line frequency switching regulator

Info

Publication number: WO2003085813A2
Application number: PCT/US2003/010013
Authority: WO
Inventors: Max Ward Muterspaugh
Original assignee: Thomson Licensing S.A.
Priority date: 2002-04-04
Filing date: 2003-04-02
Publication date: 2003-10-16
Also published as: CN101330254B; MXPA04009647A; CN100412739C; AU2003224818A1; EP1490957A2; EP1490957A4; KR20040106310A; JP2005522177A; US20060164048A1; US7199562B2; WO2003085813A3; CN1643468A; KR100995537B1; AU2003224818A8; CN101330254A; JP4339129B2

Abstract

In a switch mode power supply (SMPS), a mains supply voltage source (VM) is coupled to a rectifier (101) for producing an input supply voltage. The rectified input supply voltage is coupled unfiltered to an input (Vin) of the SMPS. A switching power transistor (Q1) having a controllable duty cycle is controlled by a duty cycle modulated signal for producing a regulated output supply voltage from the rectified input supply voltage. The periodic waveform of the mains supply voltage is used to establish the timings of the duty cycle modulated signal. In each cycle, current flow is initiated in the transistor, when the transistor is already fully turned on and a voltage developed between its main current conducting terminals is low or close to zero volts. When the output supply voltage attains the required level the transistor is turned off. Hysteresis is provided for preventing the transistor from turning on again in the same cycle, after it has been turned off.

Description

LINE FREQUENCY SWITCHING REGULATOR

Cross Reference to Related Applications This is a non-provisional application which claims the benefit of provisional application serial number 60/370,072, filed April 4, 2002.

Background of the Invention The invention relates to a switch mode power supply for a communication device. Typically, a switch mode power supply (SMPS), includes a switching power transistor having a controllable duty cycle that is controlled by a duty cycle modulated signal. An alternating current (AC) mains supply voltage source is coupled to a rectifier for producing an input supply voltage for energizing the SMPS. Typically, a large input filter capacitor is coupled at an input of the SMPS for filtering AC components from a rectified input supply voltage produced in the rectifier. It may be desirable to eliminate the large input filter capacitor. A typical SMPS requires the generation of a periodic switching signal to establish the timings of the duty cycle modulated signal. It may be desirable to utilize the periodic waveform of the mains supply voltage to establish the timings of the duty cycle modulated signal. Thereby, SMPS operation can be obtained without an added circuit complexity associated with the generation of the periodic switching signal. In a SMPS, embodying an inventive feature, a mains supply voltage source is coupled to a rectifier for producing an input supply voltage. The rectified input supply voltage is coupled unfiltered to an input of the SMPS. A switching power transistor having a controllable duty cycle is controlled by a duty cycle modulated signal for producing a regulated output supply voltage from the rectified input supply voltage. The periodic waveform of the mains supply voltage is used to establish the timings of the duty cycle modulated signal.

In carrying out an inventive feature, in each cycle, current flow is initiated in the transistor, when the transistor is already fully turned on and a voltage developed between its main current conducting terminals is low or close to zero volts. Thereby, power dissipation is, advantageously, small. When the output supply voltage attains a threshold level the transistor is turned off.

In carrying out another inventive feature, hysteresis is provided for preventing the transistor from turning on again in the same cycle, after it has been turned off. Thereby, advantageously, the transistor is prevented from turning on again in the same cycle, when the voltage developed between its main current conducting terminals is no longer close to zero volts. Consequently, increased power dissipation is, advantageously, prevented.

Summary of the Invention A switch mode power supply, embodying an inventive feature includes a source of a periodic input supply voltage and a filter capacitor. A power, switching semiconductor is coupled to the source and to the capacitor for generating periodic rectified supply current pulse in the semiconductor having a first transition in a first direction and a second transition at an opposite direction at a frequency related to that of the input supply voltage to develop an output supply voltage in the capacitor. A source of a first switch control signal is provided for conditioning the semiconductor to conduction prior to the first transition in a manner to provide for zero voltage switching in the semiconductor, during the first transition. A comparator is responsive to a signal indicative of the output supply voltage and to a signal at a reference level for generating a second switch control signal for the semiconductor to produce the second transition of the current pulse that is modulated, in accordance with a difference between the output supply voltage and the reference level signal. The comparator has a positive feedback signal path that provides hysteresis with respect to the output supply voltage.

Brief Description of the Drawings FIGURE 1 illustrates an unfiltered full-wave rectified sinewave waveform produced from a mains supply voltage at a line frequency that is useful for explaining the operation of the circuit of FIGURE 2;

FIGURE 2 illustrates a switch mode power supply, embodying an inventive feature; and FIGURES 3a, 3b and 3c illustrate waveforms useful for explaining the operation of the power supply of FIGURE 2.

Description of the Preferred Embodiments FIGURE 2 illustrates a switch mode power supply that includes a switch mode regulator 100, embodying an inventive feature. A mains supply voltage NM is applied via a line transformer Tl to a bridge rectifier 101. A voltage Nin, developed at a terminal 102a or 102b of rectifier 101, is coupled to an emitter of a regulator, series pass switching transistor Ql via terminal 102a or 102b. Transistor Ql is coupled in series with a rectifier or diode D2 to form a switching semiconductor. A collector of transistor Ql is coupled via diode D2 to a filter capacitor Cl for producing a regulated, output supply voltage Nout in capacitor Cl.

Voltage Nout is coupled via a voltage divider that includes a resistor R7 and a resistor R6, having, for example, equal values, to an inverting input terminal of a comparator or an operation amplifier Ul , pin 2, of the type LM324. A reference voltage Nref is coupled via an adjustable voltage divider resistor RIO and a resistor R5 to a non-inverting input terminal, pin 3, of amplifier Ul to establish a reference voltage Nref 1 at the non-inverting input terminal of amplifier Ul, pin 3. An output terminal of amplifier Ul, pin 1, is coupled via a voltage divider formed by a resistor R2 and a resistor R3 to the base of a switching transistor Q2. A collector of transistor Q2 is coupled via a current limiting resistor Rl to the base of transistor Ql . FIGURES 1 and 3a-3c illustrate waveforms useful for explaining the operation of switching regulator 100 of FIGURE 2. Similar symbols and numerals in FIGURES 1, 2 and 3a-3c indicate similar items or functions.

Assume that terminal 102a of bridge rectifier 101 of FIGURE 2 is separated from an emitter terminal 102b of transistor Ql , as shown by the broken lines in the form of the letter "x". Assume also that a resistive load, not shown, is applied to terminal 102a. In that case, the waveform of input supply voltage Nin at terminal 102a of FIGURE 2 would be an unfiltered full-wave rectified sinewave waveform, of mains supply voltage VM having a line frequency of, for example, 60Hz, as shown in FIGURE 1. In the following description, assume that terminals 102a and 102b are connected to each other, as shown in FIGURE 2, and are at the same potential.

During each period 9 of voltage Nin of FIGURE 3b, and as long as voltage Vout of FIGURE 3 a is lower than two times the voltage at the non-inverting input terminal, pin 3, of amplifier Ul of FIGURE 2, an output voltage of amplifier Ul, at output pin 1, is at a HIGH level, that is substantially equal to a 20 volt supply voltage, not shown, of amplifier Ul. As a result, transistor Q2 is turned on causing transistor Ql to turn on in a saturated condition. Thus, advantageously, transistor Ql is conditioned for conduction before a current Ieql of FIGURE 3c flows in transistor Ql.

When voltage Nin becomes sufficiently large to forward bias diode D2, as indicated by a portion of voltage Nin that is above a broken line in FIGURE 1, a collector-emitter voltage, not shown, of transistor Ql of FIGURE 2 changes polarity. Consequently, rectified supply current Ieql of FIGURE 3c begins flowing through a current path that includes an emitter-collector current path of transistor Ql of FIGURE 2, diode D2 and filter capacitor Cl to charge capacitor Cl and produces voltage Nout. Voltage Vout varies together with an instantaneous value of voltage Vin, during an interval tl of FIGURE 3b. FIGURE 3c illustrates a waveform of emitter current Ieql in transistor Ql of FIGURE 2, during interval tl, when voltage Vout of FIGURE 2 is coupled to a load, not shown, of for example, 11 ohm. In carrying out an inventive feature, output voltage Vout of FIGURE 3a is regulated in a power efficient manner by initiating the flow of current Ieql of FIGURE 3c in transistor Ql of FIGURE 2, when voltage Vin of FIGURE 3b is approximately equal to voltage Vout of FIGURE 3a or a magnitude of the collector-emitter voltage, not shown, of transistor Ql of FIGURE 2 is small. Current Ieql of FIGURE 3c begins flowing in transistor Ql of FIGURE 2 after transistor Ql is already conditioned for conduction. Therefore, advantageously, zero voltage switching is provided when transistor Ql is turned on. The result is that less power is dissipated in transistor Ql than if a significant voltage difference were developed between its emitter and collector of transistor Ql of FIGURE 2, prior to the initiation of emitter current Ieql of FIGURE 3c. When voltage Vout of FIGURE 3a reaches a threshold level that is equal to two times the voltage at the non-inverting input terminal, pin 2, of amplifier Ul of FIGURE 2, amplifier Ul output at pin 1 attains a LOW level, causing transistors Q2 and Ql to turn off. Voltage Vout does not increase significantly above two times the voltage at the non-inverting input terminal, pin 3, of amplifier Ul. Therefore, during a transition interval, not shown, when transistor Ql is turned off, the power dissipation in transistor Ql is also, advantageously, small. The process of replenishing the charge on capacitor Cl that was removed by the load circuit, not shown, is repeated in each period T of voltage Vin of FIGURE 3b.

A positive feedback resistor R4 of FIGURE 2, embodying an inventive feature, is coupled from output terminal of amplifier Ul, pin 1, to the non-inverting input terminal of amplifier Ul , pin 3, to provide hysteresis. Positive feedback resistor R4 causes the voltage difference between that at the inverting input terminal, pin2, and at the non-inverting input terminal, pin 3, of amplifier Ul to increase further.

Thereby, the hysteresis prevents amplifier Ul from turning on transistor Ql again to avoid multiple occurrences of pulses of current Ieql of FIGURE 3c, during a down-ramping portion Vindr of voltage Vin. Without the hysteresis, amplifier Ul of FIGURE 2 might have been capable of turning on transistor Ql to produce a second pulse of current Ieql in transistor Ql and diode D2, during the same period T of FIGURE 3b, when the voltage difference between the emitter and collector of transistor Ql of FIGURE 2 is significant and greater than zero. Thereby, the hysteresis prevents power dissipation increase in transistor Ql by preserving the zero voltage switching.

A pull-down diode D3, embodying an inventive feature, is coupled between the emitter of transistor Ql and the inverting input terminal, pin 2, of amplifier Ul. Pull-down diode D3 couples voltage Vin to inverting input terminal, pin 2, of amplifier Ul. Decreasing voltage Vin, during a down-ramping portion Vindr of voltage Vin of FIGURE 3b, causes the voltage at output terminal of amplifier Ul, pin 1, to attain the HIGH level again. Consequently, advantageously, transistor Ql is conditioned for conduction in preparation to the next cycle. Diode D2 is back biased immediately after transistor Ql is conditioned for conduction.

Therefore, current flow in conductive transistor Ql that, otherwise, could have discharged capacitor Cl is prevented until the next conduction interval tla of FIGURE 3c. Only when voltage Vin of FIGURE 3b again reaches a level that is approximately equal to voltage Vout of FIGURE 3a, diode D2 begins conducting current Ieq of FIGURE 3c again, as explained before.

The level of voltage Vout is, advantageously, maintained substantially the same in each period T of FIGURE 3b regardless of variations in the amplitude of input voltage Vin. A variation in output load current may change a peak-to-peak ripple voltage VRIPPLE in FIGURE 3 a. However, the average value of DC output voltage Vout is maintained. Ripple voltage VRIPPLE can be controlled by appropriate selection of the value of capacitor Cl with respect to the load, as is well known. Thus, regulation is achieved for input voltage variations and for load variations.

A diode Dl of FIGURE 2, a capacitor C2, and a resistor R8 form a transient suppresser. When transistor Ql turns off, the leakage inductance in transformer Tl tends to keep the current flowing which produces a high voltage spike, not shown, which could damage transistor Ql and/or produce noise in the regulated output. Diode Dl and capacitor C2 conduct this spike and resistor R8 provides a leakage path for the voltage generated. A junction terminal 106 of resistor R8, capacitor C2 and the cathode of diode Dl could also be used for providing an auxiliary supply voltage, such as needed to supply amplifier Ul or other circuits. In the arrangement of FIGURE 2 it is used to derive reference voltage Vref .

Claims

WHAT IS CLAIMED IS:

1. A switch mode power supply, comprising: a source of a periodic input supply voltage; a filter capacitor; a power, switching semiconductor coupled to said source and to said capacitor for generating periodic rectified supply current pulse in said semiconductor having a first transition in a first direction and a second transition at an opposite direction at a frequency related to that of said input supply voltage to develop an output supply voltage in said capacitor; a source of a first switch control signal for conditioning said semiconductor to conduction prior to said first transition in a manner to provide for zero voltage switching in said semiconductor, during said first transition; and a comparator responsive to a signal indicative of said output supply voltage and to a signal at a reference level for generating a second switch control signal for said semiconductor to produce said second transition of said current pulse that is modulated, in accordance with a difference between said output supply voltage and said reference level signal, said comparator having a positive feedback signal path that provides hysteresis with respect to said output supply voltage.

2. The power supply according to Claim 1, wherein said first transition occurs, when a first difference between an instantaneous level of said input supply voltage and said output supply voltage is reached.

3. The power supply according to Claim 1, wherein said hysteresis prevents said semiconductor from generating multiple current pulses in a given period of said input supply voltage in a manner to maintain the zero voltage switching.

4. The power supply according to Claim 1, wherein said switching semiconductor comprises a series pass transistor.

5. The power supply according to Claim 4, wherein said series pass transistor is coupled in series with a rectifier for preventing said capacitor from discharging via said transistor, outside said rectified supply current pulse.

6. The power supply according to Claim 4, wherein said first transition occurs, when a voltage, developed between a pair of main current conducting terminals of said transistor, changes polarity.

7. The power supply according to Claim 4, wherein said input supply voltage is coupled to a control terminal of said transistor via a signal path that bypasses a main current conducting path in said transistor to generate said first switch control signal at said control terminal of said transistor.

8. The power supply according to Claim 1, further comprising a rectifier for rectifying a mains supply voltage to produce said input supply voltage having a sine-wave rectified waveform.

9. A switch mode power supply, comprising: a source of a periodic input supply voltage; a filter capacitor; a power, switching transistor coupled to said source and to said capacitor for generating periodic rectified supply current pulse in said transistor having a first transition in a first direction and a second transition at an opposite direction at a frequency related to that of said input supply voltage to develop an output supply voltage in said capacitor; said input supply voltage being coupled to a control terminal of said transistor via a signal path that bypasses a main current conducting path in said transistor to generate a first switch control signal at said control terminal of said transistor for conditioning said transistor to conduction prior to said first transition in a manner to provide for zero voltage switching in said transistor, during said first transition; and a comparator responsive to a signal indicative of said output supply voltage and to a signal at a reference level for generating a second switch control signal for said semiconductor to produce said second transition of said current pulse that is modulated, in accordance with a difference between said output supply voltage and said reference level signal.

10. The power supply according to Claim 9, wherein said transistor comprises a series pass transistor.

11. The power supply according to Claim 10, wherein said series pass transistor is coupled in series with a rectifier for preventing said capacitor from discharging via said transistor, outside said rectified supply current pulse.

12. The power supply according to Claim 9, wherein said signal path that bypasses said main current conducting path includes said comparator.

13. The power supply according to Claim 9, wherein said first transition occurs, when a voltage developed between a pair of main current conducting terminals of said transistor changes polarity.