WO2003079240A3 - System and method for placement of dummy metal fills while preserving device matching and/or limiting capacitance increase - Google Patents

System and method for placement of dummy metal fills while preserving device matching and/or limiting capacitance increase Download PDF

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Publication number
WO2003079240A3
WO2003079240A3 PCT/US2003/007497 US0307497W WO03079240A3 WO 2003079240 A3 WO2003079240 A3 WO 2003079240A3 US 0307497 W US0307497 W US 0307497W WO 03079240 A3 WO03079240 A3 WO 03079240A3
Authority
WO
WIPO (PCT)
Prior art keywords
dummy
locating
integrated circuit
device matching
fills
Prior art date
Application number
PCT/US2003/007497
Other languages
French (fr)
Other versions
WO2003079240A2 (en
Inventor
Soo-Young Oh
Original Assignee
Ubitech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/097,978 external-priority patent/US6751785B1/en
Application filed by Ubitech Inc filed Critical Ubitech Inc
Priority to KR10-2004-7014312A priority Critical patent/KR20050007440A/en
Priority to JP2003577169A priority patent/JP2005520336A/en
Priority to EP03714076A priority patent/EP1493111A2/en
Priority to AU2003218093A priority patent/AU2003218093A1/en
Publication of WO2003079240A2 publication Critical patent/WO2003079240A2/en
Publication of WO2003079240A3 publication Critical patent/WO2003079240A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/18—Manufacturability analysis or optimisation for manufacturability
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

Systems and methods for placement of dummy metal fills while preventing disturbance of device matching and optionally limiting capacitance increase are disclosed. A computer-automated method for locating dummy fills in an integrated circuit fabrication process generally comprises receiving as input layout of the integrated circuit and specification of device matching for the integrated circuit and locating the dummy fills in the integrated circuit according to dummy rules while preserving device matching. Locating the dummy fills may include locating the dummy fills along the at least one axis of symmetry where device matching is along an axis of symmetry and locating the dummy fills so as to preserve matching of the repeated elements where device matching is repeated matched elements. The method may also include designating at least one net of the integrated circuit as a critical net, the critical nets being only a subset of all nets of the integrated circuit, identifying metal conductors corresponding to each designated critical net from the layout file, and delineating a net blocking exclusion zone extending a distance of a minimum net blocking distance (NBD) from the metal conductor for each metal conductor identified, wherein the step of locating locates the dummy fills outside of the net blocking exclusion zone.
PCT/US2003/007497 2002-03-12 2003-03-12 System and method for placement of dummy metal fills while preserving device matching and/or limiting capacitance increase WO2003079240A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR10-2004-7014312A KR20050007440A (en) 2002-03-12 2003-03-12 System and method for placement of dummy metal fills while preserving device matching and/or limiting capacitance increase
JP2003577169A JP2005520336A (en) 2002-03-12 2003-03-12 System and method for positioning a dummy metal fill while preventing interference with device matching and selective capacity limitation
EP03714076A EP1493111A2 (en) 2002-03-12 2003-03-12 System and method for placement of dummy metal fills while preserving device matching and/or limiting capacitance increase
AU2003218093A AU2003218093A1 (en) 2002-03-12 2003-03-12 System and method for placement of dummy metal fills while preserving device matching and/or limiting capacitance increase

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US10/097,978 2002-03-12
US10/097,978 US6751785B1 (en) 2002-03-12 2002-03-12 System and method for limiting increase in capacitance due to dummy metal fills utilized for improving planar profile uniformity
US10/158,617 2002-05-30
US10/158,617 US6904581B1 (en) 2002-03-12 2002-05-30 System and method for placement of dummy metal fills while preserving device matching and/or limiting capacitance increase

Publications (2)

Publication Number Publication Date
WO2003079240A2 WO2003079240A2 (en) 2003-09-25
WO2003079240A3 true WO2003079240A3 (en) 2004-07-15

Family

ID=28044138

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/007497 WO2003079240A2 (en) 2002-03-12 2003-03-12 System and method for placement of dummy metal fills while preserving device matching and/or limiting capacitance increase

Country Status (5)

Country Link
EP (1) EP1493111A2 (en)
JP (1) JP2005520336A (en)
CN (1) CN1643525A (en)
AU (1) AU2003218093A1 (en)
WO (1) WO2003079240A2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7712056B2 (en) 2002-06-07 2010-05-04 Cadence Design Systems, Inc. Characterization and verification for integrated circuit designs
US7757195B2 (en) 2002-06-07 2010-07-13 Cadence Design Systems, Inc. Methods and systems for implementing dummy fill for integrated circuits
US7774726B2 (en) 2002-06-07 2010-08-10 Cadence Design Systems, Inc. Dummy fill for integrated circuits
US7962867B2 (en) 2002-06-07 2011-06-14 Cadence Design Systems, Inc. Electronic design for integrated circuits based on process related variations

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7124386B2 (en) 2002-06-07 2006-10-17 Praesagus, Inc. Dummy fill for integrated circuits
EP1532670A4 (en) 2002-06-07 2007-09-12 Praesagus Inc Characterization adn reduction of variation for integrated circuits
US7393755B2 (en) 2002-06-07 2008-07-01 Cadence Design Systems, Inc. Dummy fill for integrated circuits
US20030229875A1 (en) 2002-06-07 2003-12-11 Smith Taber H. Use of models in integrated circuit fabrication
US7188321B2 (en) 2003-11-06 2007-03-06 International Business Machines Corporation Generation of metal holes by via mutation
JP5180625B2 (en) * 2007-03-12 2013-04-10 ルネサスエレクトロニクス株式会社 Semiconductor device
CN102130043B (en) * 2010-12-30 2013-10-02 中国科学院微电子研究所 Method for filling redundancy metal
CN115705459A (en) * 2021-08-13 2023-02-17 长鑫存储技术有限公司 Dummy pattern filling method and semiconductor device layout
CN114722768B (en) * 2022-06-08 2022-09-30 珠海妙存科技有限公司 Chip virtual component design method and device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5763955A (en) * 1996-07-01 1998-06-09 Vlsi Technology, Inc. Patterned filled layers for integrated circuit manufacturing
US6323113B1 (en) * 1999-12-10 2001-11-27 Philips Electronics North America Corporation Intelligent gate-level fill methods for reducing global pattern density effects

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5763955A (en) * 1996-07-01 1998-06-09 Vlsi Technology, Inc. Patterned filled layers for integrated circuit manufacturing
US6323113B1 (en) * 1999-12-10 2001-11-27 Philips Electronics North America Corporation Intelligent gate-level fill methods for reducing global pattern density effects

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
BALASA F ET AL: "Module placement for analog layout using the sequence-pair representation", DESIGN AUTOMATION CONFERENCE, 1999. PROCEEDINGS. 36TH NEW ORLEANS, LA, USA 21-25 JUNE 1999, PISCATAWAY, NJ, USA,IEEE, US, 21 June 1999 (1999-06-21), pages 274 - 279, XP010343916, ISBN: 1-58113-092-9 *
KAHNG A B ET AL: "FILLING ALGORITHMS AND ANALYSES FOR LAYOUT DENSITY CONTROL", IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, IEEE INC. NEW YORK, US, vol. 18, no. 4, April 1999 (1999-04-01), pages 445 - 462, XP002161725, ISSN: 0278-0070 *
STINE B E ET AL: "THE PHYSICAL AND ELECTRICAL EFFECTS OF METAL-FILL PATTERNING PROCTICES FOR OXIDE CHEMICAL-MECHANICAL POLISHING PROCESSES", IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE INC. NEW YORK, US, vol. 45, no. 3, 1 March 1998 (1998-03-01), pages 665 - 679, XP000738545, ISSN: 0018-9383 *
WAI-CHEE WONG ET AL: "A technology-independent methodology of placement generation for analog circuit", DESIGN AUTOMATION CONFERENCE, 1999. PROCEEDINGS OF THE ASP-DAC '99. ASIA AND SOUTH PACIFIC WANCHAI, HONG KONG 18-21 JAN. 1999, PISCATATWAY, NJ, USA,IEEE, US, 18 January 1999 (1999-01-18), pages 141 - 144, XP010326324, ISBN: 0-7803-5012-X *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7712056B2 (en) 2002-06-07 2010-05-04 Cadence Design Systems, Inc. Characterization and verification for integrated circuit designs
US7757195B2 (en) 2002-06-07 2010-07-13 Cadence Design Systems, Inc. Methods and systems for implementing dummy fill for integrated circuits
US7774726B2 (en) 2002-06-07 2010-08-10 Cadence Design Systems, Inc. Dummy fill for integrated circuits
US7962867B2 (en) 2002-06-07 2011-06-14 Cadence Design Systems, Inc. Electronic design for integrated circuits based on process related variations

Also Published As

Publication number Publication date
AU2003218093A1 (en) 2003-09-29
CN1643525A (en) 2005-07-20
JP2005520336A (en) 2005-07-07
WO2003079240A2 (en) 2003-09-25
EP1493111A2 (en) 2005-01-05

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