WO2003069486A1 - A memory and an adaptive timing system for controlling access to the memory - Google Patents
A memory and an adaptive timing system for controlling access to the memory Download PDFInfo
- Publication number
- WO2003069486A1 WO2003069486A1 PCT/US2003/002609 US0302609W WO03069486A1 WO 2003069486 A1 WO2003069486 A1 WO 2003069486A1 US 0302609 W US0302609 W US 0302609W WO 03069486 A1 WO03069486 A1 WO 03069486A1
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- WIPO (PCT)
- Prior art keywords
- data
- dvw
- signal
- nominal
- circuit
- Prior art date
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1689—Synchronisation and timing concerns
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/0033—Correction by delay
- H04L7/0037—Delay of clock signal
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- the invention relates generally to memory devices, methods, and systems, and more particularly, to timing for memory accesses.
- RAM random access memory
- DDR double data rate synchronous dynamic RAM
- SDRAM operate in conjunction with a data strobe to perform the memory access when data on the data lines is most likely to be valid.
- Data strobes are non-free-running signals driven by the device that is driving the data signals (the memory controller for WRITE operations, the memory for READ operations).
- the data strobe signals are edge-aligned with the data signals such that all data and the data strobes are to be asserted by the memory using the same internal clock signal. Consequently, the data signals and the data strobe signals are generated at nominally the same time.
- a typical memory does not generate data strobes in the middle of the DVW. Consequently, an external system reading the memory typically delays reading the data lines until valid data is present on the data lines.
- the memory controller is typically configured to delay the received strobe to the center of the DVW.
- Many memory systems synchronize memory accesses using delay locked loop (DLL) circuits to generate an appropriate delay following the data strobe. DLL circuits, however, consume considerable area in an already crowded integrated circuit. Using strobes and DLL circuits also presents difficulties in testing components for quality control. Further, many systems use memory controllers that control several different and independent memory modules.
- DLL delay locked loop
- memory controllers often include slave DLL circuits dedicated to each memory module and a master DLL circuit for controlling operation of the slave DLL circuits.
- Each additional DLL circuit requires additional area in the integrated circuit, thus tending to increase the size, cost, power consumption, and complexity of the memory system.
- the problems are exacerbated by the addition of multiple master DLL circuits, each associated with one or more bytes on a bus.
- a memory system and method includes a memory and an adaptive timing system for controlling access to the memory.
- the adaptive timing system captures data in a data valid window (DVW) in a data signal.
- the adaptive timing system includes a delay circuit for sampling the data signal at a midpoint of the DVW.
- the adaptive timing system may also include an identifying circuit for identifying whether the midpoint of the DNW corresponds to an actual midpoint of the DNW and adjusting the delay circuit accordingly.
- Figure 1 is a block diagram of an electronic system according to various aspects of the present invention
- Figure 2 is a block diagram of a memory system
- Figure 3 represents signal waveforms for a clock signal, a complementary clock signal, and a plurality of data signals
- Figure 4 is a block diagram of an adaptive timing system
- Figure 5 is a flow diagram of a calibration process
- Figure 6 is a flow diagram of a timing adjustment process.
- an electronic system 100 may include a processor 102, a memory system 104, and a data source and/or destination 106.
- the electronic system 100 comprises a system using a memory, such as a conventional personal computer system.
- the electronic system 100 may comprise, however, any suitable electronic system, such as a communication system, computing system, entertainment system, control system, portable electronic device, audio component, or factory control system, and the various components may differ according to the particular system and environment.
- the processor 102 generally controls operation of the electronic system, and may comprise any appropriate processor or controller, such as an Intel, Texas Instruments, or Advanced Micro Devices microprocessor.
- the data sources and/or destinations 106 may comprise any suitable components in the electronic system 100 for sending and or receiving data, including conventional peripherals such as a hard drive, optical storage system, tape storage system, printer, display, keyboai'd, tracking device, or the like.
- the data source/destination 106 is an illustrative component that may be primarily a data source (such as a keyboai'd or sensor), a data destination (such as a display or speaker), or both (such as a hard drive or transceiver).
- the memory system 104 comprises a storage system for storing data.
- the memory system 104 may comprise any appropriate memory system for storing data and transferring data between the memory system 104 and the data source/destination 106 or processor 102.
- the memory system 104 includes one or more memory modules 210A, B and a memory controller 212.
- the memory modules 210 may comprise any system for storing data, such as a conventional ROM, SRAM, DRAM, SDRAM, or any other suitable storage system.
- the memory modules 210 comprise DDR SDRAMs from Micron, such as Micron MT46N64M4 256Mb DDR SDRAMs.
- the memory controller 212 controls access to, including data transfers to and from, the memory module 210, and may perform further functions and operations as well.
- Data may be exchanged between the memory system 104 and the data source/destination 106 along a set of n data lines according to any appropriate method or technique.
- a conventional data transfer process transfers data by capturing data in a data valid window (DVW) of a data signal.
- DVD data valid window
- data is suitably asserted on the data lines upon the crossing of a clock signal (CK) and a complementary clock signal (CK#).
- the guardband intervals are suitably separated from the DVW 300 nominal midpoint by any duration selected to identify variation in the DVW 300 characteristics and correspond a desired DVW 300 duration.
- the guardbands are set approximately, or slightly less than, half the expected duration of the DVW 300 from the nominal midpoint. Consequently, the first tap corresponds to a delay immediately after the leading edge 310 of the DVW 300 (the nominal leading edge), and the third tap similarly corresponds to a delay immediately before the trailing edge 312 of the DVW 300 (the nominal trailing edge).
- the delay associated with each tap may be adjustably programmed, such as to correspond to an adjusted midpoint of the DVW 300 as it moves, for example due to temperature and/or voltage variations.
- each latch circuit 412 is activated to capture the input data received by the latch circuit 412 when the delay clock signal is asserted.
- each latch circuit 412 captures data received from the data source 106 at different times, such as the midpoint and the leading and trailing edges 310, 312 of the timing and/or data signal.
- the memory system 104 is suitably configured to respond to the signals from the compare circuit 414 in any appropriate manner, such as to determine whether and how much to adjust the delays associated with one or more of the delay circuit 410 taps.
- the delay circuit 410 may adjust the delays associated with the delay circuit 410 taps to a desired position relative to the data signal.
- a compare circuit 414 indicates that the signals received from the latch circuits 412 are substantially identical, then the signal near the nominal edge (leading edge 310 or trailing edge 312) matches the signal at the nominal midpoint. Therefore, the signal at the nominal edge is within the DVW 300.
- the memory controller 212 adjusts the delays associated with the three delay taps in accordance any appropriate method or algorithm. For example, when the compare circuit 414 indicates that the DVW 300 has moved, the delay associated with each tap may be changed to shift the delays associated with the various taps to move the nominal approximate midpoint closer to the actual midpoint of the DVW 300.
- the delays associated with the outer taps may be similarly adjusted to place the nominal approximate edges associated with the outer taps closer to the actual leading and trailing edges 310, 312 of the DVW 300. For example, one or more cycles or half-cycles of the memory controller 212 clock may be added to or subtracted from the current delay values of the various taps.
- the adjustments to the delay circuit may be made in any appropriate manner.
- the particular technique for adjusting the delays may be selecting to decrease the effects of noise or other short term effects on the system.
- the memory controller may require two or more consecutive indications from the compare circuit 414 that the DVW 300 has moved. Further, the memory controller may have adjustment limits so that the delays associated with the taps may be adjusted a limited number of times during a particular time interval or up to a limited magnitude of adjustment. The type and value of such limits may be selected according to any criteria for a particular system or application.
- the memory system 104 may initially calibrate the adaptive timing system 214. Calibration provides initial values for the nominal midpoint and leading and trailing edges 310, 312. The initial values may be provided in any appropriate manner, such as by using preselected default values or testing for DVW 300 information. For example, referring to Figure 5, for a calibration process of the present embodiment, the memory controller 212 initially requests a known timing signal from the relevant memory module 210 (step 510).
- the timing signal may be any suitable signal, such as a predete ⁇ r ⁇ ied timing signal, a conventional strobe signal, a WRITE and READ operation to generate a known signal, or the data signal itself. In one embodiment, the timing signal is a toggling signal alternating between binary high and low signals.
- the memory controller 212 samples the timing signal at several points in the timing signal (step 512), for example using the adaptive timing circuit.
- the memory controller suitably samples the timing signal over several points within one or more cycles of the timing signal to conduct a sweep of the timing signal.
- the samples may then be analyzed to identify the approximate leading and trailing edges 310, 312 of the signal's DVW 300 (steps 514, 516) and calculate the approximate midpoint relative to the free-running clock (step 518).
- the memory controller 212 may identify a first and a last sample following a data strobe that achieve a threshold value known to be in the timing signal.
- the adaptive timing system 214 may adjust the nominal midpoint and leading and trailing edges 310, 312 in the event of drift. If the memory controller 212 operates with multiple memory modules 210 or sections, the adaptive timing system 214 may perform an adjustment process for each memory module 210A, B or section of memory. For example, as the memory module 210 heats up, the DVW 300 may move. The memory system 104 may be configured to occasionally check the DVW 300, such as in accordance with a thermal and/or voltage time constant of the system. For example, the memory controller 212 may provide a CALIBRATE command to the memory to request the timing signal at regular intervals no longer than the thermal and/or voltage time constant.
- the memory controller 212 may include a time constant timer to trigger the adjustment process. If the memory controller 212 reads a toggling pattern (such as using the data signal) in normal operation sufficient to verify the characteristics of the DVW 300, the time constant timer may be reset. If the time constant timer expires, the adjustment process may then be initiated. Thus, the adaptive timing system 214 may continuously sample the strobes on READ operations and update the delay circuit 410 opportunistically when no READ operations are occurring. Consequently, the full adjustment process is performed only when a sufficient pattern has not been received and the time constant timer has expired.
- the compare circuit 414A may compare the leading edge 310 data to the midpoint (step 612). If the data are the same (step 614), then the nominal leading edge 310 is still within the DVW 300, and no adjustment is necessary. If the data are not the same, then the DVW 300 has moved. Accordingly, the nominal leading and trailing edges 310, 312 and midpoint may be increased a selected amount (step 616) or according to any selected criteria or algorithm.
- the present embodiment is described in conjunction with a delay circuit 410 having three taps, one for the nominal midpoint and two for the nominal leading and trailing edges 310, 312 of the DVW 300. Additional taps may be provided, however, to collect data about other portions of the data signal. For example, additional taps may assigned to intervals between the midpoint and the edges 310, 312 of the DVW 300 and may be similarly connected to compare circuits 414. The data collected by latch circuits 412 connected to the additional taps may be used to identify changes in the DVW 300 as well as the rate at which the changes in the DVW 300 are occurring.
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003568542A JP3987038B2 (en) | 2002-02-11 | 2003-01-29 | Memory and adaptive timing system for controlling access to memory |
AU2003205371A AU2003205371A1 (en) | 2002-02-11 | 2003-01-29 | A memory and an adaptive timing system for controlling access to the memory |
KR1020047012397A KR100733951B1 (en) | 2002-02-11 | 2003-01-29 | Memory and Adaptive Timing System for Controlling Access to the Memory |
DE60305162T DE60305162T2 (en) | 2002-02-11 | 2003-01-29 | MEMORY AND AN ADAPTIVE TIME CONTROL SYSTEM FOR CONTROLLING ACCESS TO THE MEMORY |
EP03704059A EP1479006B1 (en) | 2002-02-11 | 2003-01-29 | A memory and an adaptive timing system for controlling access to the memory |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/073,611 US7076678B2 (en) | 2002-02-11 | 2002-02-11 | Method and apparatus for data transfer |
US10/073,611 | 2002-02-11 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2003069486A1 true WO2003069486A1 (en) | 2003-08-21 |
Family
ID=27659717
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2003/002609 WO2003069486A1 (en) | 2002-02-11 | 2003-01-29 | A memory and an adaptive timing system for controlling access to the memory |
Country Status (10)
Country | Link |
---|---|
US (3) | US7076678B2 (en) |
EP (3) | EP1479006B1 (en) |
JP (1) | JP3987038B2 (en) |
KR (1) | KR100733951B1 (en) |
CN (1) | CN100350402C (en) |
AT (3) | ATE326035T1 (en) |
AU (1) | AU2003205371A1 (en) |
DE (2) | DE60335042D1 (en) |
TW (1) | TWI257549B (en) |
WO (1) | WO2003069486A1 (en) |
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2002
- 2002-02-11 US US10/073,611 patent/US7076678B2/en not_active Expired - Lifetime
-
2003
- 2003-01-29 EP EP03704059A patent/EP1479006B1/en not_active Expired - Lifetime
- 2003-01-29 DE DE60335042T patent/DE60335042D1/en not_active Expired - Lifetime
- 2003-01-29 AT AT03704059T patent/ATE326035T1/en not_active IP Right Cessation
- 2003-01-29 KR KR1020047012397A patent/KR100733951B1/en active IP Right Grant
- 2003-01-29 AT AT06111574T patent/ATE530985T1/en not_active IP Right Cessation
- 2003-01-29 AT AT06111570T patent/ATE488804T1/en not_active IP Right Cessation
- 2003-01-29 EP EP06111570A patent/EP1677204B1/en not_active Expired - Lifetime
- 2003-01-29 AU AU2003205371A patent/AU2003205371A1/en not_active Abandoned
- 2003-01-29 CN CNB038037084A patent/CN100350402C/en not_active Expired - Lifetime
- 2003-01-29 WO PCT/US2003/002609 patent/WO2003069486A1/en active IP Right Grant
- 2003-01-29 DE DE60305162T patent/DE60305162T2/en not_active Expired - Lifetime
- 2003-01-29 EP EP06111574A patent/EP1679607B1/en not_active Expired - Lifetime
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007511010A (en) * | 2003-11-13 | 2007-04-26 | インテル コーポレイション | Method and apparatus for maintaining data density for derivative clocking |
WO2010038422A1 (en) * | 2008-10-01 | 2010-04-08 | パナソニック株式会社 | Memory interface |
Also Published As
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AU2003205371A1 (en) | 2003-09-04 |
ATE530985T1 (en) | 2011-11-15 |
JP3987038B2 (en) | 2007-10-03 |
EP1479006A1 (en) | 2004-11-24 |
CN1630856A (en) | 2005-06-22 |
CN100350402C (en) | 2007-11-21 |
US20030154416A1 (en) | 2003-08-14 |
DE60305162D1 (en) | 2006-06-14 |
EP1479006B1 (en) | 2006-05-10 |
KR20040089613A (en) | 2004-10-21 |
TWI257549B (en) | 2006-07-01 |
KR100733951B1 (en) | 2007-06-29 |
EP1679607A3 (en) | 2006-10-18 |
EP1677204A2 (en) | 2006-07-05 |
DE60305162T2 (en) | 2007-05-10 |
ATE326035T1 (en) | 2006-06-15 |
EP1679607A2 (en) | 2006-07-12 |
ATE488804T1 (en) | 2010-12-15 |
US7818601B2 (en) | 2010-10-19 |
US20080155141A1 (en) | 2008-06-26 |
EP1677204A3 (en) | 2006-10-18 |
EP1677204B1 (en) | 2010-11-17 |
TW200302969A (en) | 2003-08-16 |
DE60335042D1 (en) | 2010-12-30 |
US20060129865A1 (en) | 2006-06-15 |
US7356723B2 (en) | 2008-04-08 |
EP1679607B1 (en) | 2011-10-26 |
JP2005525623A (en) | 2005-08-25 |
US7076678B2 (en) | 2006-07-11 |
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