WO2003065670A1 - Moyens et procede de codage de donnees et de communication a des debits superieurs a la largeur de bande du canal - Google Patents

Moyens et procede de codage de donnees et de communication a des debits superieurs a la largeur de bande du canal Download PDF

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Publication number
WO2003065670A1
WO2003065670A1 PCT/IB2003/000356 IB0300356W WO03065670A1 WO 2003065670 A1 WO2003065670 A1 WO 2003065670A1 IB 0300356 W IB0300356 W IB 0300356W WO 03065670 A1 WO03065670 A1 WO 03065670A1
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Prior art keywords
begin
code
codes
data
stgjatch
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PCT/IB2003/000356
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English (en)
Inventor
Igor Anatolievich Abrosimov
Alexander Roger Deas
Gordon John Faulds
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Igor Anatolievich Abrosimov
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Priority claimed from GBGB0202366.1A external-priority patent/GB0202366D0/en
Application filed by Igor Anatolievich Abrosimov filed Critical Igor Anatolievich Abrosimov
Publication of WO2003065670A1 publication Critical patent/WO2003065670A1/fr
Priority to US10/656,143 priority Critical patent/US6806817B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
    • H04L25/4908—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes

Definitions

  • the present invention relates to the communication of signals, in particular, to the transmission and reception of digital signals. More specifically, the present invention relates to encoding and decoding the data being sent to reduce the offset of the signal around the sampling threshold voltage when the data rate is above the bandwidth of the channel.
  • the present invention is particularly applicable to interfaces between integrated circuits and for high speed communications, such as currently addressed by Asynchronous Transfer Mode (ATM), Gigabit Ethernet, 3GIO, RapidlO, Hyperchannel and Fibre Transmission Channels, and makes possible yet higher data rates for a particular bandwidth of the transmission medium.
  • ATM Asynchronous Transfer Mode
  • Gigabit Ethernet 3GIO
  • RapidlO RapidlO
  • Hyperchannel Hyperchannel
  • Fibre Transmission Channels makes possible yet higher data rates for a particular bandwidth of the transmission medium.
  • a conventional communication channel comprising a differential driver, such as an LVDS (Low Voltage Differential Signaling) driver, a production package for the integrated circuit such as a BGA (Ball Grid Array), a printed circuit board, a receiver packaged similarly with its ESD (Electronic Static Discharge) structure, acts together as a filter.
  • a differential driver such as an LVDS (Low Voltage Differential Signaling) driver
  • BGA Bit Grid Array
  • ESD Electro Static Discharge
  • a signal at 6GHz may only have 20% of the amplitude of a signal at 1GHz (2Gbps).
  • a 20GHz (40Gbps) signal over a 2GHz BW channel may have only The receiver commonly has a relatively fixed sampling threshold voltage or current. If the signal being transmitted is a sine wave, and small changes are introduced at the time the sine wave is transmitted, such as by channel calibration processes or simply jitter, the entire signal can shift such that none of the data points for a period after the time shift cross the sampling threshold. An example of this is shown in Fig. 2. In this plot, the signal at 6GHz is sent through a channel with 1GHz bandwidth, and then at the start of the third cycle, the data is shifted in the transmitter by 5ps.
  • the system must tolerate the filter response when sending data.
  • the limited ability to equalise the channel at a practical level means that above the pass band of the channel, the data will be attenuated.
  • This attenuation can be managed using tracking receiver thresholds, however, the impulse response of the filter causes a more dramatic problem: the entire data signal shifts over a small number of cycles as a function of tiny amounts of phase noise or phase variations.
  • BW 1GHz bandwidth
  • the driver and receiver will reach their saturated values.
  • the speed of response depends on where in the sine wave the 1GHz signals happens to be at the point of change.
  • Each cycle of the 6GHz signal represents a little over 1 radian of the 1GHz signal.
  • the 1GHz signal normalised to +/- 1V, will change at a rate of 2V per nS over the radian centred on the sampling threshold, but less than 1/12 th of this over 1 radian of the cycle centred about the apex of the 1GHz sinusoid.
  • the received signal can be considered to have a momentum, determined by the impulse response of the channel filter characteristic.
  • the present invention applies a coding to reduce the pattern dependent artifacts within a communication channel, that result from the channel bandwidth being less than the data rate. It is an object of the present invention to enable channel calibration or perform an adjustment by the introduction of small timing increments and decrements reliably when the data is sampled by a relatively fixed threshold as described in PCT/RU01/00482, PCT/RU01/00365, GB 0131100.0 but the channel bandwidth is insufficient. Another object of the invention is to increase the maximum amount of data that can be communicated across a channel, in the case where the transmitter and receiver can operate at a frequency well above the bandwidth of the transmission medium but the transform or filter function imposed by the transmission medium distorts the signal such that it cannot be sampled reliably. It is another object of the invention to reduce the artifacts introduced into the signal from the limited and non-linear characteristics of the channel, such as by reflections not being absorbed efficiently due to the frequency of the reflection being in the non-linear region of the line termination components.
  • the present invention is a coding means for coding data represented by input symbols into codes for transmitting the codes by a transmitter along a communication channel, the codes being represented in the channel by signals having a limited minimum and maximum pulse width, to enable sampling the coded data at a receiver at each receiver's clock period, wherein the input symbols are encoded to have the minimum signal pulse width longer than one period of the receiver's sampling clock.
  • the input symbols are encoded to have a minimum signal pulse width approximately defined by formula
  • ⁇ is a minimum bit interval providing a required bit error rate (BER) of data, the bit interval being a period of time required for the transfer of one bit of information, and F is the bandwidth of the channel.
  • BER bit error rate
  • the required bit error rate of data is defined by a specialist in the art taking into account various parameters of a communication channel, such as timing uncertainty of a signal, noise in the channel, metastability in the receiver, etc.
  • the input symbols are coded to have the minimum signal pulse width longer than one period of the receiver's sampling clock.
  • the input symbols will be preferably encoded to have a minimum signal pulse width P m j n which is at least twice as long as one period of the receiver's sampling clock, or in other terms, the minimal signal pulse width will be equal to 2 bit intervals, as illustrated in Fig.5.
  • a coding means can be described by means of a code table wherein each input symbols is assigned one or more, in the present application, two codes, when a DC balance is required.
  • the code table may be created taking into account various constraints selected from maximum and minimum pulse widths (see Fig.2), a code word width and DC balance requirement of the signal in the channel.
  • 8 bit input symbols are encoded into a 13 bit output codes in accordance with the code table provided that, in a sequence of two codes, each bit, except for the first and the last bit of the sequence, must have the same left or right neighbor bit.
  • 8 bit input symbols are encoded into 16 bit output codes in accordance with a code table which is created to produce a DC balanced signal and containing two parts of codes, one part for coding symbols with negative current disparity, and another part for coding symbols with positive current disparity, the table being such that: each input symbol corresponds to two codes, one code being from the first part of the table and the second code being from the second part; codes presented in both parts of the table shall be assigned to the same input symbol; within each code presented in the part of the table for negative current disparity, the sum of "1 "s is equal to 8 or 9; within each code presented in the part of the table for positive current disparity, the sum of "1"s is equal to 7 or 8; the current disparity is
  • the code table may be reordered to provide the optimal coder implementation such as having minimal logical terms.
  • a modification of the table of the first embodiment gives a fast and elegant means to enable 8 bit input symbols encoding into 13 bit output codes.
  • the constraints include: minimal pulse width is 2, maximal pulse width is 16, code word width is 13.
  • An implementation of the coder/decoder means for a table corresponding to these requirements can be implemented as presented in Appendix A.
  • codes reordering such that: codes are splitted into two groups with 256 codes in one group and 14 codes in the second group, wherein the codes of the first group are nonsymmetrical, while the codes of the second group are symmetrical.
  • the first group of the 256 codes can be splitted into two groups of 128 codes each, such that the center, 6 th , bit is "0", while in the second group the central bit is "1".
  • each code of the first group there is a complementary code of the second group.
  • Such symmetry provides the central bit to be assigned to one of input symbol bits.
  • each subgroup may be subdivided into two smaller groups each of 64 codes, such that the first group will comprise codes having a number built from bits from 12th to 7th bits is less than the number built from bits from 5 th to 0 bits.
  • each new subgroup for each code of the first group there is a code of the second group with a reversed bit order.
  • Such a symmetry provides the way to reduce the size of amorphous table and simplify the decoder.
  • codes may be ordered in these small subgroups to simplify the logic functions they describe.
  • a communication apparatus comprising a transmitter, a receiver, and a coding means according to the first aspect of the invention.
  • the coding means produces a code wherein the minimal signal pulse width is equal to 2 bit intervals, while the receiver takes multiple samples during each clock period to track the dynamic variation in the temporal or amplitude thresholds of the data to improve the overall coding efficiency.
  • a receiver for high speed interconnect may be used as described in GB 0131100.0 filed on 31 December 2002 claiming priority from US 60/317,216 filed on 6 September 2001 , the whole description of which application being incorporated herein by reference.
  • the receiver comprises at least one sampler for sampling data, for providing a series of signal copies, each signal copy having a
  • the samples taken by the receiver may be spread in time around a regular sampling clock that enables the dynamic shift in the received data to be tracked by matching shifts in the sampling clock or inverse shifts in delay circuitry within the receiver.
  • a coding means of the invention may be further supplemented by a decoding means to further decode the codes into respective output symbols.
  • a coding means as well as the decoding means can be implemented in hardware, such as a hub, switch, router, modem or processor, as well as in a logic element synthesised or created based on a table listing of the code alphabet.
  • the coding or decoding means may be implemented in a lookup table.
  • the code table may be splitted into subtables and an intermediate code may be computed from which the final code is determined.
  • a method of coding data represented by input symbols into codes for transmitting along a communication channel is provided using the coding means of the first aspect of the invention.
  • a method of communication including coding data represented by input symbols into codes, transmitting the codes along a communication channel, and receiving data, wherein the data are coded using a method of coding of the present invention.
  • Fig.1 shows a general block diagram of the communication channel employing the coding means according to the present invention.
  • Fig.2 shows a waveform for a signal received in a 1 GHz BW channel, with a 5ps time delay introduced into the 6GHz transmitted signal at the start of the third cycle.
  • Fig.3 shows a waveform for a signal received in a 1 GHz BW channel, where the transmitted data has rapid transitions from DC to 1/8 th cycle of 1GHz to 6GHz tone.
  • Fig.4 shows partially an eye diagram for a typical communication channel.
  • Fig 5. illustrates values of the minimal and maximal pulse width.
  • Appendix A is a description of a preferred embodiment of Fig. 1 in the Verilog
  • Hardware Description Language from which actual circuitry can be synthesised using widely used CAD tools such as Ambit from Cadence, and which can be understood easily by a person skilled in the art of modern and high speed VLSI design, including a preferred code table for encoding data of 8 bits in length.
  • Appendix B is an example of a computer program in the C++ language for generating the code tables or alphabet as required by the present invention.
  • Appendix C is an alphabet of the code table for a coding scheme as described by the present invention and in which the code is DC balanced for coding an 8 bit data word such that the minimum pulse width is two sample periods, the maximum pulse width is 9 bits and the code is DC balanced.
  • the code is presented in a table having two parts, the first being a negative disparity table, and the second a positive disparity table. After each word the current disparity is calculated in the same manner as for existing 8b/10b coders, such that if the code contains less than half 1s then the disparity after this becomes negative, if it has more 1s than half the code width then the disparity becomes positive. If the number of ones is equal to the number of zeros then disparity remains the same as in the previous cycle. The state of the disparity determines from which part of the table the symbol should be taken. The order of codes can be changed, however, codes presented in both parts of the table should preferably be assigned to the same symbol to simplify decoding.
  • Appendix D is a description of a preferred embodiment of an 8 bit data word coding into 13 bit codes as described by the present invention, in which the minimum pulse width is two sample periods, the maximum pulse width is 16 bits, code words width is 13.
  • An implementation of the decoder means for this coder is presented in Appendix E.
  • the data can be viewed in an eye diagram, such as in Fig. 4.
  • this diagram the data moves from sample point to sample point, with changes in signal polarity at a point equidistant to the centre of the eyes of each sampling point. In the examples given earlier, this amounts to sending 6GHz of data down a channel with 1GHz bandwidth (BW).
  • BW 1GHz bandwidth
  • the present invention reduces the pattern dependent shift of the data in each eye by coding the data to move from eye to eye such that instead of having the opportunity to change polarity between each eye, it must stay in a state for a given number of eyes, such as 2. The number of eyes is not reduced.
  • Fig.1 illustrating a communication system in which an input data word 2 is encoded by encoder 1 to have special characteristics as described later, the encoded data is then presented to transmitter 3, sent through communication channel 5 into receiver 7, then decoded in decoder 4 to produce a replica of the original data at output 11.
  • the transmitter and receiver can operate at higher sample or clock rates than the incoming data rate, but that data rate is still well above the bandwidth of channel 5.
  • the encoder 1 encodes the data 2 to use optimally the sampling rates available in the transmitter and receiver. Hitherto, if data is sent at a rate much higher than the channel bandwidth, for example at 6 times the channel bandwidth, then the impulse function of the channel causes the received signal to be offset and distorted such that it cannot be received reliably using a fixed threshold receiver.
  • the function of the encoding means is to reduce the effect of the impulse or filtering function of the channel.
  • Appendix D An example of a suitable encoder is given in Appendix D in the form of a hardware description in the Verilog language, from which a working encoder can be synthesised automatically using widely available CAD tools.
  • the first step in applying the present invention is to determine the requirements of the receiver, in particular, whether the code it requires must be DC balanced or not, and how many bit intervals, or clock cycles, can elapse without the signal changing, that is, the lower frequency limit, or the minimum number of transitions, of the received data. Means for doing this type of coding is well understood and widely used.
  • the next step is to determine the ratio of the maximum data bandwidth that can be sent through the channel as a continuous repetitive tone, to the maximum data rate that can be supported by the channel given maximum irregularity in the data.
  • a typical maximum data rate for data containing step changes is 3.25GHz, a 2:1 ratio. This means that the data must remain constant for two sample periods, i.e. for two bit intervals, whenever it changes.
  • the data even at 3.25GHz will have encoding, such as 8b/10b, so the useful data will be 20% lower than this, or 2.6GHz of useful data (either 2.6Gbps or 5.2Gbps depending on whether the data is clocked on one edge only or on both edges).
  • the coding scheme that is described here uses all the eye transition points, so it uses the maximum capacity of the channel given these criteria. Once the criteria are identified, the algorithm as embodied in the C++ program and the numerous obvious derivatives of this program to cover other code requirements, searches for the minimum code length that meets all the criteria, and then searches for the maximum alphabet for that code length and code constraints. For example, consider a channel where the minimum signal pulse width is two sample periods, or two bit intervals, and the minimum number of transitions of the signal is one per 16 bits.
  • the program in Appendix B can be used to find the code table, as reproduced in Appendix A.
  • This particular table is preferred because it is the smallest table meeting these two requirements.
  • the data capacity without coding is 7Gbps, which is 5.6Gbps of useful data assuming that 8b/10b coding is used in the original channel.
  • 8Gbps of real data is transmitted, a 43% increase in the real data conveyed by the channel.
  • the minimum code is probably that shown in Appendix C, which is a 8b/16b code, namely 8 bits of real data is expanded to be 16 bits.
  • This code is used by selecting 256 of the letters or entries to act as a 8b/16b code, using parity and disparity to select sequential code tables for sequential words in the same way as an 8b/10b coder.
  • the 8b/16b alphabet is 319 code words in length. In this case, compared to the channel which transmitted 7Gbps using 8b/10b encoding, the channel with 8b/16b coding can now send 6.5Gbps of real data instead of 5.6Gbps, an increase of 16%.
  • the number of codes In computing the code alphabets, the number of codes must be greater than two raised to the power of the number of bits to be sent in the original data word.
  • there are 269 codes in the alphabet which is more than 256.
  • the figure 256 is the two raised to the power of data word size, 8 bits.
  • the code has a maximum interval between transitions of 9 bits. Where the maximum interval between clock changes is increased, the efficiency of the coding system also increases. For example, if a clock transition is only required every 1024, then the number of codes rejected is a much smaller proportion to the possible alphabet than in the case with small words. This increases the maximum data rate even further.
  • a method for increasing the interval between clock changes is to apply the sampling scheme as described in US 60/317,216 of 06.09.2001 by the present inventors, in which a plurality of samples are made and the difference across these samples is used to track the data.
  • the means to track the voltage and time threshold of the received data in essence by taking a number of samples and then determining which sample is the centre of the sampling eye, can be used to greatly increase the interval in which no transitions are required.
  • these two techniques are combined to create longer code words, thus greater coding efficiency, and enable these long code words to operate reliably.
  • An alternative to computing the code in a single table lookup, or logic synthesised from the description of such tables, is to split the table into sections, such as in two sections and to compute logic value, such as a disparity value, and use this value to generate the final code in conjunction with the intermediate results from the smaller tables.
  • the list of rejected codes can be re-examined to determine if sufficient increase in the alphabet length can be achieved by linking two code words. That is, an alphabet is used to generate the first code word, then a flag or carry value is used to index a further code table such that the code applied to the subsequent data word is from a different alphabet to that used to encode the first word.
  • the code table Once the code table has been generated, it is preferred to validate the table by running all possible variations of two adjacent input data words through the coder, through an extreme worst case HSPICE model of the driver, package with parasitics, pcb, any connectors including the via or connect hole model in the pcb, receiver package with parasitics, receiver ESD structure and receiver buffer, and then into the decoder.
  • the encoder and decoder in this validation process is implemented preferably in a HDL, such as using the Verilog or VHDL languages, and confirm that the entire table meets the required objectives. This has been done for the code tables published here.
  • the present invention solves a particular problem in a communication system where the transmitter and receiver can operate reliably at frequencies well above the bandwidth of the channel.
  • the design of such systems is very complex and highly specialised, requiring the solution of a multitude of problems.
  • the present invention allocates part of the performance of the transmitter and receiver to codes which apply some of the bandwidth of the transmitted data for overcoming bandwidth deficiencies in the channel medium and interconnect.
  • the present invention thus reduces the total number of real data bits that are received, compared with a channel which simply sends the data and samples it at the receiver.
  • the present invention allows more real data to be communicated in the case where the sampling rate exceeds the channel bandwidth by a multiple of two or more.
  • module coder_8Bl3B ( clock, // clock reset, // power up reset din, // Data in cin, // C ⁇ rrmand in out) ; // data output input clock; input reset; // system reset.
  • EXTRA_SORT_EN 0 int length, min, max; int min_bits, max_bits, mid_en; int nc; int c[MAXCODES]; int dsm[MAXCODES]; int dsp[MAXCODES]; int cntm, cntp; int rmfMAXCODES]; int rp[MAXCODES]; int cntrm, cntrp; int wt[MAXCODES]; int depth; int presc, iter; char weight[2 «(MAXLENGTH-1)]; int cmp[MAXCODES][MAXCODES]; char *ofile_name; int start, end, top en, dc_bal en; int sm[MAXCODES]; int sp[MAXCODES]; int smc, spc; int
  • nc // and DC balance requirements // collect result in the stack c[].
  • Appendix C Code table for 8b/16b encoding with the same criteria of DC balance, minimum pulse width and maximum transition interval.
  • 0011001100001111 82.0001110011000111 127. 0011001100011100 83.0001110011001100 128. 0011001100110011 84.0001110011100011 129. 0011001100111000 85.0001110011110000 30 130. 0011001100111100 86.0001110011111000 131. 0011001110000011 87.0001111000000111 132. 0011001110000111 88.0001111000001111 133. 0011001110001100 89.0001111000011100 134. 0011001110011000 90.0001111000110011 35 135. 0011001110011100 91.0001111000111000 136. 0011001111000011 92.0001111000111100 137.
  • Example implementation of 8 bits into 13 bits encoding means as a synthesisable Verilog model.
  • reg cmd // output command/databar bit wire cmdj; reg cmdl_d, cmdl; // stage latch command bit wire cmdl i; reg refl, refl i, refd; // bits were reflected reg [5:2] pred; // part decode bits wire [5:2] predj; reg [ [77::00]] out, out__c, // output instruction/data out_du; // lower decode wire [7:0] outj, out_d; reg [ [1122::00] dinjatch; // input latch for encoded din reg [ [1122::00] rfljatch; // stage latch for reflected encoded din wire [12:0; rfljatchj, rfljatch_p; wire cmdtj, errtj; reg [12:0] stgjatch; reg [12:0] stgjatchj;// stage latch reg errl, errlj, errl_d; reg error

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  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)

Abstract

L'invention concerne la réduction d'artefacts introduits par l'envoi de données à un débit supérieur à la largeur de bande du canal de communication, tels que les décalages de tension et de courant introduits dans les données au niveau du récepteur comme fonction des données précédantes.
PCT/IB2003/000356 2002-02-01 2003-01-29 Moyens et procede de codage de donnees et de communication a des debits superieurs a la largeur de bande du canal WO2003065670A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/656,143 US6806817B2 (en) 2002-02-01 2003-09-08 Means and method of data encoding and communication at rates above the channel bandwidth

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GBGB0202366.1A GB0202366D0 (en) 2002-02-01 2002-02-01 Means of reducing threshold offset caused by sending data at rates above the channel bandwidth
GB0202366.1 2002-02-01
US10/079,260 2002-02-21
US10/079,260 US7092439B2 (en) 2002-02-01 2002-02-21 Means and method of data encoding and communication at rates above the channel bandwidth

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US10/656,143 Continuation-In-Part US6806817B2 (en) 2002-02-01 2003-09-08 Means and method of data encoding and communication at rates above the channel bandwidth

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4376309A (en) * 1981-05-29 1983-03-08 Bell Telephone Laboratories, Incorporated Method and apparatus for signal-eye tracking in digital transmission systems
US4486739A (en) * 1982-06-30 1984-12-04 International Business Machines Corporation Byte oriented DC balanced (0,4) 8B/10B partitioned block transmission code
EP0493044A2 (fr) * 1990-12-27 1992-07-01 Sony Corporation Modulation numérique

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4376309A (en) * 1981-05-29 1983-03-08 Bell Telephone Laboratories, Incorporated Method and apparatus for signal-eye tracking in digital transmission systems
US4486739A (en) * 1982-06-30 1984-12-04 International Business Machines Corporation Byte oriented DC balanced (0,4) 8B/10B partitioned block transmission code
EP0493044A2 (fr) * 1990-12-27 1992-07-01 Sony Corporation Modulation numérique

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