WO2003056702A1

WO2003056702A1 - Method and device for converting a quantized digital value

Info

Publication number: WO2003056702A1
Application number: PCT/FR2002/004433
Authority: WO
Inventors: Gaël CHAMPION
Original assignee: Eads Telecom
Priority date: 2001-12-26
Filing date: 2002-12-18
Publication date: 2003-07-10
Also published as: WO2003056702A8; FR2834145B1; AU2002364854A1; FR2834145A1; EP1459448A1; CA2470176A1

Abstract

The invention concerns a method and a device for converting an input digital value (Sq1) quantized in accordance with a first quantization factor (Cq1) and encoded on not more than n1 bits, into an output digital value (Sq2) quantized in accordance with a second quantization factor (Cq2) and encoded on not more than n2 bits. The method consists in multiplying the input digital value (Sq1) by an integer B, encoded on not more than β bits, to generate an intermediate digital value (C); in dividing, in fixed point, the first intermediate digital value (C) by the number 2α, where α is an integer not greater than n1+β, generating the output digital value (Sq2). The number B/2α is substantially equal to the ratio of the second quantization factor (Cq2) over the first quantization factor (Cq1). Additionally, the divider means comprise a Sigma-Delta modulator (20).

Description

METHOD AND DEVICE FOR CONVERTING A QUANTIFIED NUMERICAL VALUE

The present invention relates to the field of digital processing of the fixed-point signal. It finds applications in any digital fixed-point system, and in particular in digital modulation synthesizers used in radio transmitters and radio transceivers of a digital radio communications system.

To perform operations on binary numbers, a floating point digital system includes software resources such as a correctly programmed DSP (from the English "Digital Signal Processor"). In contrast, a fixed-point system includes only sequential logic circuits such as digital adders, digital multipliers, shift registers, or the like.

Binary numbers which are processed by a fixed point digital system encode quantized values corresponding to a real value X (for example the variable value of a radio signal received by a radio receiver, or the constant value of the frequency of a radio channel). These quantized values are represented by whole numbers between 0 and 2 ^π -1, where n is the number of bits used to code the information, if the value X is always positive, or between - (2 ^{n "1} -1 ) and 2 ^{n "1} -1 if the value X is signed (that is to say if it can be negative). By convention, we denote by Xq the quantized value which is obtained from the real value X by a quantization operation. For a linear quantification, the correspondence between the real value X (called real information) and the quantized value Xq (called quantized information), is given by the relation:

Xq = rounding (XxCq) (1) where Cq is a real number called the quantization coefficient.

The quantification of the system is determined by the number Cq, in relation to the number n. The quantization coefficient Cq is such that: rounded (| X (t) | χCq) ≤ 2n-i -1, vt, if information X is signed

(2) rounding (X (t) xCq) ≤ 2n -1, Vt, otherwise where | x | denotes the absolute value operator of the real variable x. The fact of quantifying the information X creates an error, called quantization error and denoted e, such that: _{c =} v ^χ q _^ χ rounded (XxCq)

Cq Cq '

Of course, the error e is variable, in the sense that it depends on the value X. According to the properties of the rounded function, the error e is however such that

I I 1

| E | <'. The maximum value of the quantization error, denoted e _max , is

therefore given by:

^{Θmax =} 2 ^ Cq ⁽⁴⁾

The inverse of the quantization coefficient Cq is the resolution of the digital system, i.e. the smallest variation of the actual information

1 distinguishable on quantified information. In other words, - is such that if

Cq χ ₌ _L ₊ X 'then Xq = 1 + Xq'. cq

Optimizing the dynamics of the system generally leads to defining the quantification by choosing Cq such that:

Some systems require quantification of digital data, for example to be homogeneous with analog signals after digital-analog conversion of a quantized signal. In this case, there is a quantization error increased in module by e _max = ^* * _ where Cq is the

... x q corresponding quantification coefficient. However, it may be that this resolution is insufficient to represent all or part of the digital signals of the system.

On the other hand, some digital systems use constant numeric values. In a radio transmitter or receiver, for example, such a numerical constant can represent the center frequency of a radio channel. In this case, we may find ourselves in the situation where a quantization error on the numerical constant (this error being systematic, in the sense that it does not vary "does not exceed the maximum tolerable error for the numerical representation of this constant If the system does not impose quantification of digital data, we can reduce the systematic quantization error on a determined digital constant K by choosing, even if it means not optimizing the dynamics of the system, the coefficient

quantization method Cq such that K - ^arron L ^xq <ed <e _ma , where e <j is the maximum tolerable error q for the numerical representation of the constant K. This is however not possible in a system which requires quantification digital data, such as a digital modulation frequency synthesizer for example.

This is why a first object of the invention consists in reducing the quantization errors of a digital signal and / or in correcting in digital a systematic quantification error of a digital value (in particular a constant value) without constraint on quantification, that is to say without constraint on n and on Cq.

In addition, the use in a digital system of digital data from two subsystems having respective quantifications determined by separate quantization coefficients, is only possible if one of the two quantization coefficients is an integer multiple of the other.

Indeed, if one seeks to use in the same digital system data from a first subsystem having a quantization determined by a first coefficient Cq1 with digital data from a second subsystem having a determined quantification by a second coefficient Cq2, different from Cq1, one must choose Cq1 and / or Cq2 such that

Cq2 = rχCq1 or such that Cq1 = rχCq2, where r is an integer.

We can then homogenize the data by multiplying by r the data of the first subsystem, respectively of the second subsystem.

However, this is only possible if at least one of the subsystems does not require quantification of the digital data. This is why a second object of the invention consists in making it possible to connect several digital systems to one another while ensuring the homogeneity of the data but without constraints on their respective quantifications.

According to one. first aspect of the invention, there is thus proposed a method for converting a digital input value quantized according to a first quantization coefficient and coded on at most ni bits, into a digital output value quantized according to a second coefficient quantization and coded on at most n2 bits, where ni and n2 are non-zero integers.

The method comprises the steps consisting in: a) multiplying the digital input value by an integer B, coded on at most β bits, where β is a non-zero integer, to generate a first intermediate digital value coded on at most n1 + β bits; and, b) dividing, in fixed point, said first intermediate digital value by the number 2≈, where α is an integer less than or equal to n1 + β, to generate said digital output value.

According to the invention, the number - is substantially equal to the ratio of said

second quantization coefficient on said first quantization coefficient. In addition, step b) is carried out by means of a Sigma-Delta modulator (modulator ∑-Δ). Preferably, it is a 1-Δ modulator of order 1, which is the simplest to implement.

Note that this is a digital / digital conversion, that is to say that the digital output value, like the digital input value, are quantized digital values. What changes is the quantification of this numerical value. In particular, the ∑-Δ modulator is a digital / digital modulator.

According to a second aspect of the invention, there is also proposed a device for converting a digital input value quantized according to a first quantization coefficient and coded on at most ni bits, into a digital output value quantized according to a second coefficient of quantization and coded on at most n2 bits, where ni and n2 are non-zero integers.

The device comprises multiplier means for multiplying the digital input value by an integer B, coded on at most β bits, where β is a non-zero whole number. These multiplier means generate a first intermediate digital value coded on at most n1 + β bits. The device further comprises dividing means for dividing, in fixed point, said first intermediate numerical value by the number 2≈, where α is an integer less than or equal to n1 + β. These dividing means generate said digital output value.

According to the invention, the number - ^ - is substantially equal to the ratio of said

second quantization coefficient on said first quantization coefficient. In addition, said dividing means comprise a Sigma-Delta modulator (∑-Δ).

As is known, a ∑-Δ modulator is a synchronous circuit of the sampling frequency of the input signal. It operates a quantization noise (“Noise Shaping”, in English) in the high frequencies. A signal with a quantization noise reduced in the useful frequencies is recovered at the output of the ∑-Δ modulator. On average, that is to say at low frequency with respect to the sampling frequency, the gain of the device is equal to -.

There is therefore available at the output of the ∑-Δ modulator a digital output value which corresponds, with good precision, to the digital input value multiplied by the ratio of said second quantization coefficient to the first quantization coefficient.

The principle of the invention is based on the following idea. In what follows, we denote Sq1 the digital input value (quantified information), and Cq1 the first quantization coefficient. Similarly, we denote Sq2 the digital output value (quantified information), and Cq2 the second quantization coefficient. Finally, we denote by S the real value (information not quantified) corresponding to Sq1 and Sq2. We then pose the relations below:

Sq2 = rounded (S • Cq2) (6)

whence Sq2 s rounded (S • Cql) - - ^ (7)

ie Sq2 ≈ Sq 1 • -§- (9)

2≈

with §9 | =. ^'• - (10)

. Cq1 2α '

We see that the invention has the effect of realizing relation (9) by using relation (10). It therefore makes it possible to convert the digital value Sq1 into a digital value Sq2, which are information quantified according to different quantification coefficients Cq1 and Cq2, and which both correspond to the same real information S, without any restrictive hypothesis on the relationship between one and the other of these quantification coefficients is made.

Thus, the invention makes it possible to reduce the quantization error on a real, variable or constant value. Indeed, it suffices to choose the first quantization coefficient Cq1 so as to minimize the quantization error on the digital value Sq1, and to convert this value by delivering it as digital input value to a device according to the invention for obtaining a digital output value Sq2 quantized according to a second quantization coefficient Cq2, which will be chosen to be that of the quantization of the subsystem which must use the digital input value. It is thus possible to reduce the quantization error on the digital value Sq2, without constraint on the quantification of this subsystem.

This is shown by the following calculation of the quantization error e on the real value S, in the case where the device according to the invention is used.

The expression of e is given by:

Now, Sq1 = rounded (S.Cqï).

Hence | Sql | ≤ | S.Cql | + -l and -Sq1 ≤ -S.Cq1 + ^ We deduce: e <

The choice of B and α gives § ^^^ - = ^ + ε, where ε denotes a quantity

Cq2 2≈ negligible compared to unity (ε = o (1)). He then comes

N ^≤ I H + ^ ⁽ IΨI + ^ (12)

The quantization error of the quantized value Sq2 obtained by the method according to the invention is therefore, at most, equal to the sum of a part of the maximum quantization error of the value Sq1 quantified according to the quantization coefficient Cq1 and on the other hand an image of the real value S which will generally be negligible. With a quantization according to the quantization coefficient Cq2, we would have had an error increased by ^ -.

Advantageously, to reduce the quantization error on the value Sq2 in the subsystem using this value, the value of Cq1 will be chosen such that Cq1 is greater than Cq2 (Cq1> Cq2). In the particular case where the digital value concerned is an integer, the first digital input value Sq1 is equal to the real value S (Sq1 = S) and the first quantization coefficient Cq1 is equal to unity (Cq1 = 1 ). The quantization error on Sq1 is then zero, and the quantization error on Sq2 is then minimal. In this case, the relation (12) is written: e = Sxε (13)

Furthermore, the invention also makes it possible to adapt a digital value Sq1 of a first subsystem having a first determined quantization, to a second determined quantization which is that of a second subsystem having to use this numerical value, without constraint on the respective quantifications of these two subsystems. Indeed, it suffices to supply this digital value Sq1, as the digital input value, to a device according to the invention, in which said first coefficient quantization Cq1 is chosen equal to that of said first determined quantization, and in which said second quantization coefficient Cq2 is chosen equal to that of said second determined quantization.

According to a third aspect, the invention proposes a frequency synthesizer with digital modulation, comprising a phase locked loop comprising a frequency divider with variable ratio in the return channel. The division ratio of said divider is controlled by a digital value obtained in particular from a real value corresponding to the center frequency of a radio channel. The synthesizer further comprises a conversion device as defined above, to reduce the quantization error on said real value.

Other characteristics and advantages of the invention will become apparent on reading the description which follows. This is purely illustrative and should be read with reference to the accompanying drawings in which: - Figure 1 is a block diagram of a device according to the invention;

- Figure 2 is a flow diagram of the steps of a method according to the invention;

- Figure 3 is a block diagram of a first embodiment of the device of Figure 1; - Figure 4 is a block diagram of a second embodiment of the device of Figure 1;

- Figure 5 is a diagram illustrating the application of a mask to a determined numerical value;

- Figure 6 is a block diagram of a third embodiment of the device of Figure 1; and,

- Figure 7 is a block diagram of a synthesizer with digital modulation incorporating a device according to the invention.

In Figure 1, there is shown the block diagram of a device according to the invention. The device comprises an input 1 for receiving a digital input value Sq1 which is a quantized value of a variable or constant real value. The value Sq1 is quantized according to a first quantization coefficient Cq1, and coded on at most neither bits, where ni is an integer not bad. The device also includes an output 2 for delivering a digital output value Sq2. The value Sq2 is quantized according to a second quantization coefficient Cq2, and coded on at most n2 bits, where n2 is a non-zero integer. The device also includes means such as a digital multiplier 10, for multiplying the digital input value Sq1 by an integer B, coded on at most β bits, where β is a non-zero integer. The means 10 generate a first intermediate digital value C coded on at most n1 + β bits. The device also comprises dividing means, for dividing, in fixed point, said first intermediate numerical value C by the number 2 <, where α is an integer less than or equal to n1 + β. These dividing means generate the digital output value Sq2.

According to the invention, these dividing means comprise a Sigma-Delta 20 modulator, receiving the intermediate value C at input, and delivering the digital output value Sq2 at output. The ∑-Δ modulator is a digital / digital modulator, receiving as input a digital value coded on n1 + β bits, and delivering as output a digital value coded on n1 + β + 1-α bits. Preferably, it is a 1-Δ modulator of order 1, which is the simplest to implement. Nevertheless, it is possible to envisage embodiments with a higher order ∑-Δ modulator.

According to the invention, moreover, the number - ^ - is substantially equal to the

ratio - ^ L of the second quantization coefficient Cq2 on the first

coefficient of quantification Cq1. As was said in the introduction, such a device converts the digital value Sq1 quantized according to the quantization coefficient Cq1, into the digital value Sq2, quantified according to the quantization coefficient Cq2.

Figure 2 is a flowchart illustrating the steps of a method according to the invention. The method is implemented by a device as described above with reference to FIG. 1. In a step 100, the digital input value Sq1 is received. In a step 200, the value Sq1 is multiplied by the number B, to generate the first intermediate digital value C.

In a step 300, the first intermediate digital value C is divided, in fixed point, by the number 2 < ^χ , to generate the digital output value Sq2. According to the invention, step 300 is carried out using a Sigma-Delta modulator. In addition, the number - ^ - is substantially equal to the

report ^.

The diagram in FIG. 3 illustrates a first embodiment of a device according to the invention, suitable for the implementation of a first variant of the method.

In this first embodiment, the Sigma-Delta modulator 20 comprises means 21 such as a digital adder receiving as input the first intermediate digital value C as the first operand on the one hand, and a digital error value E as a second operand on the other hand. This is coded on at most α bits. The means 21 output a second intermediate digital value D coded on at most n1 + β + 1 bits.

In addition, the device comprises selection means 23, such as a digital discriminator, for selecting the n2 most significant bits of the second intermediate digital value D as the digital output value Sq2, and for selecting the α bits the less significant of the second intermediate numerical value D as a numerical error value E. It follows that n2 is equal to n1 + β + 1-α. The means 23 receive the value D at input, and deliver the value Sq2 as well as the value E at output.

A digital discriminator is a circuit separating the k most significant bits and the j least significant bits of a given digital input value, to generate two digital output values coded respectively on k bits and on j bits, and having for value the corresponding value respectively audits k most significant bits and audits j least significant bits. Here, the discriminator 23 separates the n1 + β + 1-α most significant bits from the second numerical value intermediate D on the one hand, and the least significant α bits of the value D on the other hand.

The diagram of Figure 4 illustrates a second embodiment of a device according to the invention, suitable for the implementation of a second variant of the method.

In this second embodiment, the selection means 23 of the device comprise an operator 24 for shifting to the right by α bits. Such an operator is for example produced using a properly controlled shift register. This operator 24 receives as input n1 + β + 1 bits of the second intermediate digital value D. It delivers as output the n1 + β + 1-α most significant bits of the second intermediate digital value D as the digital value of Sq2 output.

Furthermore, the selection means 23 also comprise means 25 for applying a mask to the second intermediate digital value D.

Such a mask is shown in FIG. 5 under the reference M. It is a digital value stored in an appropriate register, having at most n1 + β + 1 bits, of which the n1 + β + 1-α bits are most significant are equal to logical value 0, and whose least significant α bits are equal to logical value 1. When combined with the second intermediate digital value D in a logical AND type operation, it allows to select the least significant α bits of said second intermediate digital value D.

In other words, the means 25 receive as input the n1 + β + 1 bits of the second intermediate digital value D. They deliver as output the n1 + β + 1- α most significant bits of the second intermediate digital value D as the numerical error value E.

The diagram in FIG. 6 illustrates a third embodiment of a device according to the invention, suitable for the implementation of a third variant of the method. In this third embodiment, the selection means 23 of the device always include an operator 24 of right shift of α bits, having the same function as the operator 24 of the device of FIG. 4. In addition, the selection means 23 comprise an operator 26 for shifting to the left by α bits receiving as input the n1 + β + 1-α bits of the digital output value Sq2 and outputting a third intermediate digital value F, coded on at most n1 + β + 1 bits. The operator 26 is for example a properly controlled shift register. They also include an operator 27, to make the difference between the intermediate digital values F and C. The operator 27 is for example a digital subtractor. It receives the third intermediate numeric value F as the first operand, and the first intermediate numeric value C as the second operand. It outputs the digital error value E.

In each of the three embodiments described above with reference to FIGS. 3, 4 and 6, the device preferably comprises an operator 22 applying a unit delay to the digital error value E, for reasons of synchronization. In other words, the error signal E is supplied at the input of the adder means 21 through a unit delay operator 22.

FIG. 6 shows the diagram of a digital modulated frequency synthesizer, better known by the term DMS (from the English “Digitally Modulated Synthesiser”), which incorporates a device according to the invention.

Such a circuit can be used for the generation of a radiofrequency signal (in the UHF band between 400 and 600 MHz) modulated in frequency or in phase. It finds applications in the transmitters or transceivers of a radiocommunication system, in particular in the base stations and / or in the mobile terminals of such a system.

A DMS presents an architecture which is derived from the structure of an N-fractional frequency synthesizer, and makes it possible to generate a periodic signal modulated in frequency or in phase.

The DMS comprises a phase locked loop or PLL (from the English "Phase Locked Loop") comprising, in series in a direct channel, a phase / frequency comparator 11 or PFC (from the English "Phase / Frequency Comparator "), A loop filter 12 such as an integrator, and a voltage controlled oscillator 13 or VCO (from the" Voltage Controlled Oscillator "), as well as, in a return channel, a frequency divider 14. The VCO outputs a signal S ₀ ut q ^u ' ^est ' ^e output signal DMS, whose instantaneous frequency is f _or t. The PFC receives on a first input a reference signal S _re f having a reference frequency f _rθ f and, on a second input, a signal SCJJ _V delivered by the frequency divider 14 from the signal S _or t. For a conventional N-fractional synthesis, the frequency divider 14 is a variable ratio divider making it possible to produce the signal Sςjj by dividing the frequency f _or t of the signal S ₀ ut P ^{by a} division ratio which is alternately equal to an integer N during part of the time T1, and the integer N + 1 during the rest of the time T2. In this way, the frequency f ₀ ut of the output signal S _or t is given as a function of the frequency f _re f of the reference signal S _re f, by:

In a digital modulation synthesizer, the frequency divider

14 has an input for controlling the division ratio. This ratio is fixed by the value stored in a determined accumulator. However, in order to avoid the appearance of parasitic lines in the spectrum of the output signal S _or t due to the periodicity of the changes in the division ratio from N to N + 1 and vice versa, a DMS known in the state of l art also comprises a modulator 15, of the type of a digital / digital ∑-Δ modulator. The modulator 15 has an input which receives a digital frequency or phase modulation value S _moc (coded on k bits, and an output which delivers a digital value S ' _moc j corresponding to the scrambled value S _m0 , and coded on j bits The output of the modulator 15 is connected to a first input of a digital adder 16, the second input of which receives a digital value N ₀ which defines the bottom of the frequency band addressed by the synthesizer. adder 16 delivers a digital value S _c . It is connected to the control input of the divider 14 to deliver the value S _{c there} .

The DMS also includes a second digital adder 17, a first input of which receives a digital value Sj _n f ₀ and a second of which input receives a digital value S _c h2- The output of adder 17 delivers the aforementioned digital frequency or phase _modulation S _{mocj value} .

The digital value Sj _n f ₀ contains the modulation information (modulating signal), that is to say the useful information to be transmitted. The digital value S _cn 2 corresponds to the central frequency of the radio channel (after addition of the above-mentioned value N ₀ ).

The numerical values Sj _n f ₀ , S _C h2, S _m0 d. ^s ' mod ^{and N} o ^are values quantized according to a quantization coefficient Cq2 of the digital system constituted by the DMS. According to the invention, the digital value S _C h2 is delivered by a converter device 18 as described above with reference to FIGS. 2 to 6, from a digital value S _cn qi stored in an appropriate register. The quantized values S _cn ι and S _cn 2 correspond to a real value which is the central frequency of the channel denoted F _cn in the following. The actual value F _C h is constant because the value of the central frequency of the channel is constant. In the absence of the device 18, the real value F _C h would be directly quantified according to the quantization coefficient Cq2 of the system constituted by the DMS.

Nevertheless, the DMS presented here incorporates a device 18 according to the invention, in order to reduce the quantization error on the quantized digital value corresponding to the real value F _cn (which is a systematic error since this value is constant). In other words, the DMS comprises a device 18 for converting the digital value S _cn ι into a digital value S _cn 2 quantified according to the quantization coefficient Cq2 of the system constituted by the DMS. In application of the above, we therefore choose to implement a converter device 18 of the type described above, for which Cq1 is equal to unity (Cq1 = 1, because the real value F _c h is integer) and for which Cq2 is the quantification coefficient for the quantification of DMS.

A numerical example is given below to illustrate the advantages provided by the invention in this application. In this example: • F _re p9.6 MHz (megahertz); • k = 22; • j = 4;

• F _c h = 400017.5 kHz (kilohertz);

• N ₀ = rounded (395 MHz / F _re f); • ed = 4 Hz (Hertz).

The frequency resolution of such a DMS is given by - ^ r, where k is the

number of bits at the input of the Sigmà-Delta 15 modulator, and where j is the number of bits at the output of this modulator. The frequency resolution of the DMS, i.e. - = r-, is therefore: Cq2

The value F _m j _n corresponding to the bottom of the frequency band addressed by the DMS, is determined by the digital value N ₀ according to the relation F _m j _n = NoxF _re f. So here, F _m j _n = 41x9.6.10 ⁶ = 393.6 MHz.

Let us first consider what the situation would be without the device 18 according to the invention, that is to say if we had Sch1 = Sch2. We would have: Fch2 = rounded [(F _c h -F _m j _n ) .Cq2] = 175241

The systematic quantization error on the center frequency of the radio channel would therefore be:

that is to say :

e = 400017.5.10 ³ - ¹⁷⁵²⁴¹ + 393.6.10 * = -17.08Hz

CQ2

This value exceeds (in absolute value) the acceptable error ed. Let us now consider what is happening with the conversion device 18 according to the invention. Since the signal we are trying to represent is integer, we have Cq1 = 1. One chooses the following approximation: CQ2 ≈ j- = ²² ^ _o2 ⁶⁵ • ^In other ^words,

we choose to implement a device according to the invention with B = 229065, and α = 23. ^'

The quantization error can be determined using the relation (13) given in the introduction which is valid in the case where the real numerical value at the input of the device (here, the constant value F _c hF _m j _n ) is an integer.

It is recalled that this relation is then written:

e = S.ε = S Cq1 _B 2.17 Hz

Cq2 2α where S denotes the real numerical value at the input of the device (here F _c - Hence it comes that e = .2.17 Hz. We have therefore reached the objective of a quantization error on the value of the central frequency of the radio channel less than 4 Hz, without having to modify the quantization of the system The invention makes it possible here to reduce the systematic quantization error on the value of the central frequency of the radio channel from 17 Hz to 2 Hz. best result could be achieved by increasing the accuracy of

the approximation of - ^ but at the cost of an increase in the number β and the

number α.

Claims

1. Method for converting a digital input value (Sq1) quantized according to a first quantization coefficient (Cq1) and coded on at most ni bits, into a digital output value (Sq2) quantized according to a second quantization coefficient (Cq2) and coded on at most n2 bits, where ni and n2 are non-zero integers, comprising the steps of: a) multiplying the digital input value (Sq1) by a whole number B, coded on at most β bits, where β is a non-zero integer, to generate a first intermediate digital value (C) coded on at most n1 + β bits; b) divide, in fixed point, said first intermediate numerical value (C) by the number 2≈, where α is an integer less than or equal to n1 + β, to generate said numerical output value (Sq2), according to which the number - ^ is substantially equal to the ratio of said

second quantization coefficient (Cq2) on said first quantization coefficient (Cq1); and according to which step b) is carried out by means of a modulator

Sigma-Delta.

2. Method according to claim 1, according to which step b) comprises the steps consisting in: b1) adding said first intermediate digital value (C) on the one hand, and a digital error value (E) coded on at plus α bits on the other hand, to generate a second intermediate digital value (D) coded on at most n1 + β + 1 bits; b2) selecting the most significant n2 bits of said second intermediate digital value (D) as the digital output value (Sq2), where n2 is equal to n1 + β + 1-α; b3) selecting the least significant α bits of said second intermediate digital value (D) as a digital error value (E).

3. Method according to claim 2, according to which step b2) and step b3) are carried out jointly using a discriminator, making it possible to separate said n1 + β + 1-α most significant bits from said second intermediate digital value (D) on the one hand, and said α least significant bits of said second intermediate digital value (D) on the other hand.

4. Method according to claim 2, according to which step b2) is carried out by a right shift operation of α bits applied to the n1 + β + 1 bits of the second intermediate digital value (D).

5. Method according to claim 4, according to which step b3) is carried out by applying to the second intermediate digital value (D) a mask having at most n1 + β + 1 bits, of which the n1 + β + 1-α bits the most significant ones are equal to the logical value 0, and whose least significant α bits are equal to the logical value 1.

6. Method according to claim 4, according to which step b3) is carried out on the one hand by a shift operation to the left of α bits applied to the n1 + β + 1- bits of the digital output value (Sq2) allowing generating a third intermediate digital value (F) coded on at most n1 + β + 1 bits, and on the other hand by a difference operation between said third intermediate digital value (F) and said first intermediate digital value (C).

7. Method according to any one of the preceding claims, according to which neither of the first nor of the second quantization coefficients is an integer multiple of the other

8. Device for converting a digital input value (Sq1) quantized according to a first quantization coefficient (Cq1) and coded on at most ni bits, into a digital output value (Sq2) quantized according to a second quantization coefficient (Cq2) and coded on at most n2 bits, where ni and n2 are non-zero integers, comprising: - multiplier means (10) for multiplying the digital input value (Sq1) by an integer B, coded on at most β bits, where β is a non-zero integer, generating a first intermediate digital value (C) coded on at most ni + β bits; - divider means for dividing, in fixed point, said first intermediate numerical value (C) by the number 2 ", where α is an integer less than or equal to n1 + β, generating said digital output value (Sq2), in which number - ^ - is substantially equal to the ratio of said

second quantization coefficient (Cq2) on said first quantization coefficient (Cq1); and wherein said dividing means comprises a Sigma-Delta modulator (20).

9. Device according to claim 8, in which the Sigma- modulator

Delta (20) is a first order Sigma-Delta modulator.

10. Device according to claim 9, in which the Sigma-Delta modulator (20) comprises: - adding means (21) receiving as input said first intermediate digital value (C) as first operand on the one hand, and a digital error value (E) coded on at most α bits as a second operand on the other hand, and outputting a second intermediate digital value (D) coded on at most n1 + β + 1 bits; selection means (23) for selecting the n2 most significant bits of said second intermediate digital value (D) as the digital output value (Sq2), where n2 is equal to n1 + β + 1-α, and to select the least significant α bits of said second intermediate digital value (D) as a digital error value (E).

11. Device according to claim 10, in which said selection means (23) consist of a discriminator making it possible to separate said n1 + β + 1-α most significant bits of said second intermediate digital value (D) on the one hand, and said α least significant bits of said second intermediate digital value (D) on the other hand.

12. Device according to claim 10, in which said selection means (23) comprise a shift operator to the right of α bits (24) receiving as input the n1 + β + 1 bits of the second intermediate digital value (D), and outputting the n1 + β + 1-α most significant bits of the second intermediate digital value (D) as the digital output value (Sq2).

13. Device according to claim 12, in which said selection means (23) further comprises means (25) for applying to the second intermediate digital value (D) a mask (M) having at most n1 + β + 1 bits , whose most significant n1 + β + 1-α bits are equal to logical value 0, and whose least significant α bits are equal to logical value 1, so as to select the least significant α bits of said second intermediate numeric value (D) as the numerical error value (E).

14. Device according to claim 12, in which said selection means (23) further comprise, on the one hand, a shift operator to the left of α bits receiving as input the n1 + β + 1-α bits of the digital value output (Sq2) and outputting a third intermediate digital value (F) coded on at most ni + β + 1 bits, and on the other hand a difference operator receiving said third intermediate digital value (F) as first operand and said first intermediate digital value (C) as a second operand, and outputting said digital error value (E).

15. Device according to any one of claims 10 to 14, in which the error signal (E) is supplied at the input of the adder means (21) through a unit delay operator (22).

16. A digitally modulated frequency synthesizer, comprising a phase locked loop (PLL) comprising a variable ratio frequency divider (14) in the return path, in which the division ratio is controlled by a numerical value (Sc ) obtained in particular from a real value (F _cn ) corresponding to the central frequency of a radio channel, the synthesizer further comprising a conversion device (18) according to any one of claims 8 to 15 to reduce the quantization error on said actual value.