WO2003053043A1 - Imageur cmos pour applications de pointage et de poursuite - Google Patents

Imageur cmos pour applications de pointage et de poursuite Download PDF

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Publication number
WO2003053043A1
WO2003053043A1 PCT/US2002/040206 US0240206W WO03053043A1 WO 2003053043 A1 WO2003053043 A1 WO 2003053043A1 US 0240206 W US0240206 W US 0240206W WO 03053043 A1 WO03053043 A1 WO 03053043A1
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Prior art keywords
array
memory array
active pixel
pixel sensor
sampling
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PCT/US2002/040206
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English (en)
Inventor
Bedabrata Pain
Chao Sun
Guang Yang
Julie Heynssens
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California Institute Of Technology
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Priority to AU2002351387A priority Critical patent/AU2002351387A1/en
Publication of WO2003053043A1 publication Critical patent/WO2003053043A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/767—Horizontal readout lines, multiplexers or registers

Definitions

  • CMOS complementary metal oxide semiconductor
  • CMOS imagers can provide low-cost, low-power, reliable, highly integrated and miniaturized imaging systems.
  • the availability of sub-micron processing technology, coupled with the advent of active pixel imaging concepts, has led to the development of high performance CMOS imagers .
  • CCD image sensors generally require more power than CMOS image sensors, are frequently more expensive, and are generally more limited in high-speed operation capabilities and signal handling capacity.
  • CCDs can generate centroiding errors due to radiation-hit, variable smear, and large power dissipation.
  • CCDs are commonly used in many applications due to other advantages over CMOS imagers.
  • CCDs are commonly used in space-based applications, such as in space guidance and navigation systems, and deep-space optical communication systems, which require accurate and stable beam pointing for high speed data transfer.
  • CCDs are frequently used in space- based applications because of their wide availability (CCDs have been used in space imaging applications since the 1970s) , relatively low noise, fairly uniform response, and large dynamic range characteristics.
  • CCD chips are frequently used in star tracking applications.
  • a star tracker is used by almost all spacecraft to determine three-axis attitude.
  • a star tracker is an electronic camera connected to a computer. Using a sensed image of a portion of the sky, stars can be located and identified, and the orientation of the spacecraft can be determined based on these observations.
  • Traditional CMOS imagers have typically been not well suited to such pointing and tracking applications.
  • Star trackers have been commercially available for more than a decade. Commercial star trackers typically have a mass of a few kilograms and a power consumption of approximately 10 Watts. Commercial star trackers can be made radiation tolerant up to approximately 100 KRads . Moreover, with a Charge Injection Device (CID) and extensive shielding, a star tracker can be made to withstand very high radiation levels (e.g., potentially up to 4 Mrads) . However, CID chips tend to be very noisy, and are generally only desirable in extreme radiation environments.
  • CID Charge Injection Device
  • the present disclosure includes systems and techniques relating to CMOS imaging devices for use in pointing and tracking applications.
  • the technique includes sampling multiple rows and multiple columns of an active pixel sensor array into a memory array, and reading out the multiple rows and multiple columns sampled in the memory array to provide image data with reduced motion artifact.
  • the memory array can be an on-chip analog memory array.
  • Various operation modes may be provided, including Time Difference Sampling (TDS) , correlated double sampling (CDS) , correlated quadruple sampling (CQS) , one or more tracking modes to read out multiple windows in the active pixel sensor array, and/or a mode employing a sample-first- read-later readout scheme.
  • the one or more tracking modes can take advantage of a diagonal switch array coupled between the active pixel sensor array and the memory array.
  • the diagonal switch array, the active pixel sensor array and the memory array can be integrated onto a single imager chip with a controller (e.g., one or more on-chip control blocks) .
  • This imager device can be part of a larger imaging system for both space-based applications and terrestrial applications.
  • One or more of the following advantages may be provided.
  • An imager architecture can provide integrated on- chip timing and control and A/D conversion in a CMOS imager resulting in a low-power device, with increased resistance to radiation, offering great advantages for space-based applications.
  • the imager architecture can result in reduced complexity and reduced power requirements, as well as enhance system miniaturization.
  • the imager can be a CMOS imager with multiple operating modes, including a star tracking mode with multiple data fetch from a single command.
  • CMOS imager with multiple operating modes, including a star tracking mode with multiple data fetch from a single command.
  • star tracking mode with multiple data fetch from a single command.
  • a CMOS photodiode imager using the disclosed architecture can be compatible with high speed pointing and tracking applications, while providing ultra-low noise during tracking of objects within one or more of multiple windows of interest.
  • the CMOS imager can provide multi-window readout support from the same frame, and minimal smear and window-skew by using a sample-first-read-later mode of operation.
  • An on- chip timing and control block can enable various program, configuration, sequencing, and readout functions, allowing readout of multiple windows with variable size from a single command.
  • the CMOS photodiode imager can provide high dynamic range, high quantum efficiency, and high operating speed, and can include a high performance imager pixel .
  • FIG. 1 is a block diagram of an example imager.
  • FIG. 2A illustrates a conventional APS row-at-a-time operation.
  • FIG. 2B illustrates a sample-first-read-later operation mode.
  • FIG. 3 shows a CMOS multi-window imager according to an implementation.
  • FIG. 4 illustrates timing information for multiple operation modes.
  • FIG. 5 illustrates additional timing information for multiple operation modes.
  • FIG. 6 shows a CMOS multi-window imager according to an implementation.
  • FIG. 7 illustrates additional details regarding the memory block and control logic shown in FIG. 6.
  • FIGS. 8 and 9 illustrate selected portions of a pixel array, switch network, memory array, and readout switch array according to an implementation.
  • FIG. 10 illustrates a diagonal switch network
  • FIG. 11 illustrates pixel sample and readout in an example op-comm mode of operation.
  • FIG. 12 illustrates an example CMOS imager memory architecture for improved capacitor matching.
  • FIG. 13 illustrates another operational mode applied to the hardware shown in FIGS. 8 and 9.
  • FIG. 14 illustrates an example four sample mode of operation.
  • FIG. 15 is a block diagram illustrating an example imager application.
  • CMOS imaging devices for use in pointing and tracking applications.
  • the discussion below focuses on space-based implementations for star tracking and optical communications, but the systems and techniques described, which take advantage of VLSI system integration and of CMOS imaging technology, apply equally to other contexts, such as industrial robotics, machine vision, autonomous navigation, and various military applications .
  • FIG. 1 is a block diagram of an example imager 100.
  • the imager 100 uses an imager architecture that is compatible with random-access of pixels, as well as with integration of control circuitry for access of multiple windows of data in response to a single command.
  • the imager 100 can be a CMOS imager built on a single chip, and can be fabricated to be ideally suited for star-tracking applications.
  • the imager 100 can include an interface tailored to a tracking application (e.g., multiple data fetch from a single command) , integration of timing and control, and an on or off-chip Analog to Digital (A/D) converter. These aspects combined with random-access enables the development of a compact, miniature and low-power star-tracker.
  • A/D Analog to Digital
  • the imager 100 may have multiple operating modes, including a tracking mode, in which the star-tracker handles data from a few regions of interest (i.e. where the stars are) . These regions of interest typically constitute only a fraction of a percent of the total data from the entire field of view.
  • a tracking mode in which the star-tracker handles data from a few regions of interest (i.e. where the stars are) . These regions of interest typically constitute only a fraction of a percent of the total data from the entire field of view.
  • the imager architecture allows a reduction of data transferred to downstream processors. This can provide an order of magnitude reduction in complexity and power, and can significantly enhance miniaturization of the system.
  • CMOS imagers are generally radiation-hard (once manufactured in appropriates foundries) not only with respect to ionizing radiation but also with respect to protons and other heavy ions as well, offering great advantages for space- based applications.
  • the imager 100 includes a control architecture having an on-chip timing and control block that enables program, configuration, sequencing, and readout out of multiple windows with variable size from a single command.
  • the imager 100 can also include an on-chip high accuracy A/D converter 190 (e.g., a high accuracy 13 bit A/D converter) .
  • the readout architecture can include imager organization and timing to provide: (1) ultra-low noise (e.g., less than five electrons) during tracking at high readout rate (e.g., 10 MHz) , and (2) no smear and minimized motion artifact through suppression of any rolling shutter effect.
  • the imager 100 can include a pixel array 110, a diagonal switch array 120, a memory array 130, memory controller 140, column controller 160, and row controller 170.
  • the pixel array 110 can be a mega pixel (1024x1024) CMOS imaging array, controlled and sequenced by an on-chip timing and control block.
  • the array 110 can be an active pixel sensor (APS) array, and can include photogate, photodiode, or binned photodiode pixels.
  • the pixels can be photodiode pixels, which each have a common photo-conversion and sense node, at a pixel pitch of 9 ⁇ m.
  • the pixel array 110 can be a high performance imager pixel array that is both highly symmetrical and tailored to high performance image capture .
  • the imager 100 can support and sequence multiple regions of interest that can be of variable sizes, such as eight different windows of up to 8x8 size within a single frame.
  • the imager can support both acquisition and tracking modes, by allowing both full-frame imaging and multi-windowed imaging.
  • This multi-mode imager can be used in space-based applications, such as a miniature star tracker, or terrestrial applications, such as a laser communications system.
  • a CMOS imager chip employing the present architecture can handle multiple windows of interest simultaneously, provide a simple command interface to streamline operation, and support low noise imaging.
  • the disclosed APS can operate in a sample-first-read-later mode.
  • the pixels corresponding to the windows of the interest e.g., the regions containing the guide stars
  • the memory array 130 is large enough to hold differential signals from all of the multiple windows for the entire frame.
  • the memory array 130 can be read out using a read out block 150, which can use a source follower or a capacitative transimpedance amplifier (CTIA) readout using a single o amp .
  • CTIA capacitative transimpedance amplifier
  • the maximum readout rate can be a 10 MHz data rate.
  • FIG. 2A illustrates a conventional APS row-at-a-time operation 200.
  • This schematic diagram of the row timing shows a conventional rolling shutter operation in which pixels in each row are simultaneously sampled at the bottom of the column, followed by readout of these pixels.
  • Row N is sampled at 205 and read at 210.
  • Row N+l is sampled at 215 and read at 220.
  • Row N+2 is sampled at 225 and read at 230.
  • row sampling and pixel readout phases interleave with each other. This can lead to exposure skew and may impact the accuracy of the imaging system.
  • FIG. 2B illustrates a sample-first-read-later operation mode 250.
  • all pixels of interest are sampled rapidly into the memory array, with the memory address and diagonal switch-address being internally generated by the on-chip controller.
  • the memory array is sequentially read out (e.g., sampling may take about 1 ⁇ s, and readout may take about 100 ⁇ s) .
  • the window size is smaller than the maximum for the number of windows (e.g., 8x8 for eight windows), the unwanted memory pixels are skipped.
  • M rows are sampled at 255, then the M rows are read out at 260.
  • the readout sequence can be entirely controlled by the on-chip controller.
  • the imager can operate with ultra-low noise.
  • a common source of noise in a photodiode type APS pixel is the reset noise at the sense node, when the device is operated in the conventional row-at- a-time readout.
  • row sampling and pixel readout phases can be temporally separated, as shown in FIG. 2B. This allows reset levels for an entire frame to be stored in the memory array, and subsequently used as a reference during the differential readout.
  • CDS on-chip correlated double sampling
  • the read noise that remains is generally limited to the noise associated with sampling the pixel signal and reset levels into the memory array.
  • the read noise can be expected to be less than 5 e ⁇ .
  • the imager can revert to a row-at-a-time readout mode, with consequently higher read noise of around 30 e ⁇ .
  • the imager can be implemented using a twin-well CMOS process provided by Tower Semiconductor Ltd. Of Migdal Haemek, Israel. This is a double poly triple metal 0.5 ⁇ m process with low-dark current.
  • the diode can be implemented between the moderately doped n-well (approximately 10 17 /cm 3 ) and the p-epitaxial layer.
  • the epitaxial layer can be chosen to have low doping in order to increase the depletion width, and to provide good quantum efficiency and low diffusion cross talk.
  • the pixel structure can also be made compatible with reverse-illumination following backside thinning that involves etching the heavily doped p-substrate, with the p-epi forming the natural etch-stop.
  • a special pixel layout that involves passivation of the surface-states can be employed for reducing the dark current to less than 75 pA/cm 2 .
  • the pixel layout can be symmetric in order to eliminate non- symmetric responses in the two directions and/or systematic errors .
  • the imager can also feature a linearizer circuit, such as the column-based hard-to-soft (HTS) circuit developed at Jet Propulsion Laboratories ( JPL) , in order to provide excellent low-light-level linearity in spite of soft-reset.
  • HTS hard-to-soft
  • JPL Jet Propulsion Laboratories
  • FIG. 10 For further details of the HTS circuit, see U.S. Patent Application No. 09/677,972, filed October 2, 2000 and entitled "HIGH-SPEED ON-CHIP WINDOWED CENTROIDING USING PHOTODIODE- BASED CMOS IMAGER", and issued as U.S. Patent No. X,XXX, XXX on MONTH DAY, YEAR.
  • This circuit can be used in the full-frame mode of operation. In the sample-first-read-later mode of operation, the use of CDS minimizes the relevance of soft- reset related issues.
  • the imager architecture includes an on-chip controller that allows configuration and sequencing of multiple windows, thus allowing simplified integration and configuration of the windows within a given frame. Furthermore, the architecture allows handling of windows that have either row or column address overlap. In order to sequence multiple windows, the on-chip controller can use internal flags to keep track of the current window and the next window to be sequenced.
  • a diagonal switch array can be activated to route in only the columns belonging a current window. Once the current window has been sequenced, the controller can skip to the next address, and load in the subsequent window address from an input register. If row- address overlap between windows is detected, the controller can enable two diagonal switch arrays to route the respective columns into separate memory arrays.
  • the memory array can be organized as 4 parallel arrays of 8 pixels wide, with a height of 65 pixels, with the adjacent memory sub-arrays reserved for corresponding reset and signal values for a given pixel.
  • the memory array can handle two separate windows at a time, with a total of 8 windows per frame.
  • the window size is also programmable. Table 1 below summarizes the expected performance of an example CMOS imager built using the architecture described.
  • Table 1 above only describes expected performance for one example implementation. Other implementations may have different performance characteristics.
  • the sample-first-read-later operation mode can be employed more generally, and the imager need not be integrated onto a single chip.
  • the pixel array could be on a first chip, and the memory and readout block can be on a second chip either above or below the first chip.
  • Vertical interconnects may be used to connect the pixel array and the memory in such an implementation.
  • the diagonal switch array can contribute to an overall very low power operation mode. For example, in a mode designed to read out multiple arbitrarily sized windows, only a portion of the pixel array may need to be sampled.
  • the diagonal switch array and the sampling mode can be configured such that no current needs to be drawn on pixels that are outside the windows.
  • a very low power device By only drawing current to sample pixels that fall in the selected windows, which correspond to regions of interest, a very low power device may result, which can be of particular use in a star tracker system.
  • use of one or more diagonal switch arrays in combination with one or more memory arrays, which may be in the focal plane of the chip, can result in a very efficient use of chip space, thus making smaller imaging system possible.
  • the imager chip can sample windows in the active pixel array while accessing only those pixels that are to be read into the memory array.
  • FIG. 3 shows a CMOS multi-window imager 300 according to an implementation.
  • the imager 300 includes a memory array, which may have logically distinct parts, and corresponding switch network, and the imager 300 supports multiple operation modes, including a full-frame mode, an optical-communication (op-comm) mode, and a star-tracker mode.
  • the full-frame mode may use two pointers, such as described below, to sample and read out the entire pixel array.
  • the op- comm mode may use two pointers in either a CDS or TDS (Time Difference Sampling) mode, such as described below, to sample and read out up to two windows, with no overlap, and the windows being of variable size up to 32x32.
  • the star-tracker mode may use one pointer in either a CDS or a TDS mode, such as described below, to sample and read out up to eight windows, with two-window overlap allowed, and the windows being of variable size up to 8x8.
  • Providing both TDS and CDS modes as described, provides additional versatility for the imager.
  • the CDS mode provides reset noise suppression, and the TDS mode runs faster.
  • an imager chip can be configured to operate in one or more different modes based on requirements for the larger system. Having both TDS and CDS modes available can be of particular use when the APS array is a photodiode array.
  • switch networks and corresponding column address latches are used to sample the pixel array into the memory.
  • the various arrows in FIG. 3 illustrate in general how data propagates through the imager 300.
  • control logic includes a multi-window state machine and register, memory store and readout control logic, column starting address decoder, row decorder, row driver, image column decoder, and signal chain components.
  • Various opamps and opamp timing control circuitry can be used to facilitate image output and readout.
  • programmable features of the imager 300 can be configured using inputs as shown: (1) operational mode, (2) number of windows, (3) window size, (4) starting address, and (5) integrating time. [0052] Multiple windows, corresponding to multiple objects of interest, can be handled using a single command. Four example windows, including two overlapping windows, are shown on the pixel array.
  • FIG. 4 illustrates timing information 400 for multiple operation modes.
  • the timing information 400 includes operations to sample data needed for correlated double sampling.
  • a reference level, a reset level and a signal level can be stored for each pixel.
  • the reset levels for frame 2 can also be obtained; the signal level comes at the end of integration, but the end of integration is also the beginning of integration of the next frame, and the reset level comes at the beginning of integration.
  • pixel sampling is made into a continuous operation for faster sampling.
  • the imager can carry an extra bit of memory where the reference for the next frame can be stored. This can have additional advantages when used with a photodiode-based pixel array to perform correlated double sampling (CDS) or correlated quadruple sampling as described below.
  • CDS correlated double sampling
  • quadruple sampling as described below.
  • the first timing diagram corresponds to full-frame TDS mode and/or an op-comm TDS mode.
  • the second timing diagram corresponds to an op-comm CDS mode.
  • the third timing diagram corresponds to a star- tracker CDS/TDS mode.
  • the first line shows the integrate pointer location and frame [m+k,i]
  • the second line shows the read pointer location and frame [k,j]
  • the third line is the readout phase for a given row and frame [n,l].
  • FIG. 5 illustrates additional timing information 500 for multiple operation modes.
  • the timing information 500 includes operations to sample data needed for correlated quadruple sampling.
  • the imager may still be susceptible to flicker (1/f) noise, common mode noise, power supply rejection, and/or drift in the system. Because the two samples are temporally separate, any kind of drift (e.g., drift in the device, system, the clock, etc.) can affect the noise level.
  • CDS correlated quadruple sampling
  • CQS correlated quadruple sampling
  • the second timing diagram corresponds to a 2-pointer CDS mode (op-comm) .
  • the third timing diagram corresponds to a 1-pointer CDS mode (star-tracker) .
  • the first line shows the integrate pointer location and frame [m+k,i]
  • the second line shows the read pointer location and frame [k,j]
  • the third line is the readout phase for a given row and frame [n,l] .
  • star- tracker mode there is only one pointer.
  • the sample values for the integrate pointer phase can be stored in the memory array, and those during the read pointer phase can be stored in the single-line memory; in 4-pointer mode, all four sample values can be stored in the memory array.
  • FIG. 6 shows a CMOS multi-window imager 600 according to an implementation.
  • the imager 600 includes two separate memory arrays and memory decoders. This memory arrangement can provide architectural advantages when supporting multiple windowing frameworks. For example, the imager 600 can be configurable to run in a first mode, where up to eight 8X8 windows can be read out, and a second mode, where up to two 32x32 windows can be read out.
  • the imager 600 includes two separate diagonal switch arrays: switch networks A and B and address latches A and B.
  • the imager 600 includes additional components, such as described above, including a multi-window & memory controller, row logic, opamp signal chain, column starting address decoder, and readout decoder.
  • This layout provides an efficient use of hardware in this example implementation having two distinct multi-window modes.
  • FIG. 7 illustrates additional details 700 regarding the memory block and control logic shown in FIG. 6. These additional details 700 include a multi-window controller, memory controller, and various process flow arrows.
  • FIGS. 8 and 9 illustrate selected portions of a pixel array 810, switch network 820, memory array 830, and readout switch array 840 according to an implementation.
  • a single column of the pixel array 810 provides output for a selected row to the switch network 820.
  • the switch network 820 selects a column to route into an appropriate location in the memory array 830.
  • the memory array 830 is a 65x16 memory array made up of capacitors .
  • FIGS. 8 and 9 illustrate a mode of operation in which reset values are stored, and as signal values come, a signal value is read out, and then the reset value of the capacitor that has just been emptied is quickly stored. As shown in the memory array 830, there are sixty-four reset values, but one signal value.
  • FIG. 8 illustrates sampling 800.
  • FIG. 900 illustrates readout 900.
  • FIG. 10 illustrates a diagonal switch network 1000.
  • the switch network 1000 allows window-based addressing, such that a single address can be used to specify multiple pixels from a window to be sampled. For example, when reading an 8x8 block of pixels, eight contiguous pixels are stored in the memory (e.g., routed into the bus) by asserting a single address that makes eight diagonal connections together. Thus, multiple pixels are sampled in one shot.
  • FIG. 11 illustrates pixel sample and readout in an example op-comm mode of operation.
  • the signal values are stored on the bottom capacitors 1120, labeled memory A (1x16) and memory B (1x16) .
  • the reset values are stored on the top capacitors 1110, labeled memory A (64x16) and memory B (64x16).
  • FIG. 12 illustrates an example CMOS imager memory architecture 1200 for improved capacitor matching.
  • Corresponding signal and reset values for the pixels are stored on adjacent capacitors. This can be done using the switch network (s) such as described above to route the values such that a signal value and its corresponding reset value are always stored in adjacent capacitors.
  • the signal values can be stored on odd sets of capacitors, and the reset values can be stored on even sets of capacitors, such that the values that are ultimately correlated (e.g., signal minus reset) are stored on adjacent sets of capacitors.
  • This can result in very nice matching properties. For example, all the adjacent capacitors can be very well matched through a common centroid layout, in which gradient errors are averaged out. This layout technique reduces susceptibility to process errors, and can reduce fixed pattern noise.
  • FIG. 13 illustrates another operational mode applied to the hardware shown in FIGS. 8 and 9.
  • both signal and reset values are sampled for all the pixels in the region (s) of interest, and these sampled values are used to reduce fixed pattern noise.
  • the sampled signal and reset values can be stored in the memory array on adjacent capacitors, such as described above.
  • readout 1300 uses the same capacitors in the memory array as in FIGS. 8 and 9, but now the capacitors store multiple signal values and multiple corresponding reset values in adjacent capacitors to reduce fixed pattern noise.
  • FIG. 14 illustrates an example four sample mode of operation 1400.
  • Four-point CDS can help address flicker noise, common mode noise, power supply rejection, and/or drift issues in a particular system, and an imager with both two- point CDS and four-point CDS modes provides versatility.
  • the example four sample mode illustrated in FIG. 14 has been improved by effectively reducing the number of subtractions performed.
  • the sampled levels can be arranged such that only one subtraction is performed, as in the result being (A+D) - (B+C) .
  • the additions can be performed by dumping two capacitors simultaneously.
  • the signal and reset values are placed in the memory array according to a pattern that eliminates the need for extra subtractions during CQS.
  • Table 2 shows the various signals and their color and corresponding pattern in FIG. 14.
  • Each column has two buses that are connected to the differential signal chain.
  • Vsig(i) + Vhts-sig(i) ⁇ ⁇ V ts-rst(i) V rs t(i) ⁇ V s i g (i) .
  • FIG. 15 is a block diagram illustrating an example imager application.
  • a pointing and tracking system 1500 communicates with an active pixel sensor system 1550, such as described above.
  • the active pixel sensor system 1550 can be integrated onto a single CMOS chip and provide an interface that allows multiple arbitrarily placed windows to be specified using a single command from the pointing and tracking system 1500.
  • the pointing and tracking system 1500 can be part of a larger control system in a space-based application, such a satellite control system, or a terrestrial application, such as autonomous navigation and/or laser communications.
  • a space-based application such as a satellite control system, or a terrestrial application, such as autonomous navigation and/or laser communications.
  • the example system can be used to efficiently track multiple points of interest in a field of view for various pointing, tracking, navigation, and/or communication applications.
  • Other embodiments may be within the scope of the following claims.

Abstract

L'invention concerne des systèmes et des techniques permettant de réaliser des applications de pointage et de poursuite avec des dispositifs d'imagerie CMOS. En général, dans une implémentation, la technique consiste: à échantillonner des rangées multiples et des colonnes multiples d'une matrice de capteurs à pixels actifs (110) dans une matrice mémoire (par exemple une matrice mémoire sur puce) (130), et à afficher les rangées multiples ainsi que les colonnes multiples échantillonnées dans la matrice mémoire (130) pour produire des données d'images à faible artefact de mouvement. Divers modes de fonctionnement peuvent être prévus, notamment TDS, CDS, CQS, un mode de poursuite pour afficher des fenêtres multiples, et/ou un mode utilisant un type d'affichage échantillonné d'abord-affiché ensuite. Le mode de poursuite peut tirer avantage d'une matrice de commutateur en diagonale (120). La matrice de commutateur en diagonale (120), la matrice de capteurs à pixels actifs (110) et la matrice mémoire (130) peuvent être intégrées sur une seule puce d'imageur avec un contrôleur (140). Le dispositif imageur peut faire partie d'un système d'imagerie plus grand pour à la fois des applications basées dans l'espace et des applications terrestres.
PCT/US2002/040206 2000-12-14 2002-12-16 Imageur cmos pour applications de pointage et de poursuite WO2003053043A1 (fr)

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Cited By (5)

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Publication number Priority date Publication date Assignee Title
WO2006008553A1 (fr) * 2004-07-23 2006-01-26 Council For The Central Laboratory Of The Research Councils Dispositif d'imagerie
GB2426883A (en) * 2005-05-31 2006-12-06 Avago Technologies General Ip Imaging device using readout path selection
WO2007011092A1 (fr) * 2005-07-15 2007-01-25 Miru Enterprise, Inc. Capteur oculaire
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CN108064446B (zh) * 2017-10-20 2020-11-20 深圳市汇顶科技股份有限公司 模拟读取电路及影像传感模块

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