WO2003047095A2

WO2003047095A2 - Fast automatic gain control circuit

Info

Publication number: WO2003047095A2
Application number: PCT/IB2002/005034
Authority: WO
Inventors: Joachim Brilka; Thomas Hafemeister
Original assignee: Koninklijke Philips Electronics N.V.; Philips Corporate Intellectual Property Gmbh
Priority date: 2001-11-29
Filing date: 2002-11-25
Publication date: 2003-06-05
Also published as: DE10158417A1; WO2003047095A3; AU2002348868A8; AU2002348868A1

Abstract

An AGC detector is described, with an input for supplying an input(in) signal, particularly a CVBS signal, an output(out) for supplying a control signal (Vage) and a device for generating the control signal(Vage), which changes the control signal(CVBS) in one direction when the input signal(CVBS) complies with a predetermined property, and changes the control signal in the other direction with a first time constant when the input signal does not comply with the predetermined property. The particular aspect of the invention is that the generating device changes the control voltage(Vage) in the other direction after the end of a predetermined delay interval with a second time constant which is smaller than the first time constant, when the input signal(CVBS) does not comply with the predetermined property during a period which is longer than the predetermined delay interval.

Description

Fast AGC detector

The invention relates to an AGC (Automatic Gain Control) detector having an input for supplying an input signal, particularly a CVBS (Composite Video Blanking Signal) signal, an output for supplying a control signal and a device for generating the control signal, which changes the control signal in one direction when the input signal complies with a predetermined property, and changes the control signal in the other direction with a first time constant when the input signal does not comply with the predetermined property.

A control signal is generally used as a control voltage which is lowered when the input signal complies with the predetermined property and raised when the input signal does not comply with the predetermined property. Such an AGC detector is part of an amplitude control of an IF picture signal in a television receiver which is particularly used for mobile reception, also in vehicles. With the aid of the control voltage supplied by the AGC detector, an AGC amplifier is controlled in such a way that the amplitude of the IF picture signal is controlled at a given nominal value. With negatively modulated reception signals with a demodulated CVBS signal position having a low level for the synchronizing pulse dip and a high level for the "zero carrier", the "predetermined property" is satisfied when the synchronous pulse dip of the EF picture signal at the input of the AGC detector reaches a bottom reference value or falls below this value.

However, the ^"known AGC detectors have the drawback that they react relatively slowly to a relatively high level loss. To eliminate this drawback, it would be feasible to reduce the time constant, but then the signal amplitude would periodically vary too strongly (line tilt) which, in turn, would have a detrimental effect on the steady state.

It is therefore an object of the present invention to improve an AGC detector of the type described in the opening paragraph in such a way that a fast rise of the amplification upon loss of level can be realized in the steady state without any detrimental effects.

In an AGC detector of the type described in the opening paragraph, this object is solved in that the generating device changes the control voltage in the other direction after the end of a predetermined delay interval with a second time constant which is smaller than the first time constant, when the input signal does not comply with the predetermined property during a period which is longer than the predetermined delay interval.

When using the AGC detector according to the invention, a control in the steady state essentially only takes place under the influence of the relatively high first time constant so that unwanted stronger fluctuations of the control signal are avoided in such a state. However, when the input signal does not comply with the predetermined property for a longer period of time, which means, for example, that there is a higher loss of level, the influence of the smaller third time constant becomes manifest so that the control achieves a higher control speed in such a situation. Accordingly, it is possible to react to comparatively large control fluctuations in a faster way by means of the invention, without this having any detrimental effects on the steady state. The invention is based on the recognition that, in the steady state, a more frequent change takes place between the state in which the input signal complies with the predetermined property and the state in which the input signal does not comply with the predetermined property. In spite of a high control speed in the case of large fluctuations of the input signal, the signal distortion (line tilt) can be maintained relatively small by means of the invention. Furthermore, the invention requires only a few more components because only signals that are available are used. In an implementation in integrated circuits, the number of internal components is only relatively small, while a complete integration can be obtained because an additional periphery is not necessary.

Generally, the AGC detector comprises a first capacitor to which the output for supplying a control voltage as a control signal is connected, a first charge device which charges the first capacitor when the input signal complies with the predetermined property, and a discharge device whicrr discharges the first capacitor with a first discharge time constant when the input signal does not comply with the predetermined property. In this device which is currently particularly preferred, the discharge device discharges the first capacitor with a second discharge time constant which is smaller than the first discharge time constant after the end of a predetermined delay interval, when the input signal does not comply with the predetermined property during a period which is longer than the predetermined delay interval. The control voltage rises by charging the first capacitor by means of the charge device, whereas the control voltage falls again by discharging the first capacitor by means of the discharge device. Under the influence of the second discharge time constant, the discharge is accelerated after the predetermined delay interval has elapsed, because the second discharge time constant is smaller than the first discharge time constant. The discharge device may comprise a first discharge means and a second discharge means, which is activated after the end of the predetermined delay interval, the discharge time constant of the second discharge means being smaller than the discharge time constant of the first discharge means. The first and second discharge means preferably comprise first and second current sources which are arranged or arrangeable parallel to the first capacitor and are provided for discharging the first capacitor. The first and second current sources generate a current which flows as a discharge current through the first capacitor and thus discharges this capacitor. Upon activation of the second current source in addition to the first current source, a resultant discharge current then flows through the first capacitor, which discharge current is constituted by the sum of the currents generated by the first and second current sources. When the first current source is deactivated upon activation of the second current source, the second current source must generate a larger discharge current than the first current source. In this way, the discharge of the first capacitor is accelerated by the activation of the second current source.

The first discharge means may be arranged in such a way that it permanently discharges the first capacitor, in which the charge time constant of the charge device is significantly smaller than the discharge time constant of the first discharge means. It is true that, in this embodiment, the charge device counteracts the discharge device, so that the resultant charge time constant is slightly decreased, but this embodiment provides circuit- technical advantages because a separate activation of the first discharge means is not necessary. Accordingly, in a further improvement of this embodiment, the first current source may be arranged permanently parallel to the first capacitor.

The dischargeMevice preferably comprises a timing element which is activated or reset when the input signal does not comply with the predetermined property and activates the second discharge means after the end of the predetermined delay interval. As long as the input signal complies with the predetermined property, the timing element and thus also the second discharge means remains deactivated; this also applies to the case where the input signal complies with the predetermined property only for a period of time which is shorter than the predetermined delay interval and, even before it reaches the predetermined delay interval, assumes a state in which it complies with the predetermined property.

To this end, the second current source bridges the first capacitor via a first switch controlled by the timing element. In accordance with this embodiment, a series arrangement of the second current source and the first switch is arranged parallel to the first capacitor. By closing the first switch, the second current source starts generating current which is a discharge current and thus discharges the first capacitor more rapidly.

In a preferred embodiment, the timing element comprises a second capacitor, a second charge device for charging the second capacitor, a second switch bridging the second capacitor for activating or resetting the timing element, and a comparator which compares the charge voltage at the second capacitor with a predetermined reference value and activates the second discharge means when this reference value is exceeded. The comparator can control the first switch in such a way that the first switch closes, and thus accelerates the discharge of the first capacitor, when the charge voltage at the second capacitor exceeds the predetermined reference value, and opens, and thus interrupts the accelerated discharge of the first capacitor, when the charge voltage at the second capacitor falls below the predetermined reference value. The second charge device may comprise a third current source which is arranged in series with the second capacitor and whose current charges the second capacitor.

Generally, the first charge device comprises a fourth current source which is arranged in series with the first capacitor and charges this capacitor with its current. This fourth current source is arranged in series with the first capacitor via a third switch.

Furthermore, an input comparator is provided, which compares the input signal with a reference value and activates the first charge device when the input signal falls below this reference value. Alternatively, the charge device may also be activated when this reference value is exceeded.

The input comparator controls the third switch in such a way that it closes and that the charge current from the fourth current source starts flowing in the first capacitor when the input signal reaches the reference value.

Upon activation of the first charge device, the input comparator simultaneously deactivates the timing element. To this end, the input comparator controls the second switch in such a way that the second switch closes and thereby resets the timing element when the input signal complies with the predetermined property or falls below it, and opens and thus reactivates the timing element when the input signal does not (any longer) comply with the predetermined property or exceeds it. These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiments described hereinafter.

In the drawing: Fig. 1 shows the circuit diagram of a preferred embodiment of the AGC detector according to the invention.

Fig. 1 shows the circuit diagram of an AGC detector for IF picture signals with a negative modulation, conventionally comprising a comparator Compl, a first reference voltage source Vrefl, a first switch SW1, a first capacitor CI and first and second current sources II and 12 as implemented in, for example, the integrated circuit TDA9818.

Since the second current source 12 permanently bridges the first capacitor CI, it is constantly discharged with the current i2 generated by the second current source 12. The negative input "-" of the comparator Compl constitutes the input IN of the circuit shown, at which input a CVBS signal is present. The positive input "+" of the first comparator Compl is maintained at a reference voltage value which is generated by the first reference voltage source Vrefl . This reference voltage value constitutes a lower threshold value. As soon as the synchronizing pulse dip of the CVBS signal reaches or falls below this reference voltage value, the first comparator Compl generates a control signal at its output, which control signal controls the first switch SW1 in such a way that it closes. Closing of the first switch SW1 now has the result that the first current il generated by the first current source II starts flowing in the first capacitor CI and therefore serves as a charge current. Since the charge current il is larger than the discharge current i2 generated by the second current source 12, a charge of the first capacitor CI is the result.

In this way, the first capacitor CI, controlled by the first comparator Compl and the first switch SW1, is charged in a pulsed manner. When the level of the synchronizing pulse dip of the CVBS signal¹ corresponds to the reference voltage value generated by the first reference voltage source Vrefl, a charge balance at the first capacitor CI is formed by an AGC control loop (not shown).

The voltage thus formed at the first capacitor CI is supplied as a control voltage Vagc at the output OUT of the circuit and is used for gain control of the IF picture signal. This applies to a characteristic of the IF amplifier in which a smaller control voltage Vagc leads to a larger IF amplification, and conversely.

Since the first capacitor CI is permanently discharged with the discharge current i2 generated by the second current source 12, a voltage ripple in the control voltage Vagc is obtained, which leads to a video signal distortion in the form of line tilt via the control loop. To keep it small, the discharge time constant must be chosen to be relatively large, which leads to a relatively slow up-control of the IF amplifier (not shown) in the case of loss of level. This is particularly unacceptable for mobile reception. A decrease of the discharge time constant is only possible within given limits because otherwise the line tilt increases. To this end, the circuit shown in Fig. 1 further comprises third and fourth current sources 13 and 14, second and third switches SW2 and SW3, a second capacitor C2, a second reference voltage source Vref2 and a second comparator Comp2.

The second capacitor C2 is arranged in series with the fourth current source 14 and is thus permanently charged by its current i4. The charge voltage thus produced in the second capacitor C2 is present at the positive input "+" of the second comparator Comp2, while the reference voltage value generated by the second reference voltage source Vref2 is present at the negative input "-" of the second comparator Comp2. This reference voltage value serves as an upper threshold value. When it is exceeded by the voltage at the second capacitor C2, the second comparator Comp2 generates a control signal at its output which controls the second switch SW2 in such a way that it closes.

The third switch SW3 bridges the second capacitor C2 so that closing of this switch SW3 leads to an abrupt discharge of the second capacitor C2. By discharging the second capacitor C2, the voltage at the positive input "+" of the second comparator Comp2 falls significantly below the reference voltage value present at the negative input "-" and generated by the second reference voltage source Vref2. As a result, the second comparator Comp2 opens the second switch SW2 again.

The third current source 13 is arranged parallel to the first capacitor CI via the second switch SW2. The series arrangement of the second switch SW2 and the third current source 13 thus bridges the first capacitor CI. The first capacitor Compl controls the third switch SW3 in the same way as the first switch SW1. When the synchronizing pulse dip of the CVBS signal reaches or falls below the reference voltage value generated by the first reference voltage source Vrefl, the first comparator Compl generates a control signal at its output, which control signal not only closes the above-described first switch SW1 but also the third switch SW3 so that the second capacitor C2 is discharged and the second switch SW2 is opened. However, when the synchronizing pulse dip of the CVBS signal again exceeds the reference voltage value generated by the first reference voltage source Vrefl, which is then caused by a reduction of the amplification in the closed control loop, the first comparator Compl not only opens the first switch SW1 but also the third switch SW3. The latter results in a renewed charge of the second capacitor C2 by the fourth voltage source 14. During this process, the first capacitor CI is discharged exclusively by the second current source 12, because the second switch SW2 is still open at this instant.

When, after a given charge period after closing of the switch SW3, the second capacitor C2 is charged by the fourth current source 14 to such an extent that the voltage in the second capacitor C2 reaches and exceeds the reference voltage value generated by the second reference voltage source Vref2, the second comparator Comp2 closes the second switch SW2. In the embodiment described, a further discharge current i3 generated by the third current source 13 consequently starts to flow additionally to the discharge current i2 of the second current source 12 through the first capacitor CI so that the resultant discharge current in the first capacitor CI is increased and thus accelerates the discharge of the first capacitor CI.

In the steady state of the AGC control, this is effected in each picture line, i.e. for example every 64 μs. The time constant formed by the second capacitor C2 and the fourth current source 14 should be dimensioned in such a way that the voltage at the second capacitor C2 reaches the reference voltage value generated by the second reference voltage source Vref2 only after an interval of about 150 μs, thus when, in the embodiment shown, at least two consecutive synchronizing pulses of the CVBS signal do not reach the reference voltage value generated by the first reference voltage source Vrefl, but remain above this reference voltage value. Such a situation occurs when there is loss of level.

As already mentioned hereinbefore, when this case occurs, the third current source 13 is activated additionally to the second current source 12 by the second comparator Comp2 upon closing of the second switch SW2 for the purpose of discharging the first capacitor CI, which leads to n accelerated discharge of the first capacitor CI and thus to a faster up-control of the IF amplifier (not shown).

When the first comparator Compl responds again due to the achieved fast decrease of the level of the synchronizing pulse dip of the CVBS signal, the second capacitor C2 is discharged immediately again by closing the third switch SW3 and the second switch SW2 is thus opened again so that then only the discharge of the first capacitor CI takes place via the second current source 12 and, consequently, only the larger discharge time constant is active.

The fourth current source 14, the second capacitor C2, the second reference voltage source Vref2 and the second comparator Comp2 thus constitute a timing element which is reset by closing of the third switch SW3 and is activated again by opening this switch, and activates the third current source 13 additionally to the second current source 12 for an accelerated discharge of the first capacitor CI after a given delay interval by closing the second switch SW2.

Since the circuit shown in Fig. 1 is normally fully integrated, there is usually no access to the components and signals shown. For a further influence on the AGC control for the purpose of optimizing the automatic gain control, particularly in the case of mobile reception, it may, however, be necessary to have access to the control voltage Vagc. To this end, a fourth switch SW4 is provided in the embodiment shown, which fourth switch has a very fast switching behavior and with which a further external influence of the internal control voltage Vagc is possible via the terminal referred to as "Extern".

Claims

CLAIMS:

1. An AGC (Automatic Gain Control) detector having an input (IN) for supplying an input signal, particularly a CVBS (Composite Video Blanking Signal) signal, an output (OUT) for supplying a control signal (Vagc) and a device for generating the control signal (Vagc), which changes the control signal (Vagc) in one direction when the input signal (CVBS) complies with a predetermined property, and changes the control signal in the other direction with a first time constant when the input signal (CVBS) does not comply with the predetermined property, characterized in that the generating device changes the control voltage (Vagc) in the other direction after the end of a predetermined delay interval with a second time constant which is smaller than the first time constant, when the input signal (CVBS) does not comply with the predetermined property during a period which is longer than the predetermined delay interval.

2. A detector as claimed in claim 1 , comprising a first capacitor (CI) to which the output (OUT) for supplying a control voltage (Vagc) as a control signal is connected, a first charge device (II) which charges the first capacitor (CI) when the input signal (CVBS) complies with the predetermined property, and a discharge device (12, 13) which discharges the first capacitor (CI) with a first discharge time constant when the input signal (CVBS) does not comply with the predetermined property, characterized in that the discharge device (12, 13) discharges the first capacitor (CI) with a second discharge time constant which is smaller than the first discharge time constant after the end of a predetermined delay interval, when the input signal (CVBS) does not comply with the predetermined property during a period which is longer than the predetermined delay interval.

3. A detector as claimed in claim 2, characterized in that the discharge device comprises a first discharge means (12) and a second discharge means (13), which is activated after the end of the predetermined delay interval, the discharge time constant of the second discharge means (13) being smaller than the discharge time constant of the first discharge means (12).

4. A detector as claimed in claim 3, characterized in that the first and second discharge means comprise first and second current sources (12, 13) which are arranged or arrangeable parallel to the first capacitor (CI).

5. A detector as claimed in claim 2 or 3, characterized in that the first discharge means (12) permanently discharges the first capacitor (CI), and the charge time constant of the charge device (II) is smaller than the discharge time constant of the first discharge means (12).

6. A detector as claimed in claims 4 and 5, characterized in that the first current source (12) is arranged permanently parallel to the first capacitor (CI).

7. A detector as claimed in any one of claims 3 to 6, characterized in that the discharge device comprises a timing element (SW3, 14, C2, Vref2, Comp2) which is activated when the input signal (CVBS) does not comply with the predetermined property, and activates the second discharge means (13) after the end of the predetermined delay interval.

8. A detector as claimed in claims 4 and 7, characterized in that the second current source (13) bridges the first capacitor (CI) via a first switch (SW2) controlled by the timing element.

9. A detector as claimed in claim 7 or 8, characterized in that the timing element comprises a second capacitor^' (C2), a second charge device (14) for charging the second capacitor (C2), a second switch (SW3) bridging the second capacitor (C2) for activating or resetting the timing element, and a comparator (Comp2) which compares the charge voltage at the second capacitor (C2) with a predetermined reference value (Vref2) and activates the second discharge means (13) when this reference value is exceeded.

10. A detector as claimed in claims 8 and 9, characterized in that the comparator

(Comp2) controls the first switch (SW2) in such a way that the first switch (SW2) closes when the charge voltage at the second capacitor (C2) exceeds the predetermined reference value (Vref2), and opens when the charge voltage at the second capacitor (C2) falls below the predetermined reference value (Vref2).

11. A detector as claimed in claim 9 or 10, characterized in that the second charge device comprises a third current source (14) which is arranged in series with the second capacitor (C2).

12. A detector as claimed in any one of claims 1 to 11, characterized in that the first charge device comprises a fourth current source (II) which is arranged in series with the first capacitor (CI).

13. A detector as claimed in claims 4 and 12, characterized in that the fourth current source (II) generates a larger current (il) than the first current source (12).

14. A detector as claimed in claim 12 or 13, characterized in that the fourth current source (II) is arranged in series with the first capacitor (CI) via a third switch (SW1).

15. A detector as claimed in any one of claims 1 to 14, characterized by an input comparator (Compl) which compares the input signal (CVBS) with a reference value (Vrefl) and activates the first charge device (II) when said input signal falls below this reference value.

16. A detector as claimed in any one of claims 1 to 14, characterized by an input comparator (Compl) which compares the input signal (CVBS) with a reference value (Vrefl) and activates the first charge device (II) when this reference value is exceeded.

17. A detector as claimed in claim 14, and claim 15 or 16, characterized in that the input comparator (Compl) controls the third switch (SW31).

18. A detector as claimed in claim 7 and claim 15, 16 or 17, characterized in that, upon activation of the first charge device (II), the input comparator (Compl) simultaneously deactivates the timing element.

19. A detector as claimed in claims 9 and 18, characterized in that the input comparator (Compl) controls the second switch (SW23) in such a way that the second switch (SW23) closes when the input signal (CVBS) complies with the predetermined property, and opens when the input signal (CVBS) does not comply with the predetermined property.