WO2003046888A1

WO2003046888A1 - Decoding method for a delta modulated signal

Info

Publication number: WO2003046888A1
Application number: PCT/EP2001/013977
Authority: WO
Inventors: Stefan ZÜRBES
Original assignee: Telefonaktiebolaget Lm Ericsson (Publ)
Priority date: 2001-11-29
Filing date: 2001-11-29
Publication date: 2003-06-05
Also published as: AU2002219148A1

Abstract

The invention relates to a method of decoding a delta modulated signal which has been encoded using an adaptively varied encoding step size. The decoding method comprises receiving the delta modulated signal over an erroneous channel, determining a quality estimate for the received signal, assessing this quality estimate, and, upon decoding of the received signal, preventing or reducing an increase of the decoding step size in dependence of the assessment. The invention also relates to a receiver stage (30) for performing such a method. The receiver stage (30) comprises a decoder (32) and an assessment unit (34).

Description

Decoding Method for a Delta Modulated Signal

BACKGROUND OF THE INVENTION

Technical Field

The invention relates to a method of decoding delta modulated signals. In particular, the invention relates to decoding of delta modulated signals using an adaptively varied decoding step size.

Description of the Prior Art

Modern communications systems employ various techniques for converting analog signals to digital form. One of those analog-to-digital signal conversion techniques is a technique called delta modulation. During delta modulation the analog signal is first approximated with a series of samples. Each sample of the approximated signal is then compared to the original signal to determine the relative amplitude difference between the original signal and the approximated signal. A decision process for establishing the state of successive bits constituting the digital signal is based on this comparison. The state of an individual bit is determined by the sign of the actual difference between the original signal and the approximated signal.

Various types of delta modulation techniques are known in the art. For example there exist delta modulation techniques in which the step size between two subsequent samples of the approximated signal is constant. On the other hand there also exist delta modulation techniques in which the step size between two subsequent samples of the approximated signal is adaptively varied to make the approximated signal closely match the original analog signal. One of those delta modulation techniques using an adaptively varied step size is called Continuously Variable Slope Delta (CVSD) modulation.

CVSD modulation is a non-linear modulation scheme in which the direction of a slope error is determined and subjected to a rule. This means that the slope error is used as a criteria for determining whether or not the slope of the delta modulated signal is to be changed by progressively increasing or decreasing the step size. A changed slope is held at the new value until the rule indicates that the slope has to be changed again. It is thus possible to have a continuously adjusted slope which maximizes the closeness with which the delta modulated signal follows the original input signal while at the same time minimizing the amount of quantization noise in that signal. Quantization noise is an error signal given by the difference between the reconstructed analog signal and the original analog signal from which it was derived.

A signal encoded with a delta modulation technique which uses an adaptively varied step size can usually tolerate a certain amount of bit errors introduced while transmitting the signal over an erroneous channel without significant quality reduction at a receiving side. In principle, such bit errors merely lead to an increase of the noise floor, which is already present due to the quantization noise mentioned above and other noise sources.

Nevertheless it is often desirable to reduce the bit error probability. One way of combating bit errors introduced by an erroneous channel is bit error protection.

Various techniques for implementing bit error protection are known in the art.

Forward error correction for example is an error protection technique in which error protection bits are added to the data bits at the transmitter side, such as parity bits or Cyclic Redundancy Check (CRC) bits. The data bits and the error protection bits together fulfill a certain mathematical rule that is known on both the transmitter side and the receiver side. If the received data and error protection bits do not fulfill this rule, the receiver side knows that an error must have occurred.

By adding more error protection bits to the data bits the probability of detecting and eventually correcting errors increases. In practice, however, the number of error protection bits which can be added to the data bits is limited due to various considerations. For example many transmission standards intentionally do not use strong forward error correc- tion or other error protection techniques like interleaving due to the complexity, transmission delay, and spectrum efficiency impacts of these error protection techniques. Due to fading and interference phenomenona, a received signal may thus comprise a substantial amount of undetected bit errors or, after error protection decoding, residual bit errors contributing to a significant bit error rate.

This bit error rate is usually heavily time variant since interferences, which are a major source of bit errors, often occur in the shape of short error bursts producing random bit sequences in the received signal. While delta modulation techniques using an adaptively varied step size can tolerate a certain amount of random transmission bit errors, such bursty bit error patterns can not be handled adequately. In the case of speech transmissions, for example, the bursty bit error patterns lead to a crackling additive noise at the receiver audio output.

It is an object of the present invention to provide an im- proved method of decoding a delta modulated signal using an adaptively varied decoding step size. It is a further object of the present invention to provide a decoding method which is less vulnerable to interference signals like short error bursts.

It is another object of the present invention to provide a receiver stage implementing such a method and a communications system comprising this receiver stage.

SUMMARY OF THE INVENTION

According to the invention a method of decoding a delta modulated signal using an adaptively varied decoding step size is proposed, wherein the delta modulated signal is received over an erroneous channel, a quality estimate for the received signal is determined, the quality estimate is assessed, and, upon decoding of the received signal, an increase of the decoding step size is prevented or reduced in dependence of this assessment.

It is thus proposed to artificially reduce (compared to a scheduled increase) , prevent or disable an increase of the decoding step size at least momentarily as a precautionary measure in the case the quality estimate is not satisfactory. In the case of a high quality estimate, the step size varia- tion may be performed as indicted by the input bit sequence which is to be decoded. The prevention or disabling of a step size increase may include a step size decrease, and the reduction of a step size increase may lead to a smaller increase than indicated for example by an unreliable input bit sequence which is to be decoded.

Consequently, the probability or the effects of step size increases erroneously triggered by bit errors can be reduced, i.e., random amplifications can be avoided. This leads to a better quality of the decoded signal. The quality estimate may be determined from the received signal itself (e.g. from a bit content of the received signal) or be derived from e.g. channel measurements not directly related to the received signal or its content. Preferably the quality estimate is an instantaneous value relating to a specific portion of the received signal.

The received signal may be comprised of individual transmission units like packets or bursts. The individual transmis- sion units themselves may be comprised of subunits. For example in the case of packet based transmission each packet may comprise a header portion and a payload portion.

If during decoding of the received signal or a portion thereof an increase of the step size has to be artificially prevented or reduced as a result of the assessment of the quality estimate, the decoded signal or the decoded portion thereof may simply be discarded. According to a preferred embodiment, however, the decoded signal is processed further regardless of the assessment, i.e., regardless of the fact whether or not an increase of the step size has artificially been prevented or reduced during decoding of this signal. If for example the decoded signal is a payload portion of a packet relating to encoded speech, the decoded speech may be output regardless of the quality estimate determined for this signal.

The quality estimate determined for the received signal preferably relates to a parameter indicative of the instantaneous bit error rate. This parameter may be a one bit value which in the case of a presumably or actually high bit error rate indicates whether or not the bit content of the received signal is reliable. However, the quality estimate may also be a more complex parameter like the actual (measured) bit error rate or a value derived therefrom. The quality estimate may be determined by analyzing the bit content of the received signal. To that end, one or more specific portions like the header portion or the payload portion of a received packet may be analyzed. If for example analysis of the header reveals a header failure, an increase of the step size during decoding of the corresponding payload portion may be prevented.

When analyzing the bit content of a received signal to deter- mine a quality estimate therefor, redundancy comprised within the transmitted signal may be exploited. Such redundancy may for example be artificially introduced like in the case of forward error correction.

However, the redundancy may also result from a priori knowledge about the received signal. When encoding certain analog signals some bit sequences may be more likely to occur than other bit sequences, leading to a priori knowledge about the received signal. Receipt of one or more unlikely bit se- quences may be indicative of a high bit error rate and result in a low quality estimate.

Instead of or in addition to analyzing the bit content of the received signal, the quality estimate may also be determined by performing specific measurements. The measurements may relate to parameters indicative of the quality of the transmission channel, on the received signal strength, etc.

Furthermore, the quality estimate for the received signal may be determined by analyzing parameters generated during processing of the received signal. As an example, the distance or the accumulated distances between the received modulated signal and the reassembled modulated signal based on the receiver decisions may be exploited for determining the quality estimate. In dependence of the assessment of the quality estimate, an increase of the step size during decoding of the received signal is prevented or reduced. This means that decoding is performed either with the step size used during the last de- coding operation or with a smaller step size or with a step size that is increased less than scheduled, for example less than indicated by an unreliable input bit sequence for the decoder. Various possibilities for artificially preventing or reducing an increase of the step size exist. In general, the nature of the mechanism employed for artificially preventing or reducing an increase of the step size depends on the implemented step size variation scheme.

Several step size variation schemes are based on the occur- rence of a predefined bit pattern in the received signal.

This means that in the case that a predefined bit pattern is detected in the received bit stream, the step size is automatically increased. In such a step size variation scheme an increase of the step size may be prevented or reduced by changing a first bit pattern which is comprised within the received signal (and which may cause an erroneous or non- erroneous increase of the step size) into a second bit pattern which causes the step size to remain constant or to decrease, or which causes a smaller increase of the step size.

According to a first variant of the invention, changing the first bit pattern simply comprises replacing the first bit pattern with a predefined or dynamically selected second bit pattern which is for example chosen such that it does not trigger an increase of the step size. According to a second variant of the invention, changing the first bit pattern comprises modifying the first bit pattern such that the modified first bit pattern does not lead to an increase of the step size, or leads to a smaller increase of the step size. Modi- fication of the first bit pattern may comprise changing individual bits of the first bit pattern appropriately. Instead of preventing or reducing an increase of the step size by changing the input signal of the decoder, a dedicated control signal may be used. This control signal is supplied to the decoder and controls the decoder such that an increase of the step size is disabled or reduced momentarily, during a specific period of time, for a specific signal or for a specific signal portion.

Several techniques for preventing or reducing an increase of the step size have been described so far. Preferably, a plurality of such techniques is defined and the technique which is actually implemented is chosen in dependence of the assessment of the quality estimate. For example the receiver stage may select among the following three techniques. If the assessment indicates a low quality estimate, i.e., a very poor channel, the technique using a replacement bit pattern may be implemented. On the other hand, if the assessment indicates that some errors are to be expected, but that some information is still contained in the input bit sequence, the techniques of modifying the input bit pattern or of using a dedicated decoder control signal may be considered. If the assessment shows that the estimated number of bit errors in the input bit sequence is marginal, a regular decoding may take place, including step size increases.

The assessment of the quality estimate can be performed in various ways. The quality estimate may simply be subjected to a threshold decision. According to a more sophisticated approach, the quality estimate is subjected to decision which is effected by means of a neuronal network or any other mapping from a multidimensional range of values to a binary or finite number of decision states. Using such techniques has the advantage that besides the quality estimate one or more additional parameters can be taken into account.

The above method can be implemented both as a hardware solution and as a computer program product comprising program code portions for performing the method when the computer program product is run on a computer system. The computer program product may be stored on a computer readable recording medium like a data carrier attached to or removable from the computer system.

The hardware solution mentioned above may be constituted by a receiver stage for receiving over an erroneous channel a signal which has been delta modulated using an adaptively varied encoding step size, the receiver stage comprising a decoder for decoding the received signal using an adaptively varied decoding step size and an assessment unit for determining and assessing a quality estimate for the received signal. The receiver stage is configured such that a step size increase is prevented or reduced in dependence of the assessment performed by means of the assessment unit.

The receiver stage may further comprise a signal processor arranged in a signal path before the decoder and in communi- cation with the assessment unit. When the assessment unit determines that an increase of the decoding step size has to be prevented or reduced, the signal processor changes a first bit pattern comprised within the received signal into a second bit pattern which causes the step size not to increase or increase less than scheduled.

Moreover, the receiver stage may comprise a control unit in communication with both the assessment unit and a dedicated control input of the decoder. When the assessment unit deter- mines that an increase of the step size has to be prevented or reduced, the control unit controls the decoder accordingly.

The receiver stage may be a component of a wireless or wire- line communications system. BRIEF DESCRIPTION OF THE DRAWINGS

Further advantages of the invention will become apparent upon reference to the following description of preferred embodi- ments of the invention in the light of the accompanying drawings, in which:

Fig. 1 shows a schematic view of a CVSD encoder for modulating a signal using an adaptively varied step size;

Fig. 2 is a more detailed view of the accumulator of the CVSD encoder depicted in Fig. 1;

Fig. 3 shows the basic transmission unit of the Bluetooth packet based transmission system;

Fig. 4 shows a receiver stage adapted to decode a delta modulated signal using an adaptively varied step size according to a first embodiment of the invention; and

Fig. 5 shows a receiver stage adapted to, decode a delta modulated signal using an adaptively varied step size according to a second embodiment of the invention.

DESCRIPTION OF PREFERRED EMBODIMENTS

Although the present invention can be practiced in combination with any method and any device suitable for decoding a delta modulated signal using an adaptively varied step size, the following description of preferred embodiments is exem- plarily set forth with respect to a packet based communica- tions system which employs CVSD modulation. In particular, possible implementations of the invention in accordance with the Bluetooth speech transmission scheme as defined in Speci- fication of the Bluetooth System, Specification Volume 1, Core, Version 1.1, 22 February 2001 are described hereinafter.

Bluetooth is a short-range radio link intended to replace the cables connecting portable and/or non-portable electronic devices. Bluetooth operates in the unlicensed ISM band at 2,4 GHz and applies a frequency hop transceiver to combat interference and fading. A slotted channel is provided with a nominal slot length of 625 μsec. For full duplex transmission, a Time-Division Duplex (TDD) scheme is used. On the transmission channel, information is exchanged through packets. Each packet is transmitted on a different hop frequency. A packet nominally covers a single slot, but can be extended to cover up to five slots.

On the Bluetooth audio air interface two different voice coding schemes are supported. One of these voice coding schemes is CVSD. As has been mentioned above, this modulation scheme produces output bits b(k) which indicate whether a prediction value ύ(k) is smaller or larger than an input signal u(k). To reduce slope overload effects, the step size δ(k) is adapted according to the average signal slope ("syllabic companding") .

In Fig. 1 a CVSD encoder 10 in accordance with chapter 12.2 of the Bluetooth baseband specification is depicted. The CVSD encoder 10 comprises an accumulator 12 and a step size control unit 14. The construction of the accumulator 12 is de- picted in more detail in Fig. 2. As can be seen from Fig. 2, the accumulator 12 comprises a delay circuit 16 and a processing unit 18.

Let w(k) be the accumulator contents, h be the decay factor of the accumulator 12, β be the decay factor for the step size δ(k), α be the syllabic companding parameter monitoring the slope by considering the K most recent output bits b(k), and let

ϋ(k) = h w(k)

(1)

Supposing that = 1 if J bits in the last K output bits b(k) are equal, and α = 0 otherwise, the CVSD encoder's 10 internal state is updated according to the following set of equations

b(k) = sgn{u(k)-ύ(k-l) }

(2)

(3)

(4:

where

w(k) ϋ(k-l) + b(k)δ(k)

(5)

In these equations, δ_mιn and δ_max are the minimum and maximum step sizes, and γ_mιn and y_max are the accumulator's 12 negative and positive saturation values, respectively. Over air, the output bits b(k) are sent in the same order as they are generated by the CVSD encoder 10.

The individual parameters mentioned above are defined in the Bluetooth specification. The parameters result in a time constant of 0,5 s for the accumulator decay, and a time con- stant of 16 ms for the step size decay. The parameters J and K are chosen to equal 4. This means that the step size δ(k) used by the CVSD encoder 10 will increase if the last four output bits b(k) of the CVSD encoder 10 are equal. On the other hand, the step size δ(k) is decreased if the last four output bits b(k) are not equal.

When the output signal of the CVSD encoder 10 is transmitted over the erroneous air interface, bit errors are introduced. In order to cope with bit errors, the Bluetooth specification defines several error protection mechanisms like HEC (Header Error Check), FEC and CRC. These error protection mechanisms are now discussed in more detail with reference to Fig. 3.

In Fig. 3 the structure of a typical Bluetooth packet is depicted. Each Bluetooth packet comprises an access code portion, a header portion and a payload portion. Whereas the access code portion and the header portion are of fixed size, the size of the payload portion may vary. The header consists of six fields and comprises, including the 8-bit HEC, 18 bits. The header is encoded with a rate 1/3 FEC resulting in a 54-bit header. For certain types of packets a CRC code is generated for the payload. Furthermore, the payload may be FEC encoded also.

A received Bluetooth packet can thus be checked for bit errors using the HEC in the header portion or the access code portion, the CRC (if present) in the payload portion or the FEC. According to sections 4.3.6 and 5.4 of the Bluetooth specification, a received packet is entirely discarded if the HEC or the CRC does not check.

While the error protection schemes defined in the Bluetooth specification are able to satisfactorily cope with random transmission bit errors, it has been found that the above error protections scheme is rather vulnerable to short error bursts. Such short error bursts may result for example from asynchronous intermittent interference.

Due to such short error bursts the probability of erroneously receiving sequences of four of more subsequent bits which are equal can get rather high. For example only one or two bit errors within five subsequent bits are necessary to change a five bit sequence without four equal bits in a row to a five sequence bit that contains four or five subsequent equal bits. This means that the step size at the receiver side may erroneously increase significantly, and even faster than the exponential decay which reduces the step size again, unless a suitable mechanism for preventing step size increases under certain circumstances is provided.

In Figs. 4 and 5 two embodiments of receiver stages 30 according to the invention for receiving over an erroneous channel a delta modulated signal are depicted. The receiver stages 30 may be used for decoding a received signal encoded with the CVSD encoder 10 as depicted above or with any other encoder which uses an adaptively varied encoding step size.

The receiver stages 30 depicted in Figs. 4 and 5, respectively, each comprise a decoder 32 for decoding the received signal using an adaptively varied decoding step size and an assessment unit 34 for determining and assessing a quality estimate for the received signal. Each of the decoders 32 comprises an accumulator 36 and a step size control unit 38. When the receiver stages 30 of Figs. 4 and 5 are to process a received signal which has been encoded with the CVSD encoder 10 of Fig. 1, the accumulators 36 may have the same structure and function as the accumulator 12 depicted in Fig. 2. Also, the step size control units 38 may correspond in structure and function to the step size control unit 14 of Fig. 1. How- ever, variations of the accumulators 36 and the step size control units 38 depicted in Figs. 4 and 5 can become necessary if encoding schemes different from CVSD are used. In the following, the structure and the function of the receiver stage 30 depicted in Fig. 4 will be described in more detail. As can be seen from Fig. 4, the receiver stage 30 further comprises a signal processor 35 which is arranged in a signal path before the decoder 32 and in communication with the assessment unit 34.

A received signal in the form of a Bluetooth packet compris- ing a sequence of bits b(k) received by the receiver stage 30 is fed concurrently to the signal processor 35 and the assessment unit 34. The assessment unit 34 then determines and assesses a quality estimate for the received signal as will be described in more detail below. If due to e.g. a high bit error rate the received signal is judged as unreliable, the assessment unit 34 controls the signal processor 35 such that an increase of the decoding step size is prevented.

It should be noted that according to a possible implementa- tion of the assessment unit 34 such an increase of the step size is prevented independently from the fact whether or not the received signal b(k) is actually erroneous, since the assessment unit 34 may base its judgment solely on the quality estimate. However, as mentioned above, additional parameters may additionally be taken into account.

The signal processor 35 processes the received signal b(k) in accordance with a control signal from the assessment unit 34 and produces an output signal b' (k) which is input to the de- coder 32. The output signal b' (k) from the signal processor 35 is fed to both the accumulator 36 and the step size control unit 38 of the decoder 32. The step size control unit 38 outputs an appropriate step size δ(k) in dependence on its evaluation of the output signal b' (k) from the signal proces- sor 35. Both the output signal b' (k) from the signal processor 35 and the step size δ(k) determined by the step size control unit 38 are input into the accumulator 36 which cal- culates an estimate ϋ(k-l) for the original analog input signal of the encoder as depicted in Fig. 2.

In the following, two exemplary signal control routines im- plemented by the signal processor 35 in response to a control signal from the assessment unit 34 will be described. Both control routines are based on changing a first bit pattern which is comprised within the received signal b(k), and which may or may not cause an increase of the step size, to a sec- ond bit pattern which definitely causes the step size not to increase .

According to the first control routine, the signal processor 35 simply replaces the first bit pattern with a second bit pattern. In the CVSD scheme defined in the Bluetooth specification, the step size is increased by the step size control unit 38 if the last four bits b(k) are equal. Therefore, the second bit pattern which substitutes the first bit pattern may be a predefined bit pattern with less than four equal bits in a row. For example, the second bit pattern may be an alternating bit pattern in the form of 101010... or 1100110011.... This second bit pattern replaces the first bit pattern in the output signal b' (k) of the signal processor 35. In the packet based transmission scheme defined in the Bluetooth specification, the second bit pattern may replace a whole payload portion or at least those parts of a payload portion which comprise four or more identical bits in a row.

Now, a second control routine implemented by the signal proc- essor 35 in accordance with a control signal from the assessment unit 34 will be described. The second control routine consists in modifying individual bits comprised within the first bit pattern such that the modified bit pattern does not trigger a step size increase within the step size control unit 38. In the case of the CVSD scheme defined in the Bluetooth specification this means that a first bit pattern with four or more identical bits in a row is modified to a second bit pattern with less than four identical bits in a row. The bit sequence b' (k) thus modified is provided to the decoder 32 and guarantees that the step size does not increase while unreliable packet contents are processed. For example an un- reliable input bit sequence b(k) (0,1,0,1,1,1,1,1,0,1,0,0) can be modified by the signal processor 35 into a modified output bit sequence b'(k) (0, 1, 0, 1, 1, , 1, 1, 0, 1, 0, 0) in order to avoid more than three ones in a row.

Whereas the first control routine described above replaces all "trigger" bit sequences with "dummy" bit sequences, the second control routine only changes individual bits. The second control routine thus has the advantage that the output of the decoder 32 is changed only slightly compared to the out- put of the decoder 32 when the first control routine is implemented. Consequently, almost no information is lost when the second control routine is implemented.

In the following description of the receiver stage 30 accord- ing to the second embodiment depicted in Fig. 5, a further control routine for preventing an increase of the step size is described which does not change the information output by the decoder 32 at all.

In the second embodiment depicted in Fig. 5, a control unit

40 is provided which communicates with the assessment unit 34 on the one hand and a control input 42 of the step size control unit 38 on the other hand. Compared to the first embodiment depicted in Fig. 4, the decoder 32 thus has to be modi- fied by providing a dedicated control input 42 of the step size control unit 38. However, the second embodiment shown in Fig. 5 has the advantage that the input signal b(k) need not be changed by additional signal processing means since an increase of the step size is disabled by an appropriate control signal supplied from the control unit 40 to the step size control unit 38. This control signal is generated by the control unit 40 in response to a corresponding request from the assessment unit 34 in the case the assessment unit 34 decides that the received signal b(k) is not reliable.

The control routine for disabling a step size increase util- ized in the second embodiment depicted in Fig. 5 as well as the second control routine described above with reference to Fig. 4 have the advantageous property that they do not change the output of the decoder 32 (compared to the case where no control routine is implemented at all) unless a critical in- crease of the decoder step size would occur. It is therefore expected that false alarms, i.e., assuming that a received signal contains unreliable data but in reality it does not, can be tolerated to a reasonable degree if these control routines are employed. The reason for this is the fact that those two control routines still provide more or less' the correct wave form apart from a possibly too small amplification.

The above described mechanisms to prevent erroneous step size increases (in the case of significantly many bit errors, but still some information expected in the input bit stream) can be added with a decision scheme that uses a replacement bit sequence (as described above) for the case that the expected remaining information in the input bit stream is too low.

In this context it should be noted that all three control routines described above enable a further processing of the received signal even if the received signal is judged as unreliable. This means that even if a received packet is judged as unreliable, the payload of the packet is not discarded but processed further.

So far three control routines for preventing an increase of the step size have been described with reference to the em- bodi ents depicted in Figs. 4 and 5, respectively. All these control routines are initiated in dependence of an assessment of a quality estimate by the assessment unit 34. In the fol- lowing, various techniques for determining such a quality estimate for the received signal will be described in more detail.

These techniques are preferably performed by the assessment unit 34. However, external means for determining the quality estimate like measurement units may be provided as well. These means have to communicate with the assessment unit 34. Consequently, the assessment unit 34 may receive further in- put 44 from those means for determining the quality estimate, This input 44 can be received by the assessment unit 34 instead of or in addition to the received signal b(k). Furthermore, the assessment unit 34 may receive input only in the form of the received signal b(k).

All techniques for determining a quality estimate described hereinafter determine an instantaneous quality estimate. This instantaneous quality estimate relates to a parameter indicative of an instantaneous bit error rate.

According to a first technique of determining a quality estimate for a received signal having the form of a packet comprising a signal portion and a header portion (including an access code) , the bit content of the header portion is ana- lyzed with respect to header failures. As has been described above, the HEC depicted in Fig. 3 or the amount of bit errors detected in the access code can be used for this purpose. In other words, the payload portion of a packet with header failure is considered as unreliable and a step size increase is prevented when this unreliable payload portion is decoded by the decoder 32. The quality estimate, i.e., the parameter indicative of an instantaneous bit error rate, will in this case be a one bit value which is set to 1 in the case of a header failure (which indicates a presumably high bit error rate), and to 0 otherwise. The assessment unit 34 assesses this one bit value, which is created for each packet (or pay- load portion) to be decoded, and prevents an increase of the decoding step size during decoding of a packet (or payload portion) if the respective one bit value has been set to 1.

As a second technique of determining a quality estimate for the received signal, redundancy which has been introduced artificially on the transmitting side is exploited. This artificial redundancy may result for example from FEC (including CRC) . As has been discussed in context with Fig. 3, the Bluetooth specification defines an FEC scheme for example for the header portion, and optionally also for the payload portion. A quality estimate for the received signal indicative of an instantaneous bit error rate can be derived from specific metrics which result form FEC decoding. For example the quality estimate may be derived from the number of corrections on a bit level which result from FEC decoding. The number of corrections, which is indicative of the instantaneous bit error rate, thus determined is then assessed by the assessment unit 34 by means of a threshold decision. If the number of corrections lies above a predefined or a dynamically set threshold, a high bit error rate is assumed and an increase of the step size is prevented.

A possible implementation of the second technique is to prevent an increase of the decoding step size for the payload portion of such a packet which has a header portion that involved a high number of corrections during FEC decoding. This means that the resolution of preventing an increase of the step size corresponds to one payload portion.

In general, a higher resolution of preventing an increase of the step size can be provided if the quality estimate can be derived with a higher resolution. As an example, the Bluetooth specification defines a link with HV2 packets having a payload portion which is FEC protected with short 2/3 rate block codes with 10 information bits per code word and minimum Hamming distance of 4. In this case a reliability indication can be derived for every 10 information bits by checking whether the corresponding received code word contained detectable errors. Consequently, an increase of the step size can be prevented for individual parts (having a length of 10 bits) of the payload portion.

According to a third technique of determining a quality estimate for the received signal, a priori knowledge about the encoded signal is exploited. During speech encoding for example it can be observed that the output of a CVSD encoder com- prises significant redundancy. This redundancy manifests itself in the fact that certain bit sequences (for example eight bit words) are more likely than other bit sequences. Consequently, a quality estimate for the received signal can be derived on a bit level by analyzing the received eight bit words. In this case the quality estimate can be determined for example by monitoring a sequence of eight bit words and by counting the eight bit words comprised within the sequence which have a likelihood below a specific threshold. Consequently, a high bit error rate can be assumed if the quality estimate thus obtained exceeds a predefined value.

According to a fourth technique of determining a quality estimate for the received signal, one or more measurements are performed. The measurements relate for example to the re- ceived carrier-to-interference power ratio or to the received signal strength. Based on such measurements a quality estimate indicative of an instantaneous bit error rate may be provided. Since a low signal strength indicates a high bit error rate, the quality estimate may for example be derived from the period of time the received signal strength lies below a predefined value.

According to a fifth technique of determining the quality estimate, one or more parameters generated during processing of the received signal are analyzed. Such parameters may be derived from the decision reliability of the receiver stage. For example the distance or the accumulated distances between the received signal and a decision threshold for reassembling the analog input signal of the encoder can be used as a quality estimate indicative of the bit error rate.

Of course, any combinations of the above five techniques of determining a quality estimate for the received signal can be implemented in order to determine two or more quality estimates. If a plurality of quality estimates is available, the decision whether or not to prevent an increase of the step size may be performed by means of a neuronal network.

Although the above embodiments of the invention were described having the Bluetooth speech transmission scheme in mind, the invention is not limited to this application. In particular, the invention is neither restricted to speech transmission nor to packet based transmission nor to a specific wireless communications system. Furthermore, the invention may also be practiced in combination with delta modulation schemes different from CVSD as long as an adaptively varied decoding step size is employed. The Bluetooth specification proposes to discard the whole packet in the case of header failures or payload failures. However, the Bluetooth specification could be amended such that one of the three control routins mentioned above in context with preventing an increase of the step size are implemented when a header failure or a payload failure is detected.

While the invention has been described in conjunction with specific embodiments thereof, it is evident that many altera- tion, modifications, and variations will be apparent to those skilled in the art in the light of the foregoing description. Accordingly, the invention is intended to embrace all such alterations, modifications, and variations within the spirit and scope of the appended claims.

Claims

1. A method of decoding a delta modulated signal using an adaptively varied decoding step size, comprising: a) receiving the delta modulated signal over an erroneous channel; b) determining a quality estimate for the received signal; c) assessing the quality estimate determined in step (b) ; and d) upon decoding of the received signal, preventing or reducing an increase of the step size in dependence of the assessment in step (c) .

2. The method of claim 1, wherein the received signal is comprised of individual transmission units.

3. The method of claim 1 or 2 , wherein the decoded signal is processed further regardless of the assessment of step (c) .

4. The method of one of claims 1 to 3, wherein the quality estimate relates to a parameter indicative of an instantaneous bit error rate.

5. The method of one of claims 1 to 4, wherein step (b) comprises analyzing the bit content of the received signal.

6. The method of claim 5, wherein the bit content of a specific portion of the received signal is analyzed.

7. The method of claim 5 or 6, wherein a redundancy comprised within the received signal is analyzed.

8. The method of claim 7, wherein the redundancy results from at least one of an artificially introduced redundancy and a priori knowledge about the received signal .

9. The method of one of claims 1 to 8, wherein step (b) comprises performing measurements.

10. The method of one of claims 1 to 9, wherein step (b) comprises analyzing parameters generated during processing of the received signal.

11. The method of one of claims 1 to 10, wherein preventing or reducing an increase of the step size com- prises changing a first bit pattern which is comprised within the received signal into a second bit pattern which causes the step size to remain constant or to decrease .

12. The method of claim 11, wherein changing the first bit pattern comprises substituting the first bit pattern with the second bit pattern.

13. The method of claim 11, wherein changing the first bit pattern comprises modifying the first bit pattern.

14. The method of one of claims 1 to 10, wherein preventing or reducing an increase of the step size comprises generating a dedicated control signal and supply- ing the control signal to a decoder for the received signal to disable or reduce an increase of the step size.

15. The method of one of claims 1 to 14, wherein two or more techniques for preventing or reducing an increase of the step size are defined and wherein the technique to be implemented is chosen in dependence of the assessment of the quality estimate.

16. The method of one of claims 1 to 15, wherein the assessment of the quality estimate comprises a threshold decision or a decision which is effected by means of a mapping technique.

17. The method of one of claims 1 to 16, wherein pre- venting an increase of the steps size includes decreasing the step size.

18. A computer program product for performing the steps of claims 1 to 17 when the computer program product is run on a computer.

19. The computer program product of claim 18, stored on a computer-readable recording medium.

20. A receiver stage (30) for decoding a signal which has been delta modulated using an adaptively varied encoding step size, comprising: a) a decoder (32) for decoding the received signal us- ing an adaptively varied decoding step size; b) an assessment unit (34) for determining and assessing a quality estimate for the received signal, wherein an increase of the decoding step size is prevented or reduced in dependence of the assessment.

21. The receiver stage of claim 20, further comprising a signal processor (38) arranged in a signal path before the decoder (32) and in communication with the assessment unit (34), the signal processor (38) changing a first bit pattern which is comprised within the received signal into a second bit pattern which prevents or reduces a step size increase.

22. The receiver stage of claim 20, wherein the decoder (32) has a step size control input (42) and further comprising a control unit (40) in communication with the assessment unit (34) and the step size control input (42) .

23. A communications system comprising the receiver stage of one of claims 20 to 22.