WO2003038885A1

WO2003038885A1 - Method for making a semiconductor component

Info

Publication number: WO2003038885A1
Application number: PCT/EP2002/011691
Authority: WO
Inventors: Thomas Hecht; Harald Seidl
Original assignee: Infineon Technologies Ag
Priority date: 2001-10-31
Filing date: 2002-10-18
Publication date: 2003-05-08
Also published as: DE10153288A1

Abstract

The invention concerns a method for making a semiconductor component using a dielectric coating (701, , 70n) with several layers provided on or in a substrate (1). The invention is characterized in that after one of the layers (701, , 70n) has been prepared, it consists in carrying out a plasma treatment, for example, plasma oxidation, and/or heat treatment.

Description

description

Manufacturing method for a semiconductor device

The present invention relates to a manufacturing method for a semiconductor component with a. multilayer dielectric layer provided in a substrate.

The term substrate is to be understood in the general sense and can therefore include both single-layer and multi-layer substrates.

Although applicable to any semiconductor components, the present invention and the underlying problem with regard to capacitors in silicon technology are explained.

So-called one-transistor cells are used in dynamic read / write memories (DRAMs). These consist of a storage capacitor and a selection transistor that connects the storage electrode to the bit line. The storage capacitor can be designed as a trench capacitor or as a stacked capacitor. The invention described here relates u. a. on any capacitors for such DRAMs in the form of trench capacitors and stack capacitors.

It is known to use such a capacitor, e.g. B. to produce for a DRAM (dynamic read / write memory) with the structure of electrode layer-insulator-layer-electrode layer, the electrode layers being metal layers or (poly) silicon layers.

In order to further increase the storage density for future technology generations, the structure size is reduced from generation to generation. The ever smaller condensate door area and the resulting decreasing capacitor capacity leads to problems. It is therefore important to keep the capacitor capacity at least constant despite the smaller structure size. This can be achieved, among other things, by increasing the surface charge density of the storage capacitor.

So far, this problem has been solved on the one hand by increasing the available capacitor area (with a given structure size). This can e.g. B. by depositing polysilicon with a rough surface (hemispherical silicon grains) in the trench or on the lower electrode of the stacked capacitor. On the other hand, the surface charge density has hitherto been increased by reducing the thickness of the dielectric. So far, only different combinations of Si0 ₂ (silicon oxide) and Si ₃ N (silicon nitride) have been used as a dielectric for DRAM capacitors. A further reduction in the thickness of these dielectrics is not possible due to the increased leakage currents caused thereby.

A few materials with a higher dielectric constant have also been proposed for stacked capacitors. This explicitly includes Ta ₂ Os and BST (barium strontium titanate). However, these materials are not temperature stable in direct contact with silicon or polysilicon. In addition, they are insufficiently temperature stable.

Furthermore, it was proposed to use deposition processes with very good edge coverage and excellent layer thickness control (such as, for example, atomic layer deposition (ALD or ALCVD)), as a result of which the dielectric materials in structures with very high aspect ratios with very good edge coverage can be deposited in a controlled manner. In particular, these proposed deposition processes are very good at Surface enlargement processes (e.g. wet bottle, HSG) can be combined.

Atomic layer deposition (ALD or ALCVD) can be used to produce an advantageous multilayer structure by repeating the ALCVD process described above several times, layers with a high dielectric constant being embedded in interface layers. In atomic layer deposition (ALD or ALCVD), a first precursor layer is usually deposited on the substrate in a first step, the rinsing chambers are then rinsed and then a second precursor layer is deposited on the first precursor layer in a second step, which layer then selectively and connects in a self-limiting manner with the first precursor layer to the desired layer position. The precursors TMA (TMA = trimethylaluminum Al (CH ₃ ) ₃ ) and H ₂ 0 to form an A1 ₂ 0 ₃ layer layer may be mentioned as an example. Of course there are also examples with more than two precursors.

In the case of the ALD or ALCVD processes mentioned, however, there may be deviations in the stoichiometry of the deposited layer layers from the stable chemical composition of the materials. Furthermore, the initial growth of the dielectric layers can differ locally (nucleation). Foreign atoms from the precursor materials can also be introduced into the deposited films (e.g. H or C).

Such weak points and inhomogeneities in the dielectric lead to leakage currents or breakdowns. This limits the minimum possible layer thickness of the dielectric.

It is the object of the present invention to specify an improved production method of the type mentioned at the outset, which uses a dielectric with a high dielectric constant. constant and even lower leakage currents or leakage current distributions and at least the same capacity.

According to the invention, this object is achieved by the manufacturing method specified in claim 1.

The idea on which the present invention is based is to separate the deposition of the dielectric layer into a number of sub-steps corresponding to individual layers and, after at least one of the sub-steps, a plasma treatment step, e.g. to carry out a plasma oxidation step and / or a thermal treatment step for structural improvement of the dielectric or for improvement of the stoichiometry and for the removal of interfering foreign atoms.

The plasma treatment step, e.g. the plasma oxidation step and / or the thermal treatment step can be provided as required at any intervals, for example after each deposition cycle or for example after ten deposition cycles or only once in the entire deposition process.

Advantageously, the thickness of the dielectric can be reduced in comparison with conventional methods by the treatment in the oxygen-containing plasma.

Advantageous further developments and improvements of the respective subject of the invention can be found in the subordinate claims.

According to a preferred development, the individual layers of the dielectric layer are formed by an ALD or ALCVD method in each case by depositing at least two precursor layers in a respective deposition cycle. The deposition cycle can also have rinsing steps, etc. According to a further preferred development, a plasma treatment step, for example a plasma oxidation step, and / or a thermal treatment step is carried out after the provision of each of the layers.

According to a further preferred development, after the provision of a predetermined number of layers, a plasma treatment step, e.g. a plasma oxidation step, and / or a thermal treatment step is carried out.

According to a further preferred development, a plasma treatment step, e.g. a plasma oxidation step and / or a thermal treatment step is carried out only once in the entire deposition process.

According to a further preferred development, the thermal treatment step provides an annealing in the temperature range 200 to 1100 ° C., in particular after the deposition of all layers.

According to a further preferred development, tempering takes place in a gas atmosphere of one of the following gases or combinations thereof: 0 ₂ , NO, N0 ₂ , forming gas, H ₂ , N ₂ , Ar, NH ₃ , wet oxidation gas or similar inert or oxidizing gases ,

According to a further preferred development, the plasma treatment step, e.g. a plasma oxidation step and / or a thermal treatment step is carried out in situ in the deposition chamber for the layers.

According to a further preferred development, the layers contain a binary metal oxide, preferably A1 ₂ 0 ₃ , Ta ₂ Os, Hf0 ₂ , Zr0 ₂ , La ₂ 0 ₃ , among others. According to a further preferred development, the layers contain a ternary compound, preferably a silicate or an aluminate.

According to a further preferred development, the dielectric layer is part of a storage capacitor.

According to a further preferred development, the dielectric layer is part of a gate dielectric.

According to a further preferred development, the plasma treatment step provides treatment with an activated species, in particular with ozone or UV / ozone.

An embodiment of the invention is illustrated in the drawings and explained in more detail in the following description.

Show it:

Fig. la-n the process steps essential for understanding the invention for producing an exemplary embodiment of the semiconductor component according to the invention in the form of a trench capacitor; and

Fig. 2a-d a detailed illustration of the method step according to FIG. lh.

In the figures la-n, the same reference numerals designate the same or functionally identical elements.

In the present first embodiment, a pad oxide layer 5 and a pad nitride layer 10 are first deposited on a silicon substrate 1, as shown in FIG.

Then another oxide layer (not shown) is removed and these layers are then structured into a so-called hard mask by means of a photoresist mask, also not shown, and a corresponding etching process. Using this hard mask, trenches 2 are etched into the silicon substrate 1 with a typical depth of approximately 1-10 μm. The top oxide layer is then removed in order to reach the state shown in FIG.

In a subsequent process step, as shown in FIG. 1b, arsenic silicate glass (ASG) 20 is deposited on the resulting structure, so that the ASG 20 in particular completely lines the trenches 2.

In a further process step, as shown in FIG. 1c, the resulting structure is filled with photoresist 30. According to FIG. 1d, a lacquer recess, or a lacquer removal in the upper region of the trenches 2, then takes place Etching.

In a further process step according to FIG. 1E, the ASG 20 is likewise isotropically etched in the unmasked, paint-free region, preferably in a wet-chemical etching process. The paint 30 is then removed in a plasma-assisted and / or wet chemical process.

As shown in FIG. 1f, a cover oxide 5 is then deposited on the resulting structure.

In a further process step according to FIG. 1g, the arsenic is diffused out of the remaining ASG 20 into the surrounding silicon substrate 1 in a tempering step to form the buried plate or buried plate 60, which forms a first capacitor electrode. The cover oxide 5 and the remaining ASG 20 are then expediently removed by wet chemical means. According to FIG. 1h, a special dielectric 70 with a high dielectric constant, here A1 ₂ 0 ₃ , is then deposited on the resulting structure by means of an ALD or ALCVD method (atomic layer deposition).

2a-d a detailed illustration of the method step according to FIG. 1h.

First, a monolayer of a first precursor P1, here TMA, is deposited in a corresponding ALD deposition chamber over the resulting structure, in particular the substrate 1 in the trench, as shown in FIG. 2a.

In a subsequent process step, the ALD-Kainmer is first flushed with a flushing gas, such as N ₂ , and then a second precursor P2, here H ₂ 0, is deposited over the first precursor. According to FIG. 2b, this creates a first monolayer 70ι of the dielectric 70, here A1 ₂ 0 ₃ .

In a subsequent process step according to FIG. 2c, a plasma oxidation step PL is then carried out in situ in the ALD deposition chamber.

By means of this plasma oxidation step PL, oxygen atoms can diffuse from the plasma at points where the monolayer 70ι is not closed to the silicon substrate 1 and form an SiO ₂ layer there, so that a possible leakage current path is closed at the corresponding points.

Furthermore, oxygen atoms can occupy free unsaturated bonds to atoms or molecules desired in the dielectric film, e.g. B. in the present example on free Al atoms, so that stoichiometric Al0 ₃ is also formed here. The plasma oxidation step PL thus virtually compensates for the stoichiometry. Furthermore, free bonds to undesired foreign atoms can be saturated by the plasma oxidation step PL, so that they either do not act as traps or impurities or pass into the gas phase and disappear from the dielectric film. For example, free bonds to carbon atoms can be saturated by the oxygen and thereby form CO ₂ . Any hydrogen molecules present can also be removed from the dielectric film 70.

Referring to FIG. 2d the deposition of further layers can 70ι - 70 _n for forming the dielectric layer 70 to repeat until a desired thickness d of the dielectric is achieved.

After the deposition of the entire layer stack 70ι ... 70 _n , an annealing in the temperature range 400 to 1100 ° C takes place. The tempering can take place in a vacuum or in a gas atmosphere of one of the following gases or a combination of these gases: 0 ₂ , NO, N0 ₂ , forming gas, H ₂ , N ₂ , Ar, NH ₃ , wet oxidation gas or a similar oxidizing or inert gas.

After the formation of the special dielectric 70, arsenic-doped polycrystalline silicon 80 is deposited on the resulting structure as a second capacitor plate in a further process step according to FIG. 1 so that it completely fills the trenches 2. Alternatively, polysilicon-germanium or polysilicon-metal layer sequences or also only metal or metal-polysilicon layer sequences could be used for filling.

In a subsequent process step according to FIG. 1 j, the doped polysilicon 80, or the polysilicon germanium or a metal is etched back to the top of the buried plate 60. To achieve the state shown in FIG. 1k, the dielectric 70 is then isotropically etched with a high dielectric constant in the upper exposed region of the trenches 2, either with a wet chemical or a dry chemical etching method.

In a subsequent process step shown in FIG. 11, a collar oxide is 5 ^λ in the upper region of the trenches 2 are formed. This is done by a full-surface oxide deposition and a subsequent anisotropic etching of the oxide, so that the collar oxide 5 ^{λ x} remains on the side walls in the upper trench area.

As illustrated in FIG Im, is deposited in a subsequent process step again doped with arsenic polysilicon 80 ^Λ and etched back.

According to FIG. In, there is finally a wet chemical removal of the collar oxide 5 ^> in the upper trench region.

This essentially completes the formation of the trench capacitor. The formation of the capacitor connections as well as the production and connection with the associated selection transistor are well known in the prior art and require no further mention to explain the present invention.

It has been shown that the plasma oxidation step does not influence the capacitance per trench capacitor or per memory cell.

Furthermore, it has been shown that, for example in the case of a dielectric 70 made of AlO, the plasma oxidation step PL has an advantageous effect on the leakage current distribution of the individual capacitors. Although the present invention has been described above on the basis of a preferred exemplary embodiment, it is not restricted to this but can be modified in a variety of ways.

In particular, the invention can be used for any multilayer dielectric layers.

The present invention is particularly applicable to all memory products and gate materials.

LIST OF REFERENCE NUMBERS

Manufacturing method for a semiconductor device

1 silicon substrate

3 expanded area

5 pad oxide

5 ^Λ top oxide

5 collar oxide

10 pad nitride

20 ASG

30 photoresist

60 buried plate

70 dielectric

80, 80 ^Λ doped polysilicon

P1, P2 first, second precursor

70χ ... 70 _n layers

PL plasma oxidation step

Claims

claims

1. A method of manufacturing a semiconductor device ^'with a recess provided on or in a substrate (1) multi-layer dielectric layer (70; 70ι ... 70 _n),

characterized in that at least after the provision of one of the layers (70ι ... 70 _n ), a plasma treatment step, for example a plasma oxidation step, and / or a thermal treatment step is carried out.

2. The method according to claim 1, characterized in that the individual layers (70ι ... 70 _n ) of the dielectric

Layer (70; 70ι ... 70 _n ) are formed by an ALD or ALCVD process in each case by deposition of at least two precursor layers in a respective deposition cycle.

3. The method according to claim 1, 2 or 3, characterized in that after the provision of each of the layers (70ι ... 70 _n ), a plasma treatment step, for example a plasma oxidation step, and / or a thermal treatment step is carried out.

4. The method according to claim 1, 2 or 3, characterized in that in each case after the provision of a predetermined number of layers (70χ ... 70 _n ), a plasma treatment step, for example a plasma oxidation step, and / or a thermal treatment step is carried out.

5. The method according to claim 1, 2 or 3, characterized in that a plasma treatment step, for example a plasma oxidation step, and / or a thermal treatment step is carried out only once in the entire deposition process.

6. The method according to any one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that the thermal treatment step provides an annealing in the temperature range 200 to 1100 ° C.

7. The method according to any one of the preceding claims, characterized in that after the deposition of all layers (70ι ... 70 _n ) an annealing in the temperature range 200 to 1100 ° C takes place.

8. The method according to claim 5, characterized in that the tempering takes place in a gas atmosphere of one of the following gases or combinations thereof: 0 ₂ , NO, N0 ₂ , forming gas, W_, N ₂ , Ar, NH ₃ , wet oxidation gas or similar inert or oxidizing gases.

9. The method according to any one of the preceding claims, characterized in that the plasma treatment step, for example a plasma oxidation step, and / or a thermal treatment step is carried out in situ in a deposition chamber for the layers (70ι ... 70 _n ).

10. The method according to any one of the preceding claims, characterized in that the layers (70χ ... 70 _n ) contain a binary metal oxide, preferably A1 ₂ 0 ₃ , Ta0 ₅ , Hf0 ₂ , Zr0 ₂ , La ₂ 0 ₃ , among others.

11. The method according to any one of the preceding claims, characterized in that the layers (70ι ... 70 _n ) contain a ternary compound, preferably a silicate or an aluminate.

12. The method according to any one of the preceding claims, characterized in that the dielectric layer (70; 70ι ... 70 _n ) is part of a storage capacitor.

13. The method according to any one of the preceding claims 1 to 11, characterized in that the dielectric layer (70; 70 _.... 70 _n ) is part of a gate dielectric.

14. The method according to any one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that the plasma treatment step provides treatment with an activated species, in particular with ozone or UV / ozone.