WO2003034601A1

WO2003034601A1 - Wireless lan

Info

Publication number: WO2003034601A1
Application number: PCT/EP2002/011199
Authority: WO
Inventors: Sabine Roth; Martin Rieger; Heinrich Schemmann
Original assignee: Thomson Licensing S.A.
Priority date: 2001-10-16
Filing date: 2002-10-05
Publication date: 2003-04-24
Also published as: DE10150476A1

Abstract

According to the HIPER-LAN 2 system standard for wireless data communication, the output power Pout in each case needed at the transmitting end of the devices involved in the data communication is determined by control which, however, is associated with corresponding effects on the ratio between output power and power dissipation at the transmitting end. According to the invention, in particular, amplifier stages 2, 4, 5 with power dissipation in the data signal path of the transmitting device of such devices are in each case only supplied with the amount of power Psupply required for maintaining the linearity in the data signal processing depending on the required output power Pout. This reduces the power dissipation in such devices and improves the efficiency.

Description

Wireless LAN

The invention is based on a network for wireless data communication, also called wireless LAN (Local Area Network) , between devices having a corresponding receiving and transmitting device, and, in particular, relates to their transmitting area.

In data transmission, such devices operate with a multiplicity of carrier frequencies, preferably based on a method known as OFDM (Orthogonal Frequency Division Multiplex) . Because of different propagation conditions (e.g. due to multi-path reception, buildings in the environment) , they must be able to cover a relatively large transmitting power range of e.g. 48 dB (decibels), and circuit-related distortion and circuit-related signal interference must be avoided.

It is therefore known of devices for' wireless data communication to operate amplifiers provided in the stages of their data signal path at the transmitting end in a control range which is largely linear, and to counteract field strength fluctuations (e.g. in a mobile radio system, due to change in the transmission path) correspondingly with a variation' of the transmitting power by adjustment of the output power at the transmitting end as a consequence of a control provided for this purpose. According to the HIPER- LAN 2 system standard for wireless data communication, the output power at the transmitting end which is needed in the respective case for the communication of two devices is determined in the control in that in each case the device currently operating as receiver informs the device operating as transmitter, in principle, whether more or less transmitting power is required which, however, is associated with corresponding effects on the relationship between output power at the transmitting end and power dissipation of the relevant device . The criterion for the controllability of the transmitter is the so-called 1-dB compression point at which the output signal would be compressed by 1 dB due to overdriving of one or more stages in the data signal path at the transmitting end.

The corresponding modulation method predetermines a minimum margin, also called back off, of e.g. 6 dB by which the transmitting signal must be less than the 1-dB compression point of the transmitter for the influence of the distortion on the data signal to be transmitted with regard to receiver signal/noise ratio, data error rate and data rate still be to tolerable.

In the definition of the control range with the demand for distortionless data signal paths and the variation of the transmitting power, production and/or component tolerances must also be taken into consideration which can reduce the efficiency of such devices even further.

The invention, therefore, deals with the object of demonstrating a concept for the transmitting area of devices for wireless data communication, by means of which the efficiency can be improved, taking into consideration technological requirements and the demand for linear signal transmission paths with a relatively large range of output power.

The object is achieved by a method specified in Claim 1 and by a device specified in Claim 7.

The invention is based on the concept of supplying the transmitting device of such devices, depending on the required output power or, respectively, power to be radiated, in each case only with the amount of energy which is required for maintaining the abovementioned linearity for the data signal processing so that stages with power dissipation such as, in particular, amplifier stages in the data signal path can always be operated in such a manner that the output does not drop below a back off of e.g. 6 dB of the entire data signal path at the transmitting end and in order to achieve the improvement in efficiency aimed for.

In principle, therefore, adjustable power supplies for stages with power dissipation are provided in the transmitting device of the respective device and corresponding gain adjustments are performed for their respective control according to the invention.

For this purpose, it is sufficient and thus saves expenditure if the relevant adjustments of the supply power and/or of the gain in the path of the data signal processing are constructed incrementally.

In a further development of the invention, the transmitting device is integrated in an integrated circuit (IC) for wireless data communication although there are actually important reasons against integrating the transmitting device because of the technology for such ICs (the breakdown voltage at which a corresponding transistor structure is destroyed is within a range of 2 to 4 volts) and, as already mentioned initially, because of the relatively large range of transmitting power and the relatively high demands on linearity.

In practice, all the aforementioned adjustments for power supply and gain can be performed with the IC according to the invention. To ensure reliable operating conditions - particularly because of the adjustment of the power supply for maximum output power - an overload protection and a circuit for temperature monitoring are also provided according to the invention.

By integrating the transmission device in an IC, devices and corresponding devices for wireless data communication can be advantageously simplified. The invention will be explained in greater detail with reference to the drawing of an illustrative embodiment, in which:

Fig. 1 shows a block diagram of the transmitting device according to the invention;

Fig. 2 shows diagrams a) to d) for illustrating the operation of the transmitting device according to the invention and

Fig. 3-5 show circuit diagrams for the block diagram according to Fig. 1.

In Fig. 1, the part essential to the invention of the transmitting device of a device having a receiving and transmitting device for wireless data communication is shown by means of a simplified block diagram.

This part of the transmitting device has for the data communication a data signal processing path which essentially comprises the following circuit .stages 1-6, arranged in series: a first intermediate-frequency amplifier hereinafter called first IF amplifier 1, a second intermediate frequency amplifier hereinafter called second IF amplifier 2, a second frequency converter 3 constructed as mixer, a first amplifier 4 constructed as driver stage and a second amplifier 5 forming the output stage of the transmitting device, the output of which amplifier is connected to a load 6 which is constructed as antenna in mobile devices such as, e.g. so-called "mobiles", but can also be an external filter and/or amplifier circuit which can be connected to the device output .

The part of the data signal processing path of the transmitting device which is not essential to the invention and is not therefore shown comprises in a manner known per se an input amplifier, a filter circuit called DAC post filter and a first frequency converter in order to convert the data signal used for the data communication from e.g. 60 MHz (Megahertz) which is supplied to it via the input amplifier and the filter circuit by a digital/analogue converter, also not shown, into an intermediate frequency of e.g. 1.225 GHz (Gigahertz). The frequency-converted data signal is then fed into the input of the first IF amplifier 1 for further processing.

Due to a conversion by means of the second frequency converter 3, the data signal finally exhibits a frequency of e.g. 5 GHz at the output of the transmitting device.

The circuits according to circuit blocks 1-5 are preferably constructed with in each case one inverting data signal input and one non-inverting data signal input and with in each case one inverting data signal output and one non-inverting data signal output, also called first and second connections for the data signal hereinafter. These circuits exhibit adjusting means, which can be controlled by a microprocessor 8, by means of which supply power and/or gain can be adjusted for these circuits in order to be able to control them in accordance with the invention - i.e. depending on the output power needed in the data communication, in such a manner that the data signal at the output of the transmitting device, called data output signal 7 hereinafter, in each case reaches or maintains the back off of e.g. 6 dB predetermined by the corresponding modulation method and mentioned initially, the respective adjustment of the supply power and/or the gain being made via a so-called BUS interface 9 and control lines 10.

The output power needed in each case is determined in the known manner, initially explained, with the other device involved in the wireless data communication. The information about the output power needed is supplied to the microprocessor 8 via a data microprocessor bus 11 whereupon the microprocessor, according to the invention, performs the respective adjustment of the supply power and/or of the gain.

These adjustments are preferably incremental and take place in predetermined steps of the same step size as shown by way of example with the sections d₀-d₄ along the respective abscissa of diagrams a) to d) shown in Fig. 2.

The principle of the operation of the transmitting device according to the inventron is explained in greater detail with reference to these diagrams a) to d) :

The abscissa of the respective diagrams a) to d) is a measure of the output power P_out which is needed for the wireless data communication.

The ordinates of diagrams a) to d) represent normalized gains v_norm. The ordinate of diagram d) is a measure of the supply power _SUp ]__y which, according to the invention, is provided in each case depending on the output power P_out needed whereas the ordinate of diagram c) is a measure of the output power P_out generated during this process by the transmitting device in dB (decibels) .

Diagram a) symbolically shows step-like gain profiles L1-L3 as a result of the step-like gain adjustments depending on the output power needed. The profiles L1-L3 represent the gain settings for

- the second amplifier 5 which forms the output stage of the transmitting device (according to the continuous line LI) ,

- the first amplifier 4 which is constructed as driver stage (according to the dashed line L2) , and, respectively,

- the second IF amplifier 2 (according to the dotted line L3) .

Due to the fact that gain adjustments at the second frequency converter 3 are preferably not provided, a corresponding variation for the second frequency converter 3 is not shown.

Diagram b) symbolically shows a sawtooth-shaped gain variation as a result of the gain adjustments for the first IF amplifier 1 with a ramp-like rise in the gain within each adjustment step d₀-d₄ and a corresponding resetting to a predetermined value. Such a gain variation which can also be composed of a multiplicity of small steps within each adjustment step dø-d₄ and can be generated with the aid of the microprocessor 8, e.g. with a circuit known as "amplifier with a dB-linear output voltage" from US-A- 5,874,857, is provided for linearizing the overall gain according to the invention. As is symbolically shown in diagram c) with the step-like variation L4 of the output power, the overall gain would otherwise exhibit a step-like variation due to the step-like gain adjustments for the second IF amplifier 2, the first amplifier 4 constructed as driver stage and the second amplifier 5 forming the output stage of the transmitting device.

Diagram c) shows the linear variation L5 of the output power which is obtained from assembling the gain variations of diagram a) and diagram b) . Variation L4 reproduces the associated variation of the 1-dB compression point, mentioned initially, with an adjustment of the gains and of the supply power according to the invention.

The interaction^' of the gain adjustments with the result of a continuous output power variation L5 is advantageous because, as a result, the data output signal 7 does not drop below the back off of e.g. 6 dB, or only insignificantly so (at the beginning of each adjustment step dø-d₄) at the end of each adjustment step dg-d₄ and thus virtually at each required output power. As diagram d) shows, the supply power is adapted at the same time with each step. Thus, the required minimum margin of e.g. 6 dB is ensured at each stage. As is intended to be shown with step d₄ in diagram c) and d) , the second amplifier 5 which forms the output stage of the transmitting device exhibits, at maximum supply power ^p _suppi_y/ the maximum upper limit of its controllability, where controllability is intended to mean the full drive at which there is not yet any overdriving. According to diagram a) the first amplifier 4 constructed as driver stage and the second IF amplifier 2 are also preferably adjusted for maximum gain, in addition to the second amplifier 5.

This step d₄ is intended to characterize, at the same time, the maximum output power, called P_{out ma}x hereinafter, at the signal output of the second amplifier 5 which can be 10 dBm, e.g. in the case of a connected load 6 of 50 ohms, and is predetermined by the breakdown voltage of the output transistors of the second amplifier 5 which are preferably to be arranged in an IC.

If the output power drops below this output power

P_{out max}, which has a back off of 6 dB, by a predetermined amount (e.g. as a result of an improvement in the propagation conditions) , the gain and the supply power ^p _supply °f the second amplifier 5 forming the output stage of the transmitting device are reduced according to the invention - as is intended to be illustrated e.g. with the transition from adjustment step d₄ to adjustment step d₃ - in such a manner that the data output signal 7 again exhibits a back off of virtually 6 dB even with a reduced gain of the second amplifier 5 (but maximum gain of the first IF amplifier 1 due to its sawtooth-shaped gain variation) ; or in other words: the control range of the second amplifier 5 which is correspondingly reduced by adjustment of the supply power _SUpPi_y is utilized in the same way as in step d₄, i.e. as a result of the gain adjustment of the second amplifier 5, which is reduced in a step-like manner, and the gain adjustment of the first IF amplifier 1 (rising in a ramp-like manner within an adjustment step) , so that the data output signal 7 cannot drop below a back off of 6 dB at the end of the adjustment step d₃ (at the same time transition from adjustment step d₄ to adjustment step d₃ or conversely) . According to diagram a) , however, the gain of the first amplifier 4 which is constructed as driver stage, and the gain of the second RF amplifier 2 remain unchanged.

If, as is intended to be shown by way of example with adjustment step d_2/ the output power drops further below the output power P_{out max} (^e-9- ^as result of a further improvement in the propagation conditions) by a predetermined amount, the supply power P_SUppi_y and the gain of the second amplifier 5 forming the output stage of the transmitting device are correspondingly reduced further according to the invention so that in this case, too, this amplifier 5 is controlled in such a manner that the data output signal 7 exhibits a back off of virtually 6 dB immediately after the transition from adjustment step d₃ to adjustment step d₂. According to diagram a), the gain of the first amplifier 4 constructed as driver stage and the gain of the second IF amplifier 2 also remain unchanged in this case.

If, however, as is intended to be shown by way of example with step d^_ the output power drops even further below the output power P_{out ma}χ by a predetermined amount, the supply power P_suppi_y and the gain are reduced further, according to the invention, depending on the output power ^p _out iⁿ this case, too. However, the supply power P_8uppi_y and the gain are now preferably reduced at the first amplifier 4 constructed as driver stage, in such a manner that a signal compression would essentially now occur by means of the first amplifier 4 for the entire data signal path at the transmitting end - e.g. corresponding to the 1-dB compression point of the transmitter - since, according to the invention, the second amplifier 5 which forms the output stage of the transmitting device is now no longer driven to such an extent .

As is shown in diagram a) , the gain of the second IF amplifier 2 remains unchanged, and the gain of the second amplifier 5 is reduced during step d]_ .

If, in addition, as is intended to be shown by way of example with step U_Q , the output power drops further below the output power P_{out max} (e.g. due to the improvement in the propagation conditions) until finally a minimum output power P_{out min} is reached, the supply power P_suppi_y and the gain are reduced further in this case, too, according to the invention. The supply power _suppi_y is reduced both in the second frequency converter 3 constructed as mixer and in the second IF amplifier 2 whereas, however, the gain is only reduced in the second IF amplifier 2 so that a signal compression for the entire data signal path at the transmitting end - e.g. corresponding to the 1-dB compression point of the transmitter - would now essentially take place by means of the second IF amplifier 2.

In this connection, the reduction in the supply power 3?_su_pply at the second frequency converter 3 constructed as mixer serves a different purpose according to the invention, as will be explained later in the description for Fig. 3.

It should be pointed out here that the number of adjustment steps d₀-d₅ for reducing or adjusting the supply power P_suppi_y and/or gain is only an example and that continuous adjustments can also be provided instead of such steps .

In addition, it is conceivable to aim for a larger back off if further transmit amplifier stages follow, or instead of the load 6. This can be achieved by, e.g. permanently setting the second IF amplifier 5 for a low gain which means a reduction in the adjustment range by e.g. 10 dB. Due to the adjustments in the supply power P_suppi_y and/or gain depending on the required output power P_Du_t' stages with power dissipation such as, in particular, the amplifier stages 2, 4, 5 in the data signal path are thus in each case supplied only with the amount of power required for maintaining the abovementioned linearity for the data signal processing and, in principle, the output power P_out needed in each case determines the circuit block or blocks 1-5 at which a corresponding adjustment of the supply power ^p _supply and/or gain must be performed.

In a development of the transmitting device according to the invention, it is provided to integrate the circuits according to circuit blocks 1-5 into an integrated circuit (IC) .

To ensure reliable operating conditions for such an IC - particularly because of the adjustment of the supply power for maximum output power P_{out max} - an overload protection circuit 12 (Fig. 1) is provided as is shown further in Fig. 1, which is connected to the microprocessor 8 via a first line connection 13 (Fig. 1) and the BUS interface 9.

The overload protection circuit 12 exhibits a voltage detector by means of which it preferably monitors the respective amplitude of the data output signal 7 via a second line connection 14 (Fig. 1) . In this arrangement, the transmitting device with the voltage detector in the overload protection circuit 12, the microprocessor 8

(including the BUS interface 9) and the circuits according to circuit blocks 1-6 forms a control device in which the data signal at the output of the transmitting device is used as controlled variable for a controller formed by microprocessor 8, BUS interface 9 and voltage detector together while the adjustment means in the circuits according to circuit blocks 1-5 act as control elements. To protect, the IC against an inadmissible increase in temperature, a further protection circuit 15 (Fig. 1) is provided. This circuit 15, by means of which the temperature can be monitored, has a connection to the microprocessor 8 via a third line connection 16 (Fig. 1) and the BUS interface 9. The protection circuits 12 and 15 are also integrated in the aforementioned IC.

In the text which follows, preferred embodiments of the circuits for the second IF amplifier 2 (Fig. 3) , the second frequency converter 3 (Fig. 3) , the first amplifier 4 constructed as driver stage (Fig. 4) and the second amplifier 5 forming the output stage of the transmitting device (Fig. 5) are described.

Fig. 3 shows a simplified circuit diagram for the second IF amplifier 2 and the second frequency converter 3. Both circuits are arranged between reference potential (earth) and the positive potential +V_CC of an operating voltage source, not shown. In principle, the second IF amplifier 2 is formed with two parallel-connected series circuits of in each case one differential amplifier 20; 20' and a switchable current source II; nxll.

The respective differential amplifier, called first (20) and second (20') differential amplifier in the text which follows, in each case exhibits a first transistor (TI; TI ' ) and second transistor (T2; T2 ' ) , the emitters of the transistors TI, T2 belonging to the first differential amplifier 20 being connected via in each case one emitter resistor Rl to the current source II which will be called the first switchable current source II in the text which follows, whereas the emitters of the transistors TI ' , T2 ' belonging to the second differential amplifier 20' are connected via in each case one emitter resistor Rl/n to the current source nxll which will be called second switchable current source nxll in the text which follows. Both differential amplifiers 20, 20' have a common first and a common second connection for the incoming data signal or the data signal supplied to the second IF amplifier 2 in that both the base terminals of the first two transistors TI; TI ^■ and the base terminals of the second two transistors T2; T2 ^■ are connected to one another and form the data signal input DATA_IN of the second IF amplifier 2.

In addition, each of the transistors TI, T2 of the first differential amplifier 20 has a common first and a common second connection with one of the transistors TI ' , T2 ' of the second differential amplifier 20' for the data signal amplified by the second IF amplifier 2 in that both the collector terminals of the first two transistors TI; TI ' are connected via a common collector resistor Rl, and the collector terminals of the second two transistors T2 ; T2 ' are connected via a common collector resistor Rl, to the positive potential +V_Cc of the operating voltage source and form the data signal output D TAo_UT of the second IF amplifier 2 from where the amplified data signal is supplied to the data signal input DATA_IN of the second frequency converter 3 via coupling capacitors C, C for further processing.

The multiple use of the reference symbols C, Rl, II and n is intended to point to an advantageous simplification in the circuit. Thus, e.g. n = 3 is to be provided for a gain variation of 10 dB.

The first switchable current source (II) and the second switchable current source (nxll) arranged between the first and second differential amplifier 20; 20', respectively, and reference potential, by means of which sources, according to the invention, the respective supply power P_SUpply to the second IF amplifier 2 is determined, in each case exhibits a switch SI; SI' controlled by the microprocessor 8. The control by the microprocessor 8 is effected in such a manner that either the first or the second differential amplifier 20; 20' is in operation. The respective switching-over of the current sources 13, nxI3 advantageously in each case also enables the supply power P_suppi_y to be adjusted and for the gain for the second IF amplifier 2 to be adjusted with a constant operating voltage v_Cc-

The first differential amplifier 20 with the first switchable current source II and the second differential amplifier 20' with the second switchable current source nxll thus in each case form a first and second gain path for the data signal to be amplified by the second IF amplifier 2. The switch position shown (SI closed and SI' opened) corresponds to adjustment step dg . In the switch position not shown (SI' closed and SI opened) which is intended for adjustment steps d;_L-d₄, the second IF amplifier 2 has the greater gain of 10 dB, already mentioned by way of example.

As the second frequency converter 3, a circuit constructed as multiplier is preferably used which has two parallel-connected series circuits of in each case one differential amplifier 30; 30' and the collector-emitter path of a transistor T3 ; T3 ' having an emitter resistor R2 , the transistors T3, T3 ' in conjunction with two parallel- connectable current sources 12, nxI2 forming the input stage DATA_IN of the frequency converter 3 according to the invention.

The differential amplifiers 30; 30' are constructed with in each case a first transistor (T4; T4 ' ) and a second transistor (T5; T5 ' ) in a manner known per se, in each case two corresponding collector terminals connected to the positive operating voltage +V_Cc via a common impedance Z forming the data signal output DATA_0UT of the second frequency converter 3 while in each case two base terminals, correspondingly connected to one another, of these transistors T4, T5 ' ; T4 ' , T5 are used as signal input U_osz for the signal of the local oscillator LO (Fig. 1) for the data signal to be frequency-converted. The emitter terminals, which in each case belong together or, respectively, are connected to one another, of these transistors T4, T5; T4 , T5 ' are connected to the collector terminal of the corresponding transistor T3 ; T3 ' of the input stage of the frequency converter 3, called third transistors T3 ; T3 ' in the text which follows.

The base terminals of the two third transistors T3 ; T3 ' are used as data signal input DATA_IN of the frequency converter 3 for the data signal which is to be converted, for example, from 1.225 GHz to 5 GHz as already mentioned. Their emitter terminals are connected to one another via two emitter resistors R2, R2 correspondingly provided, and the two current sources 12, nxI2, which can be connected in parallel, are arranged between the junction and reference potential (earth) .

The circuit constructed as multiplier can be operated by the two current sources 12, nxI2, which can be connected in parallel with one another, with different supply currents or basic currents also called biasing, according to the invention, because of the linearity required by the transmitting device and of a current-dependent influence due to a DC offset of the input stage of the frequency converter 3 (LO feed-through) of the local oscillator signal LO on subsequent circuits, the respective supply currents being dimensioned to be as low as possible for the above reasons.

Each of these current sources 12, nxI2, differing from one another by the factor n, called first current source (12) and second current source (nxI2) in the text which follows, exhibits a switch S2; S2 ' controlled by the microprocessor 8. The control by the microprocessor 8 is effected in such a manner that either the first current source 12 or the second current source nxI2 are in operation. Using the switching-over of the current sources 12, nxI2 according to the invention which, due to the circuit configuration of the frequency converter 3, results in virtually no gain adjustment, the current-dependent influence due to the DC offset of the input stage of the frequency converter 3 (L0_feecj through.) °f the local oscillator signal LO is correspondingly adapted to the subsequent circuit blocks 4, 5 in that in the gain reduction (Fig. 2, step d₀) of the second IF amplifier 2 by e.g.

10 dB, the abovementioned supply current is also reduced by preferably 10 dB by switching from the second current source (nxI2) to the first current source (12) , or conversely at a corresponding increase in gain (Fig. 2, step d^) of the second IF amplifier 2. As a result, the ratio between the data signal and the local oscillator signal LO_feecj t_hroug_h breaking through is advantageously improved when less output power P_out is needed (step.2c, step d₀) and the linearity required of such a transmitting device is retained in the processing of the data signal .

In addition, the switch-over from the second current source (nxI2) to the first current source 12 according to the invention results in an advantageous saving of supply power P_suppi_y as side effect; the switch position shown (S2 closed and S2 ' opened) corresponds to adjustment step dg .

Fig. 4 shows a simplified circuit diagram of the first amplifier 4 constructed as driver stage. In principle, its circuit configuration with two parallel-connected series circuits, arranged between reference potential and positive operating voltage potential +Vc of in each case a differential amplifier 40; 40' and a switchable current source 13 ; 14 corresponds to the second IF amplifier 2 shown in Fig. 3.

Its data signal input DATA_IN, which is formed by correspondingly interconnected base terminals of first transistors (T6, T7 ' ) and second transistors (T6¹, T7) of the two differential amplifiers 40; 40' is connected via a filter circuit which, in the simplest case, can be an LC filter and is provided, in particular, for suppressing the local oscillator signal LO, to the data signal output DATA_0UT of the second frequency converter 3.

The data signal output DATAo_UT of the first amplifier 4 constructed as driver stage is formed by correspondingly interconnected collector terminals, connected to the positive operating voltage potential +V_Cc via a common resistor R5; R5 ' , of the first transistors (T6, T7 ' ) and the second transistors (T6', T7) of the two differential amplifiers 40; 40'.

The emitter terminals of the transistors T6, T7 belonging to the first differential amplifier 40 are connected via in each case one emitter resistor R3 to the current source 13 which will be called the first switchable current source 13 in the text which follows while the emitters of the transistors T6 ' , T7 ' belonging to the second differential amplifier 40' are connected via in each case one emitter resistor R4 to the current source 14 which will be called the second switchable current source 14 in the text which follows.

The first switchable current source (13) and the second switchable current source (14) arranged between the first and second differential amplifier 40; 40', respectively, and reference potential, by means of which sources, according to the invention, the respective supply power P_suppi_y for the first amplifier 4 constructed as driver stage is determined, in each case exhibits a switch S3; S3¹ controlled by the microprocessor 8. The control by the microprocessor 8 is preferably effected in such a manner that either the first differential amplifier or the second differential amplifier 40; 40' is in operation. The respective switching-over of the current sources 13, 14 advantageously provides here, too, in each case both for the adjustment of the supply power P_suppi_y and the adjustment of the gain for the first amplifier 4, constructed as driver stage, with constant operating voltage V_cc. The first differential amplifier 40 with the first switchable current source 13 and the second differential amplifier 40' with the second switchable current source 14 thus form here, too, in each case a first and, respectively, second gain path for the data signal to be amplified by the first amplifier 4. The switch position shown (S3 closed and S3' opened) corresponds to adjustment step d]_ . In the switch position not shown (S3 ' closed and S3 opened) which is provided for adjustment steps d₂-d₄, the second IF amplifier 2 exhibits a gain which is greater by e.g. 10 dB.

Fig. 5 shows the principle of a circuit concept according to the invention for the second amplifier 5, which forms the output stage of the transmitting device, by means of a block diagram a) in connection with more detailed circuit diagrams b) and c) .

As is shown in the block diagram, the second amplifier 5 comprises three parallel-connected circuit blocks 50-52, which, in principle, are similar, with a common data signal input DATA_IN and a common data signal output D TA_OO to which, e.g. the external load 6 shown in Fig. 1 is connected.

To be able to reduce or vary the supply power P_SUppiy depending on the required output power P_out in accordance with the invention, the first (50) , the second (51) or the third (52) circuit block are switched on in a preferred circuit embodiment of the second amplifier 5 (in accordance with the adjustment steps d₂-d₄ shown in Fig. 2) : thus, in the case of a maximum output power P_out (i.e. according to adjustment step d₄) e.g. the third circuit block 52 is switched on. The second circuit block 51 is then provided for the output power P_out according to adjustment step d₃ while the first circuit block 50 is provided for the output powers P_out according to adjustment steps d₀-d₂. Compared with the first circuit block 50, the third circuit block 52 should preferably have a gain which is greater by 20 dB and the second circuit block 51 should have a gain which is greater by 10 dB.

In the case where the transmitting device is taken into operation (also from the so-called standby mode) - that is ^• to say during the start-up phase in which the output power P_ot at the transmitting end is still determined in a known manner - the third circuit block 52 is preferably first switched on according to adjustment step d₄ while the other circuit blocks 51 and 50 are switched off. The procedure is analogous (greatest gain adjustment in each case) corresponding to adjustment step d₄ with regard to the gain adjustment at circuit stages 1-4 which are arranged in front of the second amplifier 5 in the path of data signal processing.

Fig. 5 b) shows a simplified circuit diagram of the respective circuit block 50-52. Each of these circuit blocks 50-52 connected in parallel between reference potential and the positive potential +V_Cc of the operating voltage source has an input stage 53 and an output stage 5 .

It is pointed out in this connection that, for the sake of simplicity, identical reference symbols are used for all corresponding circuit sections of circuit blocks 50-52 in the text which follows.

The input stage 53 of the respective circuit blocks 50- 52 essentially consists of in each case two emitter follower circuits connected in parallel between reference potential and operating voltage +V_Cc# of in each case one transistor T50; T50' and a switchable current source I_Dcι; 1'_DCI arranged between its emitter terminal and reference potential, called first current sources I_Dci/ I'_DCI in the text which follows, the base terminals of these transistors T50, T50' forming the data signal input DATA_IN of the respective circuit block 50-52. The first current sources I_Dcι; I'DCI of the respective circuit blocks 50-52 in each case have a first switch S50; S50', which can be' controlled by the^' microprocessor 8, in order to be able to switch off advantageously also their input stage 53 in the cases of correspondingly less required output power P_out according^' to the adjustment steps d₂-d₄ shown in Fig. 2 - or to be able to switch the input stage 53 on again in cases of correspondingly more required output power P_out- Furthermore, a second switch S51; S51', which can be controlled by the microprocessor 8, is connected in parallel with the collector-emitter path of the respective transistor T50, T50' in the input stage 53 of the respective circuit block 50-52. The second switches S51, S51 ' are provided for preventing crosstalk between input and output of circuit blocks 50-52 switched off. As an alternative, the respective second switch S51; S51' can also be connected in parallel with the corresponding first current source I_DCI; I'_DCI to prevent such crosstalk.

The data signal is supplied to the output stage 54 from the emitter of the respective transistor T50, T50 ' in the input stage 53 of the respective circuit block 50-52 via a filter constructed as high-pass filter, which preferably consists of an RC section (C50, R50; C50', R50 ' ) and is intended to block signals below the data signal frequency.

The output stage 54 of the respective circuit block 50- 52 is formed by in each case two series circuits, arranged between the positive operating voltage +V_CC and reference potential, of in each case a switchable current source I_Dc₂; I'_DC2, called second current sources I_Dc₂ I'DC2 in the text which follows, and a circuit, constructed as current mirror, with a diode-connected transistor T51; T51', the short- circuited base-collector path of which is connected to the base terminal of a corresponding transistor 52; 52' operated as a common-emitter circuit which provides the output current of the respective current mirror. The collector terminals of the two transistors 52, 52' supplying the current mirror output currents, and thus the data output signal 7, form the data signal output DATA_OU of the respective circuit block 50-52.

The short-circuited base-collector path of the respective diode-connected transistor T51; T51' is also connected via the corresponding high-pass filter (C50, R50; C50', R50') to the emitter of the corresponding transistor T50; T50' of the input stage 53 and, in addition, can be connected to the positive operating voltage potential +V_Cc by the corresponding second switchable current source I_Dc₂;

I ' DC2 ■

The second current sources I_Dc2; I'_DC2 of the respective circuit blocks 50-52 in each case have a third switch S52; S52 ' , which can be controlled by the microprocessor 8, in order to be able to switch off the output stages of 54 of corresponding circuit blocks 50-52 - according to adjustment steps d₂-d₄ shown in Fig. 2 - in the cases of less required output power P_out or to be able to switch them on again in the cases of more required output power P_out-

Although the illustration shows the first switches (S50, S50'), the second switches (S51, S51 ' ) and the third switches (S52, S52 ' ) , controlled by the microprocessor 8, in the open position, the first switches (S50, S50') and the third switches (S52, S52 ' ) are closed in the switched-on state of the respective circuit block 50-52 while the second switches S51, S51' are opened; in the switched-off state of the respective circuit block 50-52, in contrast, the first switches (S50, S50 ' ) and the third switches (S52, S52 ' ) are opened while the second switches S51, S51' are closed.

Using the high-pass filters (C50, R50; C50', R50') between input stage 53 and output stage 54 of the respective circuit block 50-52 advantageously makes it possible to define or dimension the currents of the first current sources (I_DC_I/ I'_DCI)- and of the second current sources (IDC₂/ I'_DC2) independently of one another so that these stages 53, 54 have the necessary linearity in the processing of the data signal. Thus, the transistors T50, T50' operated as emitter follower circuit in the respective circuit block 50- 52 require a relatively large fundamental current of in comparison with the fundamental current of the diode- connected transistors T51, T51 ' in the output stage 54 constructed as current mirror.

According to the invention, however, the fundamental currents which can be adjusted by means of the first current sources (IDCI/ I'DCI) and the second current sources (I_Dc₂, I'_DC2)_/ respectively, are only selected to be of such a magnitude that input stage 53 and output stage 54 of the respective circuit block 50-52 meet the requirement for linearity in the processing of the data signal.

For the data signal fed into the signal input DATA_IN the input stage 53 of the respective circuit block 50-52, in conjunction with the corresponding high-pass filters (C50, R50; C50', R50 ' ) acts like a voltage/current converter from which the data signal flows as data signal current into the signal input of the output stage 54 constructed as current mirror. The amplification is then effected by multiplying the data signal current by means of the transistors T52, T52 ' supplying the data output signal 7, which - as is shown symbolically in Fig. 2 c) by means of the parallel- connection of individual transistors T52 (1) -T52 (1+n) - are constructed as so-called multiple transistors in accordance with the intended gain of the respective circuit block 50- 52.

Finally, it should be pointed out that the invention has been described by means of a preferred illustrative embodiment; in accordance with the embodiment of a further illustrative embodiment, not described in greater detail, however, it is also possible to provide adjustments according to the invention with regard to the supply power ^p _supply ^anc^ the gain depending on the required output power P_out only in the second amplifier 5 forming the output stage of the transmitting device or/and in the first amplifier 4 constructed as driver stage.

Claims

Patent Claims

1. Method for reducing power dissipation at the transmitting end in the operation of a communications system operating bidirectionally, in particular, on the basis of the orthogonal frequency division multiplex method (OFDM) with wireless data transmission between corresponding devices in each case having a receiving and transmitting device, which, in the case of a change in the data transmission path and/or the propagation conditions, correspondingly counteract a variation in the transmit power by adjusting the output power P_out of their transmitting device, characterized by the following steps: evaluation of the data signal transmission at the device operating as receiver and reporting to the device operating as transmitter whether more or less output power Pout is needed and adapting the supply power depending on the result of the evaluation by automatically adjusting the supply power P_SUpply and/or the overall gain of the device operating as transmitter in the transmitting device.

2. Method according to Claim 1, characterized in that the adjustment of the supply power P_SUpply and/or of the overall gain is effected depending on the required output power P_out in each case on the basis of an adjustment criterion which is determined with regard to the controllability of the transmitting device by a minimum margin (back off) from the 1-dB compression point predetermined by the modulation method of the communications system, at which the data output signal (7) would be compressed by 1 dB due to overdriving of one or more stages (1-5) in the data signal path at the transmitting end.

3. Method according to Claim 2, characterized in that the adjustment of the supply power P_SUpp_ly and/or of the overall gain is effected by corresponding adjustment of the supply power P_SUppiy and/or gain at one or more stages (1-5) processing the data signal, in the data signal path at the transmitting end.

4. Method according to Claim 3, characterized in that the output power P_out needed in each case determines the stage or stages of the stages (1-5) processing the data signal at which a corresponding adjustment of the supply power Psu_ppi_y and/or gain is to be performed.

5. Method according to Claim 4, characterized in that due to the adjustments of the supply power P_SUppi and/or gain, in particular, amplifier stages (2, 4, 5) processing the data signal in the data signal path are in each case supplied only with the amount of power which is required for maintaining the back off from the 1-dB compression point.

6. Method according to Claim 3, characterized in that the supply power P_Su_pply ^anα^ the overall gain are adjusted in step-like manner in predetermined adjustment steps (d₀-d₄) .

7. Device for carrying out the method according to Claim 1.

8. Device according to Claim 7, characterized in that the device has in the data signal path at the transmitting end an amplifier (50-52) which processes the data signal and which is formed with an input stage (53) constructed as emitter follower circuit, an output stage (54) constructed as current mirror and a high-pass filter (C50, R50; C50 ' , R50 ' ) arranged in the data signal path between the input stage (53) and the output stage (54) .

9. Device according to Claim 8, characterized in that the high-pass filter (C50, R50; C50', R50 ' ) provides for mutually independent adjustment of the supply current and thus a mutually independent optimization of the linearity at the input stage (53) and at the output stage (54) .

10. Device according to Claim 9, characterized in that a first current source (I_DCI* I'DCI) is provided for the supply current adjustment of the input stage (53) and a second current source (I_Dc2 I'_DC2) is provided for the supply current adjustment of the output stage (54) .