WO2003025784A3 - Method of scheduling in a reconfigurable hardware architecture with multiple hardware configurations - Google Patents

Method of scheduling in a reconfigurable hardware architecture with multiple hardware configurations Download PDF

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Publication number
WO2003025784A3
WO2003025784A3 PCT/US2002/029479 US0229479W WO03025784A3 WO 2003025784 A3 WO2003025784 A3 WO 2003025784A3 US 0229479 W US0229479 W US 0229479W WO 03025784 A3 WO03025784 A3 WO 03025784A3
Authority
WO
WIPO (PCT)
Prior art keywords
scheduling
configurations
reconfigurable
architecture
hardware
Prior art date
Application number
PCT/US2002/029479
Other languages
French (fr)
Other versions
WO2003025784A2 (en
Inventor
Craig B Greenberg
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to JP2003529342A priority Critical patent/JP2005505030A/en
Priority to KR10-2003-7006945A priority patent/KR20040069257A/en
Priority to EP02775836A priority patent/EP1461698A2/en
Priority to AU2002341686A priority patent/AU2002341686A1/en
Publication of WO2003025784A2 publication Critical patent/WO2003025784A2/en
Publication of WO2003025784A3 publication Critical patent/WO2003025784A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/24—Loading of the microprogram

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Logic Circuits (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

A scheduler for a reconfigurable chip is described in which multiple configurations for single function are stored. The scheduler has the option of selecting any one of the configurations. The system increase the efficiency of the reconfiguration chips operation.
PCT/US2002/029479 2001-09-14 2002-09-16 Method of scheduling in a reconfigurable hardware architecture with multiple hardware configurations WO2003025784A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2003529342A JP2005505030A (en) 2001-09-14 2002-09-16 Scheduling method in reconfigurable hardware architecture having multiple hardware configurations
KR10-2003-7006945A KR20040069257A (en) 2001-09-14 2002-09-16 Method of scheduling in a reconfigurable hardware architecture with multiple hardware configurations
EP02775836A EP1461698A2 (en) 2001-09-14 2002-09-16 Method of scheduling in a reconfigurable hardware architecture with multiple hardware configurations
AU2002341686A AU2002341686A1 (en) 2001-09-14 2002-09-16 Method of scheduling in a reconfigurable hardware architecture with multiple hardware configurations

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/953,568 2001-09-14
US09/953,568 US20030056091A1 (en) 2001-09-14 2001-09-14 Method of scheduling in a reconfigurable hardware architecture with multiple hardware configurations

Publications (2)

Publication Number Publication Date
WO2003025784A2 WO2003025784A2 (en) 2003-03-27
WO2003025784A3 true WO2003025784A3 (en) 2004-07-01

Family

ID=25494199

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/029479 WO2003025784A2 (en) 2001-09-14 2002-09-16 Method of scheduling in a reconfigurable hardware architecture with multiple hardware configurations

Country Status (7)

Country Link
US (1) US20030056091A1 (en)
EP (1) EP1461698A2 (en)
JP (1) JP2005505030A (en)
KR (1) KR20040069257A (en)
CN (1) CN1568460A (en)
AU (1) AU2002341686A1 (en)
WO (1) WO2003025784A2 (en)

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US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
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US20040015899A1 (en) * 2000-10-06 2004-01-22 Frank May Method for processing data
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
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US7844796B2 (en) * 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7210129B2 (en) * 2001-08-16 2007-04-24 Pact Xpp Technologies Ag Method for translating programs for reconfigurable architectures
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US7996827B2 (en) * 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
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AU2003214003A1 (en) 2002-02-18 2003-09-09 Pact Xpp Technologies Ag Bus systems and method for reconfiguration
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
WO2004021176A2 (en) 2002-08-07 2004-03-11 Pact Xpp Technologies Ag Method and device for processing data
AU2003289844A1 (en) * 2002-09-06 2004-05-13 Pact Xpp Technologies Ag Reconfigurable sequencer structure
JP4665760B2 (en) * 2003-06-25 2011-04-06 日本電気株式会社 Electronic computer, semiconductor integrated circuit, control method, program generation method, and program
KR100731976B1 (en) * 2005-06-30 2007-06-25 전자부품연구원 Efficient reconfiguring method of a reconfigurable processor
GB0519981D0 (en) 2005-09-30 2005-11-09 Ignios Ltd Scheduling in a multicore architecture
JP4720436B2 (en) * 2005-11-01 2011-07-13 株式会社日立製作所 Reconfigurable processor or device
WO2007062327A2 (en) * 2005-11-18 2007-05-31 Ideal Industries, Inc. Releasable wire connector
JP2009524134A (en) 2006-01-18 2009-06-25 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト Hardware definition method
US8645955B2 (en) 2006-06-12 2014-02-04 Samsung Electronics Co., Ltd. Multitasking method and apparatus for reconfigurable array
KR100883655B1 (en) * 2006-12-04 2009-02-18 삼성전자주식회사 System and method for switching context in reconfigurable processor
KR100893527B1 (en) 2007-02-02 2009-04-17 삼성전자주식회사 Method of mapping and scheduling of reconfigurable multi-processor system
KR100940362B1 (en) 2007-09-28 2010-02-04 고려대학교 산학협력단 Method for mode set optimization in instruction processor using mode sets
KR101511273B1 (en) 2008-12-29 2015-04-10 삼성전자주식회사 System and method for 3d graphic rendering based on multi-core processor
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CN101853178B (en) * 2010-04-30 2012-07-04 西安交通大学 Description method of reconfigurable hardware resource in scheduling
CN103559154B (en) * 2013-11-06 2016-03-23 东南大学 The method of memory access time delay is hidden in a kind of reconfigurable system
JP6669961B2 (en) * 2015-12-24 2020-03-18 富士通株式会社 Processor, control method of reconfigurable circuit, and program
WO2018169911A1 (en) 2017-03-14 2018-09-20 Yuan Li Reconfigurable parallel processing
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Also Published As

Publication number Publication date
EP1461698A2 (en) 2004-09-29
CN1568460A (en) 2005-01-19
JP2005505030A (en) 2005-02-17
AU2002341686A1 (en) 2003-04-01
WO2003025784A2 (en) 2003-03-27
US20030056091A1 (en) 2003-03-20
KR20040069257A (en) 2004-08-05

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