WO2003024042A1

WO2003024042A1 - Method and apparatus for multiple resolution carrier offset recovery

Info

Publication number: WO2003024042A1
Application number: PCT/CA2002/001390
Authority: WO
Inventors: Octavian V. Sarca
Original assignee: Redline Communications Inc.
Priority date: 2001-09-13
Filing date: 2002-09-12
Publication date: 2003-03-20
Also published as: EP1428366A1

Abstract

A carrier offset recovery method and apparatus are provided that use a dual sequence has a period N=2n that is less than a second sequence having a period M=2m. The apparatus includes an error corrector circuit that combines the range from one offset estimation with the precision of the other. To obtain a very large range for the carrier offset one can employ one or more additional stages. For example, one can use a sequence with a period of P=2p samples where P<N. Offset estimation would be performed first on the P-sample sequence, then on the N-sample sequence and finally on the M-sample sequence.

Description

Method and Apparatus for Multiple Resolution Carrier Offset Recovery

Field of the Invention

The present invention relates to wireless communications systems and is particularly concerned with carrier offset recovery.

Background of the Invention

Most of the modern digital communication systems perform carrier-offset recovery in the digital domain using digital signal processing (DSP) techniques. With digital carrier offset recovery, the high-frequency signal is down-converted to baseband, sampled and quantized without having the receiver carrier frequency locked (equal to) to the transmitter carrier frequency.

The principle of this method is shown in Fig. 1. A numerically controlled oscillator (NCO) 18 is the digital equivalent of the voltage-controlled oscillator (VCO) in analog receivers with numeric input and output. Before demodulation, the digital signal is first analyzed to detect the carrier offset 14, which is the difference between the transmitter carrier frequency and the receiver carrier frequency. Then, the offset is compensated using the numerical controlled oscillator (NCO) 18 and a complex multiplier (MUL) 16. The NCO input is the desired frequency expressed as a fraction of the sampling rate. The number is typically represented as a fractional signed integer. The NCO output is typically a complex (quadrature) digital signal representing a sine wave with the desired frequency (either positive or negative).

To facilitate digital carrier offset recovery and other synchronization operations (i.e. automatic gain control, time synchronization, channel equalization) in the receiver, the transmitter appends a short training sequence at the beginning of each transmission, often called preamble. Many systems use periodic (repetitive) sequences as preambles because they can be easily generated and detected. The autocorrelation function of a sequence x(i) with a period of M samples, i.e. x(i+M) = x(i), will have maximums for every other M samples and, if there is no carrier frequency offset, the maximums are real numbers because x(i)-x*(i-k-M) = x(i)-x*(i) = |x(i)|² (x* denotes the complex conjugate of x). However, if a non-zero carrier offset is present the autocorrelation will produce a complex value with an angle A = 2-π-k-M-foFs/fcL , where fo_Fs is the carrier offset and fcu is the sampling rate. This is because

x₀(i)-x₀*(i-k-M) = x(i)-exp(j-2-π-i-f₀Fs/fcLi )-x*(i-k-M)-exp(-j-2-π- (i-k-M)-fo_Fs/fcL )

= |x(i)|²-expG-2-π-k-M-f_OFs/fcLκ)

This property is often used to derive the carrier offset and to compensate for it. Typical systems use the autocorrelation at M samples (k = 1) but other multiples can be used. For k = 1 , the angle A = 2-π- M-foFs fcLK divided by M can be directly programmed into the NCO to provide carrier offset recovery. To simplify the implementation, M is typically selected to be a power of 2, i.e. M = 2^m and then division by M becomes a simple shift to the right with m bits.

Fig. 2 illustrates the carrier offset recovery circuit that is typically used with preambles based on a repetitive sequence. The carrier offset recovery circuit of Fig. 2 shows detail of the carrier offset detection block 14. To carrier offset detection block

14 includes a second multiplier 20 coupled to the input 12 and a first delay 22 coupled between the input and of the multiplier. The output of second multiplier 20 is connected to a positive input to an adder 24 having a second positive input and in negative input. A second delay 26 is coupled from the output of second multiplier 20 to the second positive input of the adder 24. The output of adder 24 is applied to first register 28 whose output is applied to an angle block 30, a max detect block 36 and the negative input of the adder 24. The output of angle block 30 is applied to a division block 32 whose output is applied to second register 34 latched by the output of max detect block 36. The second register 34 has its output applied to the NCO 18. The period of the preamble sequence is assumed to be M = 2^m. DELI 22 and DEL2 26 are first-in-first-out (FIFO) delays of M samples. DELI 22 with the multiplier MUL2 20 compute the product x₀(i)-x₀*(i-M) while the adder SUM 24, the delay DEL2 26 and the register REG1 28 integrate the product over a running M- sample window to obtain the correlation function. The ANG block 30 extracts the angle and the DIV block 32 divides by M = 2^m. For M = 2^m the divider is a shift register that right shifts the input word with m bits. The maximum detection MAX 30 is used to enable writing the result of the division into the register REG2 34. REG2 34 is updated only once for every preamble. The value in REG2 34 is used then by the NCO 18 to correct the carrier frequency offset by multiplying (in MUL2 20) the input data with exp(-j-2-π-i-foFs/fcLκ)-

There is a certain tradeoff in choosing the period M of the training sequence. A large M provides better precision since the actual measured angle is multiplied by M. However, the angle function cannot distinguish angles A in a range larger than (-π,π) and thus unambiguous carrier offset recovery is possible only for offsets smaller than fcLκ/(2M): -f_CL /(2M) < f_0FS < (2M)

When carrier frequency is large in comparison with the clock frequency this tradeoff becomes a significant limitation of the digital carrier offset recovery.

Summary of the Invention

The present invention provides a method and apparatus that allows digital carrier offset recovery to achieve both range and precision. Accordingly the present invention provides a method that uses two or more repetitive sequences with different periods. As shown below, the sequences need not to be different, but different period sizes can be derived from the same sequence. However, the apparatus used to extract these sequences will be different. The description of the method and apparatus focuses first on the case of two sequences and then extends to multiple sequences. In accordance with an aspect of the present invention there is provided a method of carrier offset recovery comprising the steps of: determining a first carrier offset factor from a first sequence; determining a second carrier offset factor from a second sequence, different from the first; and deriving a carrier offset correction in dependence upon the first and second carrier offset factors.

In accordance with another aspect of the present invention there is provided an apparatus for carrier offset recovery comprising: means for determining a first carrier offset factor from a first sequence; means for determining a second carrier offset factor from a second sequence, different from the first; and means for deriviing a carrier offset correction in dependence upon the first and second carrier offset factors.

Brief Description of the Drawings

Fig. 1 illustrates a known canier offset recovery circuit;

Fig. 2 illustrates a known carrier offset recovery circuit of Fig. 1 with further detail of the carrier offset detection block;

Fig. 3 illustrates a carrier offset recovery circuit in accordance with an embodiment of the present invention; and

Fig. 4 illustrates the enor correction block of Fig. 3 in further detail.

Detailed Description of the Preferred Embodiment

With two periodic sequences, one will have a short period of N = 2ⁿ < M samples while the other one will have a long period of say M = 2^m samples. The sequences need not to be different since it is possible to use 2^m"n periods of the short sequence to obtain a period of the long sequence. It is known that the long sequence provides better resolution while the short sequence provides larger range. In the following we describe the apparatus needed to extract carrier offset from the two sequences and the apparatus to combine the two offset values produced by first apparatus.

Referring to Fig. 3 there is illustrated a carrier offset recovery circuit in accordance with an embodiment of the present invention. The carrier offset recovery circuit 100 of Fig. 3 includes an input 102, a carrier offset recovery circuit 104, a multiplier 106 and a numerical controlled oscillator NCO 108. The carrier offset recovery circuits 104 includes a second multiplier 110 connected to input 102, a first chain delay 112 having delay blocks 112 a and 112b coupled in series between input 102 and a first switch 116 at a first terminal with the first delay 112 also directly connected to the other terminal of first switch 116. The output of the first switch 116 is applied to the second multiplier 110. The output of the second multiplier 110 is applied to a positive input of an adder 120 having a second positive input and a negative input. A second delay chain 122 includes delays 122a and 122b connected from the multiplier 110 to a second switch 126 at a first terminal. Delay 122a is connected to a second terminal of second switch 126 whose output is connected to the second positive input of adder 120. The output of adder 120 is applied to register 128. The output of register 128 is input to an angle block 130 and a max detect block 136. The outputs of angle block 130 and max detect block 136 are applied to an error correction block 132, the output of which is applied to the NCO 108.

Each of the M-sample delays 112 and 122 (DELI and DEL2) are divided into one delay 112a and 122a of N samples (DELI a and DEL2a) and one delay 112b and 122b of M-N samples (DELlb and DEL2b). Two switches 116 and 126 (SW1 and SW2) are introduced to select between N-sample and M-sample delays. Fig. 3 shows the circuit for carrier offset recovery with dual-resolution. When compared to circuit in Fig. 2 this circuit has little added complexity.

The circuit operation is divided into two stages, one for the short sequence and one for the long sequence. During the first stage the switches are configured to use N- sample delays 112a and 122a. Once MAX detect 136 detects the maximum, the computed angle from angle block 130 is loaded into the error correction block 132, which divides the angle by N and outputs it to the NCO 108. Where N is the period of the short sequence and thus it provides the maximum range for carrier offset recovery. In the second stage, the switches 116 and 126 are toggled to provide M-sample delays 112b and 122b. When MAX detects 136 detects the maximum, the angle computed by block 130 is loaded into the error correction block 132. The error correction block 132 combines the results of the two offset estimations to provide an accurate and wide-range offset. The result is output to the NCO 108. The system operates similarly to a successive approximation analog to digital converter, where the first stage gives an approximate result, then the second gives a better approximation, and so on.

Hence, the error correction block 132 includes a first plurality of inputs 140

A(0). . . A(k - 1) and a second plurality of output 142 O(0). . . O(m + k + 1). The error correction block 132 includes a subtractor 150, an increment by one 152, an adder 154, MUX 156, and a register 158. The subtractor 150 has a second plurality of positive inputs 160 and a first plurality of negative inputs 162. The plurality outputs 142 and the plurality of inputs 140 coupled thereto, respectively. A third plurality of outputs of subtracters 150 are applied as input to the increment by one block 152 whose outputs are applied to the adder 154. The inputs 140 are also applied to the adder 154. The outputs of adder 154 are applied as inputs to the mux 156 along with the first plurality of inputs. The second plurality of the inputs from the mux 156 are applied to the register 158. The outputs of register 158 are applied to the output 142.

A key part of the operation of the carrier offset recovery with dual-resolution is the error correction circuit 132 (ERCOR), which combines the range from one offset estimation with the precision of the second. Signals A(i) with i = 0, ..., k-1 at inputs 140 encode the angle using fractional signed integer format as output by ANG block 130 on k bits. A(0) is the least significant bit (LSB) and A(k-l) is the most significant bit (MSB). The register 158 signals O(i) with i = 0, ..., m+k-1 that encode the frequency in fractional signed integer format as required by the NCO 108. O(0) is the LSB and O(m+k-l) is the MSB. The error correction circuit 132 consists in one substractor (SUBS) 150, one incrementer (INC) 152, one adder (ADD) 154, one multiplexer (MUX) 156 and one register (REG) 158. During the first stage, the MUX 156 is configured to input la. Thus, when maximum is detected, the corresponding angle is written directly into REG 158. During the second stage the MUX 156 is configured to input lb. When maximum is again detected, the new angle value and the previous frequency estimate are combined in SUBS 150 and INC 152 to produce the correction term. The correction term is finally added in ADD 154 to the new angle value to provide the new frequency offset estimate.

Note that the division by N = 2" required for the first stage is performed at the la input into MUX and that the division by M = 2^m required for the second stage is performed at the '-' input into SUBS.

Recall that the shorter the period the less precise is the carrier offset estimation. Therefore, the difference between m and n must not be larger than 2-3 to allow the error correction circuit operate properly. To obtain a very large range for the carrier offset we can employ one or more additional stages. For example, we can use a sequence with a period of P = 2^P samples where P < N. Offset estimation would be performed first on the P-sample sequence, then on the N-sample sequence and finally on the M-sample sequence. For the circuit in Fig. 3 changes would be minimal. Each of DELI a and DEL2a, delaying now N-samples will be split into one delay of P- samples and one delay of N-P samples. Accordingly, switches 116 and 126 (SW1 and SW2) would have three positions instead of two and MAX will have to detect three maximums. For the circuit of Fig. 4, MUX 156 would have three inputs instead of two. Also, SUBS, INC and ADD would be doubled: one branch would combine the result from the P-sample and N-sample angle estimates and the other branch will combine this intermediate result with the M-sample angle estimate.

Claims

What is claimed is:

1. A method of carrier offset recovery comprising the steps of:

determining a first carrier offset factor from a first sequence;

determining a second carrier offset factor from a second sequence, different from the first; and

deriving a carrier offset correction in dependence upon the first and second carrier offset factors.

2. A method as claimed in claim 1 wherein the first sequence is less than the second sequence.

3. A method as claimed in claim 1 wherein the first sequence has a period N=2ⁿ.

4. A method as claimed in claim 1 wherein the second sequence has a period M=2^r

5. Apparatus for carrier offset recovery comprising:

means for determining a first carrier offset factor from a first sequence;

means for determining a second carrier offset factor from a second sequence, different from the first; and

means for deriviing a carrier offset correction in dependence upon the first and second carrier offset factors.

6. A method as claimed in claim 5 wherein the first sequence is less than the second sequence.

7. A method as claimed in claim 5 wherein the first sequence has a period N=2ⁿ.

A method as claimed in claim 5 wherein the second sequence has a period M=2"