WO2003013051A3 - Timing recovery in data communication circuits - Google Patents

Timing recovery in data communication circuits Download PDF

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Publication number
WO2003013051A3
WO2003013051A3 PCT/IE2002/000114 IE0200114W WO03013051A3 WO 2003013051 A3 WO2003013051 A3 WO 2003013051A3 IE 0200114 W IE0200114 W IE 0200114W WO 03013051 A3 WO03013051 A3 WO 03013051A3
Authority
WO
WIPO (PCT)
Prior art keywords
timing recovery
decision
data communication
communication circuits
ted
Prior art date
Application number
PCT/IE2002/000114
Other languages
French (fr)
Other versions
WO2003013051A2 (en
Inventor
Carl Damien Murray
Philip Curran
Navarro Alberto Molina
Original Assignee
Massana Res Ltd
Carl Damien Murray
Philip Curran
Navarro Alberto Molina
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Massana Res Ltd, Carl Damien Murray, Philip Curran, Navarro Alberto Molina filed Critical Massana Res Ltd
Publication of WO2003013051A2 publication Critical patent/WO2003013051A2/en
Publication of WO2003013051A3 publication Critical patent/WO2003013051A3/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H04L7/0062—Detection of the synchronisation error by features other than the received signal transition detection of error based on data decision error, e.g. Mueller type detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/403—Bus networks with centralised control, e.g. polling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0004—Initialisation of the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0334—Processing of samples having at least three levels, e.g. soft decisions
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L2025/03433—Arrangements for removing intersymbol interference characterised by equaliser structure
    • H04L2025/03439—Fixed structures
    • H04L2025/03445—Time domain
    • H04L2025/03471—Tapped delay lines
    • H04L2025/03477—Tapped delay lines not time-recursive
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0334—Processing of samples having at least three levels, e.g. soft decisions
    • H04L7/0335—Gardner detector

Abstract

In a 1 OOOBASE- T transceiver, a timing error detector (TED, 5) receives its inputs directly from the output of an ADC (2) and from a decision device (4). Timing recovery is acquired in three stages: a non-decision directed (NDD) stage during which only the output of an ADC (2) are used for acquisition; a stage for acquiring the remote scrambler and predicting symbols; and a decision-directed (DD) stage during which locally predicted symbols are also used for acquisition. Because the timing error detector (TED, 5) does not take inputs from the FFE (3) there is no information about cable length, and so an input of gain from an AGC is used to indicate cable length.
PCT/IE2002/000114 2001-08-02 2002-07-31 Timing recovery in data communication circuits WO2003013051A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US30916401P 2001-08-02 2001-08-02
IE20010739 2001-08-02
US60/309,164 2001-08-02
IE2001/0739 2001-08-02

Publications (2)

Publication Number Publication Date
WO2003013051A2 WO2003013051A2 (en) 2003-02-13
WO2003013051A3 true WO2003013051A3 (en) 2003-11-27

Family

ID=26320332

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IE2002/000114 WO2003013051A2 (en) 2001-08-02 2002-07-31 Timing recovery in data communication circuits

Country Status (1)

Country Link
WO (1) WO2003013051A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7930127B2 (en) * 2008-11-11 2011-04-19 Nxp B.V. Oscillator prescale calibration for harmonizing multiple devices with independent oscillators over an I2C bus interface
US8224602B2 (en) 2008-11-11 2012-07-17 Nxp B.V. Automatic on-demand prescale calibration across multiple devices with independent oscillators over an I2C Bus interface

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09130443A (en) * 1995-10-31 1997-05-16 Toshiba Corp Digital demodulator

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09130443A (en) * 1995-10-31 1997-05-16 Toshiba Corp Digital demodulator

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1997, no. 09 30 September 1997 (1997-09-30) *
UNGERBOECK G: "DECISION DIRECTED METHOD FOR TIMING RECOVERY IN PAM DATA SIGNAL RECEIVERS", IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, vol. 18, no. 3, August 1975 (1975-08-01), pages 769 - 771, XP000808453, ISSN: 0018-8689 *

Also Published As

Publication number Publication date
WO2003013051A2 (en) 2003-02-13

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