WO2003010616A1

WO2003010616A1 - Mos integrated circuit with current mirror

Info

Publication number: WO2003010616A1
Application number: PCT/JP2002/006970
Authority: WO
Inventors: Munehiro Karasudani
Original assignee: Niigata Seimitsu Co., Ltd.
Priority date: 2001-07-23
Filing date: 2002-07-10
Publication date: 2003-02-06
Also published as: JP2003037456A

Abstract

An MOS integrated circuit equipped with a current mirror comprising pMOS transistors (Tr1, Tr2) arranged closely to each other. Wiring length of each transistor (Tr1, Tr2) is shortened by extending the drain line of each transistor (Tr1, Tr2) to a desired position so that a distributed resistance being generated on a source line (12) can be reduced to a negligible level thus suppressing voltage drop on the source line (12) and eliminating uneven source potential.

Description

Description of MOS Integrated Circuit Technology with Current Mirror ^

The present invention relates to a MOS integrated circuit having a current mirror. Background art

Technologies for manufacturing semiconductor devices include Si (silicon) bipolar technology, compound semiconductor GaAs (gallium arsenide) technology, and CMOS technology. Among them, CMOS technology has features such as low power consumption, low voltage operation, high-speed operation with miniaturization, and low manufacturing cost. Mostly adopted.

Among them, the RF (Radio Frequency) circuit (analog circuit section) that receives and processes high-frequency signals often uses bipolar technology or GaAs technology. Technology was rarely used. This is because the CMOS technology is mainly suitable for digital circuits, and the SMOS cannot obtain good and sufficient high-frequency characteristics in the CMOS circuit.

However, in recent years, semiconductor chips for the short-distance wireless data communication technology bluetooth II and wireless LAN using the 5 GHz band, which have introduced CMOS technology, have appeared. This is because, unlike mobile phones, etc., where voice calls are the highest priority, Bluetooth and wireless LANs are mainly for data communication, so the reference values of the characteristics required for the RF circuit are more relaxed than those of mobile phones, etc. It depends. However, if CMOS technology is improved in the future, it is expected that CMOS technology will be introduced to mobile phones and other devices.

On the other hand, the most basic and important circuit used in integrated circuits is a current mirror circuit. Figure 1 shows the basic circuit of a power mirror constructed using the CMOS technology. The current mirror circuit shown in FIG. 1, p MO S transistor T r 1 to flow a reference current I, and the current 1 ₂ is equal, a circuit for supplying the p MO S transistor T r 2 in the independent potentials FIG In FIG. 1, the pMOS transistor Trl has a so-called diode connection in which the source and the gate are connected. p M〇 S Transistor The source of Tr 1 is connected to the power supply VDD, and the drain is grounded via the resistor R. Another pMOS transistor Tr2, which forms a current mirror together with the pMOS transistor Tr1, has a source connected to the power supply VDD, a drain connected to a desired position, and a gate connected to the pMOS transistor Trl. Connected to the gate of r1.

The current mirror circuit is written as a circuit diagram as shown in Fig. 1, but when actually laying out on a semiconductor chip, the current mirror circuit arrangement often has to be separated as shown in Fig. 2. . Conventionally, in this case, each transistor T rl, Tr 2 itself is arranged at a required position on the layout, and another power supply VDD is connected to the source of each transistor T rl, Tr 2. Was.

In this case, the wires 11 and 12 between the gates of the transistors Tr 1 and Tr 2 and between the sources are elongated long. However, if the source line 12 to which the power supply VDD is connected is elongated, a distributed resistance is generated on the source line 12. In particular, when laying out a current mirror circuit as shown in Fig. 2 in an RF circuit that handles high-frequency signals, the source line The resistance value generated on 12 increases. As a result, a voltage drop occurs due to the resistance, and the source potentials are not uniform between the transistors Tr 1 and Tr 2.

As a result, the balance of the current mirror is lost, and the current 12 flowing through the transistor Tr ₂ cannot be made equal to the reference current I flowing through the transistor Tr 1. This is a factor that degrades the operation performance of the circuit. In particular, in order to improve the high-frequency characteristics of RF circuits in mobile phones and the like, it is desirable to eliminate such errors of the current mirror as much as possible.

The present invention has been made to solve such a problem, and keeps the current mirror in good balance even when the circuit arrangement of the current mirror is far away from the chip layout. The purpose is to be able to Disclosure of the invention

In a MOS integrated circuit having a current mirror according to the present invention, a plurality of MOS transistor elements constituting a current mirror are arranged close to each other, and a signal line connected to a drain of the plurality of MOS transistor elements is provided as desired. It is characterized by wiring to the position.

Another embodiment of the present invention is characterized in that the sources of the plurality of MOS transistor elements are commonly connected to the same power supply.

According to another aspect of the present invention, an amplifier circuit in which a differential amplifier that amplifies an input signal from a previous stage and outputs the amplified signal to the next stage is connected in multiple stages, and is commonly connected to the plurality of differential amplifiers connected in multiple stages. A plurality of MOS transistors connected between the plurality of differential amplifiers and the constant current source circuit, and a plurality of current mirror circuits each including a plurality of MOS transistors. And the signal lines connected to the drains of the plurality of MOS transistor elements are routed to the positions of the plurality of differential amplifiers, respectively. .

Since the present invention comprises the above technical means, the source wiring length between a plurality of M〇S transistor elements constituting the current mirror circuit is shortened, and the distributed resistance and the voltage drop generated on the distribution line can be minimized. Becomes BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a diagram showing a configuration example of a general current mirror circuit.

FIG. 2 is a diagram showing an example of a layout of a conventional current mirror circuit.

FIG. 3 is a diagram showing an example of a layout configuration of the current mirror circuit according to the present embodiment on a CMOS integrated circuit.

FIG. 4 is a diagram showing another example of the layout of the current mirror circuit according to the present embodiment on a CMOS integrated circuit.

FIG. 5 is a diagram showing a configuration example of a multistage amplifier to which the current mirror circuit of the present embodiment is applied. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a diagram showing an example of a layout of a current mirror circuit according to the present embodiment on a CMOS integrated circuit. Karen Tomi error circuit shown in FIG. 3, p MO S transistor T r 1 to flow a reference current I, and the current 1 ₂ is equal, is a circuit for supplying the P MO S transistor T r 2 in the independent potential . In FIG. 3, the pMOS transistor Trl has a so-called diode connection in which the source and the gate are connected. The gate of this pMOS transistor Tr1 is connected to the gate of the other PM〇S transistor Tr2 that forms a current mirror together with the pMOS transistor Tr1.

The sources of the pair of pMOS transistors Trl and Tr2 are connected in common to the same power supply VDD via a common node A which is approximately the same distance from each transistor Tr1 and Tr2. I have. The drain of the pMOS transistor Tr1 is grounded via the resistor R, and the drain of the pMOS transistor Tr2 is connected to a desired position.

As shown in FIG. 3, in the present embodiment, a pair of pMOS transistors Tr 1 and Tr 2 constituting a current mirror are arranged close to each other and connected to the drain of the transistor Tr 2 The signal line (drain line) 10 is extended to a desired position for wiring.

Since the pair of pMOS transistors Tr1 and Tr2 are located close to each other, the signal line between the gates (gate line) 11 and the signal line between the sources (source line) 12 must be shortened. Can be. As a result, the distributed resistance generated on the source line 12 can be reduced to a negligible level, and a voltage drop on the source line 12 can be suppressed.

Moreover, in the present embodiment, the sources of the transistors Trl, Tr2 are commonly connected to the same power supply VDD via the common node A located at substantially the same distance. The two source potentials can be made almost exactly the same magnitude. Therefore, it is possible to eliminate irregularities in the source potentials of the transistors Tr 1 and Tr 2 and to maintain a good current mirror balance.

FIG. 4 shows the current mirror circuit according to the present embodiment on a CMOS integrated circuit. FIG. 8 is a diagram illustrating another example of a layout configuration in FIG. Karen Tomi error circuit shown in FIG. 4, reference current I flowing through the p MOS transistor T r 1, with an equal correct the current I _2, I _3> 1 _4, each P MO S transistor T r 2~T r 4 It is a circuit for flowing.

In the circuit shown in FIG. 4, the so-called diode-coupled pMOS transistor Tr1 in which the source and the gate are connected to each other and three other pMOS transistors Tr2 to Tr4 are three. A pair of current mirror circuits (three pairs of pMOS transistors Tr1 are also used) is configured.

In the current mirror circuit in this case, the gate of the pMOS transistor Tr1 and the gates of the other three pMOS transistors Tr2 to Tr4 are connected to each other. The sources of the pMOS transistors Tr1 to Tr4 are commonly connected to the same power supply VDD via a common node B.

The drain of the pMOS transistor Tr1 is grounded via the resistor R, and the drains of the other three pMOS transistors Tr2 to Tr4 are connected to desired positions.

As shown in FIG. 4, three pairs of pMOS transistors Trl to Tr4 constituting the current mirror are arranged close to each other and connected to the drains of transistors Tr2 to Tr4. Each of the drain lines 10 is extended to a desired position for wiring.

Also in this case, the wiring length of the source line 12 connecting the three pairs of pMOS transistors Trl to Tr4 can be reduced. Thus, the distributed resistance generated on the source line 12 can be reduced to a negligible level, and the voltage drop on the source line 12 can be suppressed. As described above, in the present embodiment, even if the number of transistors constituting the current mirror circuit is increased, the irregularities in the source potential are eliminated and the current mirror circuit is reduced. Can be kept in a good balance.

FIG. 5 is a diagram illustrating an application example of the above-described current mirror circuit. Here, for example, the configuration of a multi-stage amplifier applied to various wireless communication devices such as AM or FM radio receivers, television receivers, mobile phones, short-range wireless data communication technology bluetooth, and wireless LANs. Is shown. In FIG. 5, components having the same functions as the components shown in FIG. 4 are denoted by the same reference numerals.

The multistage amplifier shown in Fig. 5 is composed of n stages of differential amplifiers connected in multiple stages from the input side to the output side. First-stage differential amplifier circuit arranged in the input stage is configured to include two resistors R _n, R ₁₂ and two p MO S transistor Q _n, a differential pair consisting of Q ₁₂ Metropolitan. The second-stage differential amplifier is configured to include a differential pair including _two transistors R ₂₁ and R ₂₂ and two pMOS transistors Q _{2 and} Q ₂₂ as in the first-stage. . The third to n-th stages (not shown) have the same configuration.

In each differential pair, drain of each transistor Q i have Q 12 (i = l~! 1 ) are grounded via resistor R _M, the R _i2. Each preparative Rungis evening Q _n, the gate of Q _i2, except for the first stage of the differential amplifier, the output signal from the preceding stage of the differential amplifier is input. Each Trang register Q _n of the first stage of the differential amplifier, Q, to the _second gate, the small signal before amplification is input.

Also, in each differential pair, the sources of the two transistors Q; Q _i2 are commonly connected to each other, and these common sources are connected to the _pMOS transistors Tr 2, Tr 3, Tr 4 ,… Drains are connected. In this case, the pMOS transistors Tr2, Ti-3, Tr4, ... function as switching elements of each differential pair.

Another pMOS transistor Tr1 that forms a current mirror circuit together with each transistor Tr2, Tr3, Tr4,... Are grounded via a resistor R, and the source is connected to one end of the constant current source circuit 30. The other end of the constant current source circuit 30 is connected to the power supply VDD. Each differential pair has the same current I as flowing through the constant current source circuit 30 through the pMOS transistor Tf2, Tr3, Tr4, ... composed of a current mirror circuit. I ₂ , I ₃ , I ₄ > are supplied respectively.

In the multistage amplifier configured as described above, the signal input to the bases of the transistors Q 1, Q 2, and Q ₁₂ of the first-stage differential amplifier is amplified by a predetermined level and output. The signal amplified and output here is input to the bases of the transistors Q _{2 and} Q ₂₂ of the second-stage differential amplifier, and further amplified and output by the second-stage differential amplifier. Is done. Similarly, the signals are sequentially amplified by the differential amplifiers at each stage. As a result, the amplitude of the input signal to the first-stage differential amplifier increases in the subsequent stage, and finally an output signal amplified to a predetermined level is obtained.

In the multi-stage amplifier configured as described above, the pMOS transistors Tr:! To Tr4 that constitute the current mirror are arranged close to each other and connected to the drains of the transistors Tr2 to Tr4. The drain line 10 is extended to the position of the differential pair in each stage and wired. Therefore, the source line 12 connecting the transistors Tr 1 to Tr 4 can be shortened.

As a result, the distributed resistance generated on the source line 12 can be reduced to a negligible level, and the voltage drop on the source line 12 can be suppressed. Therefore, it is possible to maintain a good balance of the current mirror by eliminating irregularities in the source potentials at each of the transistors 1 to 1 to 4 so that the current mirror circuit having such characteristics can be used in a wireless communication device. When applied to multi-stage amplifiers, good input / output characteristics The linearity can be ensured. In addition, since the wiring length from each of the transistors Tr 1 to Tr 4 to the power supply VDD and the constant current source circuit 30 is short, it is necessary to reduce the impedance of the connection between the transistors and realize low-noise power supply. The operation can be stabilized even when handling high-frequency signals.

In the above-described embodiment, a PMOS transistor is used as a transistor element constituting the current mirror circuit. However, it goes without saying that an nMOS transistor may be used.

Further, the number of the transistor elements constituting the current mirror circuit shown in the above embodiment is merely an example, and the present invention is not limited to this.

In addition, FIG. 5 shows a multistage amplifier as an application example of a current mirror circuit, but the present invention is not limited to this, and any application using a current mirror circuit is possible.

In addition, the above-described embodiments are merely examples of embodying the present invention, and the technical scope of the present invention should not be interpreted in a limited manner. is there. That is, the present invention can be embodied in various forms without departing from its spirit or its main features.

As described above, in the present invention, a plurality of MOS transistors constituting a current mirror are arranged close to each other, and a signal line connected to the drains of the plurality of MOS transistors is moved to a desired position. Since the wiring is used, the wiring length of the signal line connecting the source of each MOS transistor and element can be shortened. As a result, the distributed resistance generated on the source line can be reduced to a negligible level, so that the voltage drop on the source line is suppressed and the source resistance of each MOS transistor is reduced. The difference between the potentials can be prevented. Therefore, even when the circuit arrangement of the current mirror is far away from the chip layout, the current mirror can be well balanced. In particular, when the current mirror circuit of the present invention is applied to an RF circuit such as a mobile phone, the high-frequency characteristics can be improved.

According to another feature of the present invention, the sources of a plurality of MOS transistor elements are commonly connected to the same power supply, so that the source potential of each MOS transistor can be more accurately aligned. Thus, the balance of the current mirror can be better maintained. Industrial applicability

INDUSTRIAL APPLICABILITY The present invention is useful for a MOS integrated circuit capable of maintaining a good balance of a current mirror even when the circuit arrangement of the power mirror is far away from the chip layout.

Claims

The scope of the claims

1. A plurality of MOS transistors constituting a current mirror are arranged close to each other, and a signal line connected to the drains of the plurality of MOS transistors is routed to a desired position. MOS integrated circuit with a current mirror.

2. The MOS integrated circuit having a current mirror according to claim 1, wherein the sources of the plurality of MOS transistor elements are commonly connected to the same power supply. .

3. An amplifier circuit consisting of multiple stages of differential amplifiers that amplify the input signal from the previous stage and output it to the next stage;

A constant current source circuit commonly connected to the plurality of multistage connected differential amplifiers;

A current mirror circuit comprising a plurality of MOS transistor elements connected between the plurality of differential amplifiers and the constant current source circuit, wherein the plurality of MOS transistor elements are arranged close to each other; A MOS integrated circuit having a current mirror, wherein the signal lines connected to the drains of the plurality of MOS transistor elements are respectively routed to the positions of the plurality of differential amplifiers.