WO2003010550A3 - Integrated testing of serializer/deserializer in fpga - Google Patents

Integrated testing of serializer/deserializer in fpga Download PDF

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Publication number
WO2003010550A3
WO2003010550A3 PCT/US2002/017532 US0217532W WO03010550A3 WO 2003010550 A3 WO2003010550 A3 WO 2003010550A3 US 0217532 W US0217532 W US 0217532W WO 03010550 A3 WO03010550 A3 WO 03010550A3
Authority
WO
WIPO (PCT)
Prior art keywords
serdes
test
fpga
testing
circuit
Prior art date
Application number
PCT/US2002/017532
Other languages
French (fr)
Other versions
WO2003010550A2 (en
Inventor
Austin H Lesea
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xilinx Inc filed Critical Xilinx Inc
Priority to EP02737351A priority Critical patent/EP1410053B1/en
Priority to CA002453601A priority patent/CA2453601C/en
Priority to JP2003515867A priority patent/JP4056469B2/en
Priority to DE60205118T priority patent/DE60205118T2/en
Publication of WO2003010550A2 publication Critical patent/WO2003010550A2/en
Publication of WO2003010550A3 publication Critical patent/WO2003010550A3/en

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31715—Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation

Abstract

A field programmable gate array (FPGA) device (200) includes a high-speed serializer/deserializer (SERDES) (202). The field programmable gate array allows programmable built-in testing of the SERDES at operating speeds. A digital clock manager circuit (212) allows clock signals coupled to the SERDES to be modified durring the test operations to stress the SERDES circuit. The logic array (210) of the FPGA can be programmed to generate test patterns and to analyze data received by the SERDES circuit. Cyclic redundancy check (CRC) (232) characters, or other error checking characters, can also be generated using the logic array. During testing, the FPGA can perform extensive tests on the communication circuitry and store the results of the testing. An external tester (300) can read the results of the test without substantial test time or complicated test equipment. After testing is complete, the device may be re-programmed to perform the end-user function adding zero cost to the device for test implementation.
PCT/US2002/017532 2001-07-24 2002-05-30 Integrated testing of serializer/deserializer in fpga WO2003010550A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP02737351A EP1410053B1 (en) 2001-07-24 2002-05-30 Integrated testing of serializer/deserializer in fpga
CA002453601A CA2453601C (en) 2001-07-24 2002-05-30 Integrated testing of serializer/deserializer in fpga
JP2003515867A JP4056469B2 (en) 2001-07-24 2002-05-30 Integrated test of serializer / deserializer in FPGA
DE60205118T DE60205118T2 (en) 2001-07-24 2002-05-30 INTEGRATED INSPECTION OF A SERIALIZER / DESERIALIZER IN FPGA

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/912,683 2001-07-24
US09/912,683 US6874107B2 (en) 2001-07-24 2001-07-24 Integrated testing of serializer/deserializer in FPGA

Publications (2)

Publication Number Publication Date
WO2003010550A2 WO2003010550A2 (en) 2003-02-06
WO2003010550A3 true WO2003010550A3 (en) 2003-05-15

Family

ID=25432268

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/017532 WO2003010550A2 (en) 2001-07-24 2002-05-30 Integrated testing of serializer/deserializer in fpga

Country Status (6)

Country Link
US (1) US6874107B2 (en)
EP (1) EP1410053B1 (en)
JP (1) JP4056469B2 (en)
CA (1) CA2453601C (en)
DE (1) DE60205118T2 (en)
WO (1) WO2003010550A2 (en)

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Also Published As

Publication number Publication date
CA2453601A1 (en) 2003-02-06
EP1410053A2 (en) 2004-04-21
CA2453601C (en) 2007-08-21
WO2003010550A2 (en) 2003-02-06
US6874107B2 (en) 2005-03-29
DE60205118T2 (en) 2006-05-24
JP2004537054A (en) 2004-12-09
DE60205118D1 (en) 2005-08-25
US20030023912A1 (en) 2003-01-30
EP1410053B1 (en) 2005-07-20
JP4056469B2 (en) 2008-03-05

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