WO2003009372A3 - Low resistivity tantalum nitride/tantalum bilayer stack - Google Patents

Low resistivity tantalum nitride/tantalum bilayer stack Download PDF

Info

Publication number
WO2003009372A3
WO2003009372A3 PCT/US2002/018988 US0218988W WO03009372A3 WO 2003009372 A3 WO2003009372 A3 WO 2003009372A3 US 0218988 W US0218988 W US 0218988W WO 03009372 A3 WO03009372 A3 WO 03009372A3
Authority
WO
WIPO (PCT)
Prior art keywords
tantalum
low resistivity
layer
bilayer stack
tantalum nitride
Prior art date
Application number
PCT/US2002/018988
Other languages
French (fr)
Other versions
WO2003009372A2 (en
Inventor
Suraj Rengarajan
Michael A Miller
Peijun Ding
Tony P Chiang
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of WO2003009372A2 publication Critical patent/WO2003009372A2/en
Publication of WO2003009372A3 publication Critical patent/WO2003009372A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Physical Vapour Deposition (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

Provided herein is a method of forming a low resistivity tantalum nitride/tantalum bilayer stack at a low temperature, comprising the steps of depositing a tantalum nitride layer on a dielectric layer; and depositing a tantalum layer over the tantalum nitride layer such that the tantalum layer deposited at the low temperature comprises alpha phase tantalum thereby forming a low resistivity bilayer stack. Also provided is a method of forming a copper barrier and seed layer on a semiconductor wafer by the methods disclosed herein.
PCT/US2002/018988 2001-07-20 2002-06-17 Low resistivity tantalum nitride/tantalum bilayer stack WO2003009372A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US30669801P 2001-07-20 2001-07-20
US60/306,698 2001-07-20

Publications (2)

Publication Number Publication Date
WO2003009372A2 WO2003009372A2 (en) 2003-01-30
WO2003009372A3 true WO2003009372A3 (en) 2003-10-16

Family

ID=23186451

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/018988 WO2003009372A2 (en) 2001-07-20 2002-06-17 Low resistivity tantalum nitride/tantalum bilayer stack

Country Status (1)

Country Link
WO (1) WO2003009372A2 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5281485A (en) * 1990-10-26 1994-01-25 International Business Machines Corporation Structure and method of making Alpha-Ta in thin films
EP0751566A2 (en) * 1995-06-30 1997-01-02 International Business Machines Corporation A thin film metal barrier for electrical interconnections
US6110598A (en) * 1995-05-31 2000-08-29 Nec Corporation Low resistive tantalum thin film structure and method for forming the same
WO2000070664A1 (en) * 1999-05-17 2000-11-23 Infineon Technologies Ag Method for depositing a two-layer diffusion barrier
WO2002065547A2 (en) * 2001-01-31 2002-08-22 Applied Materials, Inc. METHOD OF OBTAINING LOW TEMPERATURE ALPHA-Ta THIN FILMS USING WAFER BIAS

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5281485A (en) * 1990-10-26 1994-01-25 International Business Machines Corporation Structure and method of making Alpha-Ta in thin films
US6110598A (en) * 1995-05-31 2000-08-29 Nec Corporation Low resistive tantalum thin film structure and method for forming the same
EP0751566A2 (en) * 1995-06-30 1997-01-02 International Business Machines Corporation A thin film metal barrier for electrical interconnections
WO2000070664A1 (en) * 1999-05-17 2000-11-23 Infineon Technologies Ag Method for depositing a two-layer diffusion barrier
WO2002065547A2 (en) * 2001-01-31 2002-08-22 Applied Materials, Inc. METHOD OF OBTAINING LOW TEMPERATURE ALPHA-Ta THIN FILMS USING WAFER BIAS

Also Published As

Publication number Publication date
WO2003009372A2 (en) 2003-01-30

Similar Documents

Publication Publication Date Title
US6028000A (en) Method of forming contact plugs in semiconductor device having different sized contact holes
TWI334220B (en) Mim capacitor integrated into the damascens structure and method of making thereof
WO2003028091A3 (en) Copper interconnect barrier layer structure and formation method
WO2002069380A3 (en) Atomically thin highly resistive barrier layer in a copper via
JPH10284603A (en) Continuous highly conductive metal wiring and manufacture therefor
WO2007084982A2 (en) Dual-damascene process to fabricate thick wire structure
WO2002073689A3 (en) Integrated barrier layer structure for copper contact level metallization
EP1201786A3 (en) Seed layer deposition
WO2003015130A3 (en) Integrated system for oxide etching and metal liner deposition
EP1186685A3 (en) Method for forming silicon carbide films
US20030203615A1 (en) Method for depositing barrier layers in an opening
US20010043136A1 (en) Lateral high-Q inductor for semiconductor devices
US6187647B1 (en) Method of manufacturing lateral high-Q inductor for semiconductor devices
EP1267405A3 (en) Semiconductor device and method for fabricating the same
WO2002093648A3 (en) Semiconductor device interconnect
JPH07221181A (en) Formation of metal wiring of semiconductor element
JP2000021873A (en) Laminate structure, wiring structure and their manufacture, and semiconductor device
US6204096B1 (en) Method for reducing critical dimension of dual damascene process using spin-on-glass process
WO2003009372A3 (en) Low resistivity tantalum nitride/tantalum bilayer stack
WO2002065547A3 (en) METHOD OF OBTAINING LOW TEMPERATURE ALPHA-Ta THIN FILMS USING WAFER BIAS
WO2002041391A3 (en) Amorphized barrier layer for integrated circuit interconnects
JP2001053151A (en) Semiconductor integrated circuit device and manufacturing method of the same
KR100193897B1 (en) Plug formation method of semiconductor device
JP2000232106A (en) Semiconductor device and manufacture of semiconductor device
JP2003243498A (en) Semiconductor element and its manufacturing method

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): CN JP KR

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP

DPE2 Request for preliminary examination filed before expiration of 19th month from priority date (pct application filed from 20040101)