WO2003005782A3 - Stackable microcircuit and method of making the same - Google Patents

Stackable microcircuit and method of making the same Download PDF

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Publication number
WO2003005782A3
WO2003005782A3 PCT/US2002/021101 US0221101W WO03005782A3 WO 2003005782 A3 WO2003005782 A3 WO 2003005782A3 US 0221101 W US0221101 W US 0221101W WO 03005782 A3 WO03005782 A3 WO 03005782A3
Authority
WO
WIPO (PCT)
Prior art keywords
neo
dies
die
layer
pem
Prior art date
Application number
PCT/US2002/021101
Other languages
French (fr)
Other versions
WO2003005782A2 (en
Inventor
Lawrence D Andrews
Douglas M Albert
Original Assignee
Irvine Sensors Corp
Lawrence D Andrews
Douglas M Albert
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Irvine Sensors Corp, Lawrence D Andrews, Douglas M Albert filed Critical Irvine Sensors Corp
Publication of WO2003005782A2 publication Critical patent/WO2003005782A2/en
Publication of WO2003005782A3 publication Critical patent/WO2003005782A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
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    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2225/1047—Details of electrical connections between containers
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

A Neo layer (107, 285) is provided with at least one die (10) having a microelectronic device on an active surface (55) of the die (10). The dies (10) are supported on a support substrate (105, 300) that can be readily handled by machines in an automated manufacturing setting. Both of the die (10) and the substrate (105, 300) are encapsulated in a layer material to provide a distinctive Neo layer or Neo PEM. The different embodiments offer additional respective advantages of improved manufacturability. Further versatility is provided by enabling use of dies (10) from different sources including bare dies (10) and dies (10) that are already packaged in a Plastic Embedded Microcircuit (PEM), for example. The ongoing goal of providing a stackable array of Neo layers (107, 285) is still met.
PCT/US2002/021101 2001-07-02 2002-07-02 Stackable microcircuit and method of making the same WO2003005782A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US30230601P 2001-07-02 2001-07-02
US60/302,306 2001-07-02

Publications (2)

Publication Number Publication Date
WO2003005782A2 WO2003005782A2 (en) 2003-01-16
WO2003005782A3 true WO2003005782A3 (en) 2003-08-28

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PCT/US2002/021101 WO2003005782A2 (en) 2001-07-02 2002-07-02 Stackable microcircuit and method of making the same

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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7198965B2 (en) * 2002-11-06 2007-04-03 Irvine Sensors Corp. Method for making a neo-layer comprising embedded discrete components
EP1724835A1 (en) * 2005-05-17 2006-11-22 Irvine Sensors Corporation Electronic module comprising a layer containing integrated circuit die and a method for making the same
DE102005041640A1 (en) * 2005-08-29 2007-03-15 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Modular microelectronic component
DE102006044016A1 (en) * 2006-09-15 2008-04-03 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Stackable functional layer for a modular microelectronic system
FR2923081B1 (en) * 2007-10-26 2009-12-11 3D Plus PROCESS FOR VERTICAL INTERCONNECTION OF 3D ELECTRONIC MODULES BY VIAS.
EP2539773B1 (en) * 2010-02-26 2014-04-16 Micronic Mydata AB Method and apparatus for performing pattern alignment
US10777457B2 (en) * 2017-10-03 2020-09-15 Ubotic Company Limited Carrier substrate, package, and method of manufacture
CN112687614A (en) 2019-10-17 2021-04-20 美光科技公司 Microelectronic device assemblies and packages including multiple device stacks and related methods
US11362070B2 (en) * 2019-10-17 2022-06-14 Micron Technology, Inc. Microelectronic device assemblies and packages including multiple device stacks and related methods

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5086018A (en) * 1991-05-02 1992-02-04 International Business Machines Corporation Method of making a planarized thin film covered wire bonded semiconductor package
US6060373A (en) * 1998-07-10 2000-05-09 Citizen Watch Co., Ltd. Method for manufacturing a flip chip semiconductor device
US6342398B1 (en) * 1998-12-17 2002-01-29 Taiwan Semiconductor Manufacturing Company Method of backside emission analysis for BGA packaged IC's

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5086018A (en) * 1991-05-02 1992-02-04 International Business Machines Corporation Method of making a planarized thin film covered wire bonded semiconductor package
US6060373A (en) * 1998-07-10 2000-05-09 Citizen Watch Co., Ltd. Method for manufacturing a flip chip semiconductor device
US6342398B1 (en) * 1998-12-17 2002-01-29 Taiwan Semiconductor Manufacturing Company Method of backside emission analysis for BGA packaged IC's

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