WO2003003459A2 - Arrangement of a semiconductor component on a substrate - Google Patents

Arrangement of a semiconductor component on a substrate Download PDF

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Publication number
WO2003003459A2
WO2003003459A2 PCT/DE2002/001896 DE0201896W WO03003459A2 WO 2003003459 A2 WO2003003459 A2 WO 2003003459A2 DE 0201896 W DE0201896 W DE 0201896W WO 03003459 A2 WO03003459 A2 WO 03003459A2
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WO
WIPO (PCT)
Prior art keywords
chip
substrate
contact surfaces
electrically connected
semiconductor component
Prior art date
Application number
PCT/DE2002/001896
Other languages
German (de)
French (fr)
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WO2003003459A3 (en
Inventor
Holger HÜBNER
Original Assignee
Infineon Technologies Ag
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Publication date
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Publication of WO2003003459A2 publication Critical patent/WO2003003459A2/en
Publication of WO2003003459A3 publication Critical patent/WO2003003459A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds

Definitions

  • the present invention relates to an arrangement of a semiconductor component comprising at least two semiconductor chips on a substrate provided as a chip carrier.
  • Semiconductor components which consist of a first chip and at least one second chip, the second chip being arranged on the first chip and the first and the second chip being electrically connected to one another, are known from the prior art.
  • the second chip which is usually arranged on a first main side with contact areas of the first chip, is regularly electrically connected to some of the contact areas of the first chip via bond wires.
  • the second chip is consequently arranged with its rear side, that is to say the side which has no contact areas, on the first main side of the chip.
  • the semiconductor component thus obtained is in turn arranged on a substrate and electrically connected to it.
  • the back of the first chip - that is to say the main side opposite the first main side - is usually arranged on the substrate.
  • Contact areas located on the main side of the first chip can then be connected via bonding wires to corresponding contact areas on the component side of the substrate.
  • the object of the present invention is to provide an alternative solution for the arrangement of a generic semiconductor component on a substrate.
  • the invention proposes an arrangement of a semiconductor component on a substrate, in which the substrate has contact areas on an assembly side.
  • the semiconductor component consists of a first chip and at least one second chip, the second chip being arranged on the first chip and the first and the second chip being electrically connected to one another.
  • the first chip has contact areas on its first main side, via which the first chip can be electrically connected to associated contact areas of the substrate.
  • the invention provides that the contact areas located on the first main side of the first chip face the contact areas of the substrate and are connected to the contact areas of the substrate via a connecting means.
  • the contact areas of the first chip and the substrate are connected to one another via a connecting means.
  • an intermediate carrier is provided as the connecting means between mutually associated contact surfaces of the first chip and the substrate, which has contact surfaces on its upper and lower sides which are oriented such that they face the contact surfaces of the first chip and the contact surfaces of the substrate and are electrically connected to these, wherein respective contact surfaces of the intermediate carrier are electrically connected via vias.
  • the mutually assigned contact areas on the top and the contact areas of the first chip can be connected via a diffusion solder layer, as a result of which the distance between the mutually assigned contact areas is less than 10 ⁇ m.
  • the second chip is arranged on the first main side of the carrier, the intermediate carrier advantageously has usually has a recess into which the at least one second chip protrudes.
  • conductive adhesives, solder bumps or stud bumps are used as connecting means.
  • the contact areas of the first chip and those of the substrate face one another.
  • the first chip is thus contacted with the substrate via the solder bumps, stud bumps or the conductive adhesive flip chip.
  • the second chip is connected to the first chip using diffusion soldering technology (SOLID) and if the back of the chip is thinned at the same time, the second chip has a smaller thickness than that of the connecting means.
  • the second chip or chips can thus be protected in the cavity formed by the substrate, the first chip and the connecting means.
  • the substrate preferably also has contact areas which consist of a SOLID metallization. Since, in the variant described, the connection can take place over a large area due to the large contact areas, an additional stabilizing agent between the semiconductor component and the substrate can be dispensed with. An "underfill” is usually used as a stabilizing agent. The procedure described is particularly advantageous when the substrate is a film carrier.
  • the contact areas on the first main side of the first chip are preferably implemented as SOLID metallization, which is known per se. Compared to conventional bond pads in the top metal layer of a chip, these SOLID
  • Metallizations have the advantage that they can be made much larger.
  • the bond pads in conventional chips are usually implemented in the top metal level on the first main side of the chip. The available area for the bond pad is therefore limited for design reasons.
  • the SOLID metallization is arranged on the first main side of the first chip and above a much smaller via is electrically connected to the bond pad in the top metal layer of the chip. As a result, almost the entire area for the bond pads in the first chip can be omitted, since the area required for contacting is provided directly on the passivation layer of the chip by the SOLID metallization.
  • SOLID metallizations are characterized in particular by the fact that they are highly temperature-resistant. The metallizations survive temperatures above 600 ° C without damage. These properties make it possible to use inexpensive soldering methods when contacting the semiconductor component with a substrate instead of the bond connections that are usually used.
  • the contact surfaces consist, for example, of AlSiCu or are already metallized with a solderable surface, for example copper.
  • the invention makes it possible to contact the semiconductor component, that is to say in particular the first chip, with the substrate on the principle of the “flip chip”.
  • the at least one second chip is arranged on the first main side of the first chip.
  • the second chip is therefore preferably located on the side on which the contact surfaces to be connected to the substrate are provided. This procedure makes it possible to manufacture the semiconductor component as long as the first chips are still present in the wafer assembly.
  • the at least one second chip is preferably arranged toward the first chip in such a way that contact areas of the first and second chips which are assigned to one another face one another and are electrically connected to one another, the distance between a respective contact area of the first and the second chip second chips is less than 10 microns. In preferred embodiments, this distance is only at most half as large or, better, only at most a quarter as large. A typical distance of 2 ⁇ m between the contact areas with a high contact density can be achieved by the method of diffusion soldering technology (SOLID), which is known per se.
  • SOLID diffusion soldering technology
  • This arrangement according to the invention with a small distance between a respective contact area of the first and the second semiconductor chip is particularly advantageous when using a thin, flexible second chip. It is particularly advantageous if the first chip is also thin and flexible. It has been demonstrated in tests that a full-surface connection of the first and second chip leads to reliable contacting, even if the distance is less than 10 ⁇ m and the connection zone or connection layer consists of a material that does not allow plastic flow, such as for example intermetallic phases of the connection material used in diffusion soldering.
  • the first and second chips arranged one above the other are optimized with regard to their bending behavior.
  • there is an extremely thin layer stack which can be used advantageously in all arrangements to be miniaturized.
  • the substrate preferably likewise has a recess into which the at least one second chip projects.
  • the thickness of the second chip is in any case greater than the thickness of the diffusion solder layer. Without the mentioned recess, the second chip would have to be on the main chip facing away from the substrate. side of the first chip. However, this would complicate the electrical contacting of the first and second chips.
  • FIG. 1 shows a perspective view of an arrangement known from the prior art, the semiconductor component being connected to the substrate via bond wires, FIG.
  • FIG. 2 shows a first exemplary embodiment of the arrangement according to the invention, in which the semiconductor component is contacted with the substrate via a diffusion solder connection,
  • FIG. 3 shows a second exemplary embodiment of the arrangement according to the invention, in which the contact surfaces of the semiconductor component and of the substrate are connected to one another via conductive adhesive or solder bumps,
  • FIG. 4 shows a third exemplary embodiment of the arrangement according to the invention, in which an intermediate carrier is provided between the semiconductor component and the substrate, and
  • FIG. 5 shows an enlarged section from the first chip, which represents the structure of the SOLID metallization.
  • Figure 1 shows an arrangement known from the prior art in a perspective view.
  • a semiconductor component consisting of a first chip 10 and a second chip 20 applied to its first main side 11 is arranged on the component side 31 of a substrate 30.
  • the second chip 20 has a substantially smaller area than the first Chip 10 on.
  • the first and second chips are electrically connected to one another "face-to-face".
  • the first and the second chip 10, 20 thus each have associated contact areas which are electrically connected to one another. This type of connection does not emerge from the perspective illustration chosen in FIG. 1.
  • the contact surfaces assigned to the second chip would have to be arranged adjacent to the edge thereof.
  • the first chip 10 has on its first main side 11 contact areas 12 which are electrically connected to contact areas 32 of the substrate 30 via bond wires 51.
  • the semiconductor component is mechanically attached to the substrate, for example, by adhesive bonding or soldering.
  • FIG. 1 shows, by way of example, only a second chip 20 on the first main side 11 of the first chip 10. It is also known to arrange a plurality of second chips 20 on the first main side 11. It is also conceivable that the second chip 20 is designed as a chip stack, that is to say as a plurality of chips arranged one above the other. Such chip stacks and their contacting with one another are known from the prior art.
  • FIG. 2 shows a first embodiment of the arrangement according to the invention.
  • the semiconductor component is basically constructed as described in FIG. 1.
  • the first and the second chip 10, 20 are preferably connected by means of diffusion soldering technology (SOLID).
  • the respective contact surfaces 12, 22 are in this case via plated-through holes, which are much smaller than the contact surface itself, with respective contact pads in the uppermost metal layer of the Most chips 10 and second chips 20 connected. This can be seen, for example, from FIG. 5 of the application.
  • the distance between a respective contact area of the first and the second chip is less than 10 ⁇ m.
  • the electrical contact with contact surfaces 32 of the substrate 30 is now "flip chip".
  • contact areas 12, 32 which are assigned to one another are connected to one another via a diffusion solder layer 52.
  • the distance between the mutually associated contact surfaces 12, 32 is thus a maximum of 10 ⁇ m. Since a second chip 20 thinned from its rear side also has a greater thickness D 1, a recess 33 is provided in the substrate 30, into which the second chip 20 projects. The recess 33 is advantageously adapted to the size of the second chip 20. In FIG. 2, the second chip 20 does not necessarily have to be thinned from the back. However, thinning has advantages in terms of its flexibility and thus in terms of its reliability.
  • mutually associated contact surfaces 12, 32 are electrically and mechanically connected to one another with a conductive adhesive or solder bumps 50.
  • the thickness D2 of the conductive adhesive or the solder bump 50 is regularly greater than the thickness D1 of the second chip 20. Therefore, in this exemplary embodiment it is not necessary to provide a recess in the substrate 30. The second chip 20 thus comes to rest in the cavity formed by the first chip 10, the substrate 30 and the conductive adhesive or the solder bumps 50.
  • a further mechanical fastening of the semiconductor component to the substrate, for example by means of an underfill, is not necessary, but is conceivable, since the contact surfaces 12, 32 produced using SOLID technology already provide a sufficiently large connection. Any other desired soldering method could also be used as the connecting means between the mutually assigned contact surfaces 12, 32.
  • the SOLID metallizations have a particularly high temperature resistance.
  • the SOLID metallization is distinguished by the fact that the contact pads 13 in the uppermost metal layer of the first chip or of the substrate are connected to respective contact areas via vias 14. The contact pads 13 in turn need only a small area. The surface in the uppermost metal layer obtained in the substrate or chip can thus be used for other purposes.
  • FIG. 5 shows the structure of such a SOLID metallization.
  • FIG. 4 shows a third exemplary embodiment of the arrangement according to the invention.
  • the semiconductor component consisting of the first and the second chip 10, 20, is here contacted with the substrate 30 via an intermediate carrier 40.
  • the intermediate carrier 40 is with its underside 42 with the
  • the intermediate carrier 40 On its underside 42, the intermediate carrier 40 has contact surfaces 45 which are assigned to the contact surfaces 32 of the substrate. The contact surfaces 45 are electrically connected via contacts 46 to contact surfaces 44 on the upper side 41. The contact areas 12 of the first chip 10 are assigned to the contact areas 44. The electrical contacting of respectively assigned contact areas is preferably carried out by means of a diffusion solder connection. Due to the small thickness of a diffusion solder joint, the intermediate carrier
  • the use of a conductive adhesive instead of the head layer which has grown up on the contact areas also enables small thicknesses between the respectively assigned contact areas.
  • the intermediate carrier like the solder bumps or stud bumps, compensate for a thermal mismatch between the semiconductor component and the substrate, as is customary in conventional arrangements.

Abstract

The invention relates to an arrangement of a semiconductor component on a substrate, whereby the substrate (30) comprises contact surfaces (32) on an assembly side (31). The semiconductor component comprises a first chip (10) and at least one second chip (20), whereby the second chip (20) is arranged on the first chip (10). The first and the second chip (10, 20) are thus electrically connected to each other. Furthermore the first chip (10) comprises contact surfaces (12) on the first main side (11) thereof, with which the above faces the assembly side (31) of the substrate (30). The contact surfaces of the first chip (10) are electrically connected to the corresponding contact surfaces (32) of the substrate (30) by means of a jointing agent.

Description

Beschreibungdescription
Anordnung eines Halbleiterbauelementes auf einem SubstratArrangement of a semiconductor device on a substrate
Die vorliegende Erfindung betrifft eine Anordnung eines Halbleiterbauelementes aus zumindest zwei Halbleiterchips auf einem als Chipträger vorgesehenen Substrat.The present invention relates to an arrangement of a semiconductor component comprising at least two semiconductor chips on a substrate provided as a chip carrier.
Halbleiterbauelemente, welche aus einem ersten Chip und zu- mindest einem zweiten Chip bestehen, wobei der zweite Chip auf dem ersten Chip angeordnet ist und wobei der erste und der zweite Chip elektrisch miteinander verbunden sind, sind aus dem Stand der Technik bekannt. Der zweite Chip, welcher üblicherweise auf einer ersten Hauptseite mit Kontaktflächen des ersten Chips angeordnet ist, ist regelmäßig über Bonddrähte mit einigen der Kontaktflächen des ersten Chips elektrisch verbunden. Der zweite Chip wird folglich mit seiner Rückseite, also der Seite, die keine Kontaktflächen aufweist, auf der ersten Hauptseite des Chips angeordnet.Semiconductor components which consist of a first chip and at least one second chip, the second chip being arranged on the first chip and the first and the second chip being electrically connected to one another, are known from the prior art. The second chip, which is usually arranged on a first main side with contact areas of the first chip, is regularly electrically connected to some of the contact areas of the first chip via bond wires. The second chip is consequently arranged with its rear side, that is to say the side which has no contact areas, on the first main side of the chip.
Das so beschaffene Halbleiterbauelement wird seinerseits wiederum auf einem Substrat angeordnet und elektrisch mit diesem verbunden. Üblicherweise wird der erste Chip mit seiner Rückseite - also der der ersten Hauptseite gegenüberliegenden Hauptseite - auf dem Substrat angeordnet. Auf der erstenThe semiconductor component thus obtained is in turn arranged on a substrate and electrically connected to it. The back of the first chip - that is to say the main side opposite the first main side - is usually arranged on the substrate. On the first
Hauptseite des ersten Chips befindliche Kontaktflächen können dann über Bonddrähte mit entsprechenden Kontaktflächen auf der Bestückungsseite des Substrates verbunden werden.Contact areas located on the main side of the first chip can then be connected via bonding wires to corresponding contact areas on the component side of the substrate.
Die Aufgabe der vorliegenden Erfindung besteht darin, eine alternative Lösung für die Anordnung eines gattungsgemäßen Halbleiterbauelementes auf einem Substrat anzugeben.The object of the present invention is to provide an alternative solution for the arrangement of a generic semiconductor component on a substrate.
Diese Aufgabe wird mit den Merkmalen des Anspruches 1 sowie den Merkmalen des Anspruches 2 gelöst. Vorteilhafte Ausgestaltungen der Erfindung ergeben sich aus den abhängigen Ansprüchen . Die Erfindung schlägt eine Anordnung eines Halbleiterbauelementes auf einem Substrat vor, bei der das Substrat auf einer Bestückungsseite Kontaktflächen aufweist. Das Halbleiterbauelement besteht aus einem ersten Chip und zumindest einem zweiten Chip, wobei der zweite Chip auf dem ersten Chip angeordnet ist und wobei der erste und der zweite Chip elektrisch miteinander verbunden sind. Der erste Chip weist auf seiner ersten Hauptseite Kontaktflächen auf, über die der erste Chip elektrisch mit zugeordneten Kontaktflächen des Substrates verbunden werden kann. Die Erfindung sieht vor, daß die auf der ersten Hauptseite des ersten Chips gelegenen Kontaktflächen den Kontaktflächen des Substrates zugewandt sind und über ein Verbindungsmittel mit den Kontaktflächen des Substrates verbunden sind.This object is achieved with the features of claim 1 and the features of claim 2. Advantageous embodiments of the invention result from the dependent claims. The invention proposes an arrangement of a semiconductor component on a substrate, in which the substrate has contact areas on an assembly side. The semiconductor component consists of a first chip and at least one second chip, the second chip being arranged on the first chip and the first and the second chip being electrically connected to one another. The first chip has contact areas on its first main side, via which the first chip can be electrically connected to associated contact areas of the substrate. The invention provides that the contact areas located on the first main side of the first chip face the contact areas of the substrate and are connected to the contact areas of the substrate via a connecting means.
Gemäß dem Gedanken der Erfindung werden die Kontaktflächen des ersten Chips und des Substrates über ein Verbindungsmittel miteinander verbunden.According to the idea of the invention, the contact areas of the first chip and the substrate are connected to one another via a connecting means.
Als Verbindungsmittel zwischen einander zugeordneten Kontaktflächen des ersten Chips und des Substrats ist in einer ersten Variante ein Zwischenträger vorgesehen, der auf seiner Ober- und Unterseite Kontaktflächen aufweist, die so ausgerichtet sind, daß sie den Kontaktflächen des ersten Chips und den Kontaktflächen des Substrates zugewandt und mit diesen elektrisch verbunden sind, wobei jeweilige Kontaktflächen des Zwischenträgers über Durchkontakte elektrisch in Verbindung stehen. Bei der Verwendung eines Zwischenträgers können die einander zugeordneten Kontaktflächen auf der Oberseite und die Kontaktflächen des ersten Chips über eine Diffusionslotschicht verbunden werden, wodurch der Abstand zwischen den einander zugeordneten Kontaktflächen weniger als 10 μm beträgt. Gleiches gilt für die einander zugeordneten Kontaktflächen des Zwischenträgers und den Kontaktflächen des Sub- strates. Ist der zweite Chip auf der ersten Hauptseite des Trägers angeordnet, so weist der Zwischenträger vorteilhaf- terweise eine Ausnehmung auf, in die der zumindest eine zweite Chip hineinragt .In a first variant, an intermediate carrier is provided as the connecting means between mutually associated contact surfaces of the first chip and the substrate, which has contact surfaces on its upper and lower sides which are oriented such that they face the contact surfaces of the first chip and the contact surfaces of the substrate and are electrically connected to these, wherein respective contact surfaces of the intermediate carrier are electrically connected via vias. When using an intermediate carrier, the mutually assigned contact areas on the top and the contact areas of the first chip can be connected via a diffusion solder layer, as a result of which the distance between the mutually assigned contact areas is less than 10 μm. The same applies to the mutually associated contact areas of the intermediate carrier and the contact areas of the substrate. If the second chip is arranged on the first main side of the carrier, the intermediate carrier advantageously has usually has a recess into which the at least one second chip protrudes.
Als Verbindungsmittel werden in einer zweiten Variante Leit- kleber, Lotbumps oder Studbumps verwendet. In dieser Ausgestaltung sind die Kontaktflächen des ersten Chips und die des Substrates einander zugewandt. Der erste Chip wird somit über die Lotbumps, Studbumps oder den Leitkleber Flip-Chip mit dem Substrat kontaktiert. Wird der zweite Chip über die Diffusi- onslöttechnik (SOLID) mit dem ersten Chip verbunden, und ist dieser gleichzeitig auf seiner Rückseite gedünnt, so weist der zweite Chip eine geringere Dicke als die des Verbindungsmittels auf. Der beziehungsweise die zweiten Chips können somit geschützt in dem durch das Substrat, den ersten Chip und das Verbindungsmittel gebildeten Hohlraum angeordnet werden.In a second variant, conductive adhesives, solder bumps or stud bumps are used as connecting means. In this embodiment, the contact areas of the first chip and those of the substrate face one another. The first chip is thus contacted with the substrate via the solder bumps, stud bumps or the conductive adhesive flip chip. If the second chip is connected to the first chip using diffusion soldering technology (SOLID) and if the back of the chip is thinned at the same time, the second chip has a smaller thickness than that of the connecting means. The second chip or chips can thus be protected in the cavity formed by the substrate, the first chip and the connecting means.
Vorzugsweise weist auch das Substrat Kontaktflächen auf, die aus einer SOLID-Metallisierung bestehen. Da bei der beschriebenen Variante die Verbindung großflächig aufgrund der großen Kontaktflächen erfolgen kann, kann auf ein zusätzliches Stabilisierungsmittel zwischen dem Halbleiterbauelement und dem Substrat verzichtet werden. Üblicherweise wird als Stabilisierungsmittel ein "Underfill" verwendet. Besonders vorteilhaft ist das beschriebene Vorgehen dann, wenn das Substrat ein Folienträger ist.The substrate preferably also has contact areas which consist of a SOLID metallization. Since, in the variant described, the connection can take place over a large area due to the large contact areas, an additional stabilizing agent between the semiconductor component and the substrate can be dispensed with. An "underfill" is usually used as a stabilizing agent. The procedure described is particularly advantageous when the substrate is a film carrier.
Die Kontaktflächen auf der ersten Hauptseite des ersten Chips sind bevorzugt als SOLID-Metallisierung ausgeführt, die an sich bekannt ist. Gegenüber konventionellen Bondpads in der obersten Metallage eines Chips weisen diese SOLID-The contact areas on the first main side of the first chip are preferably implemented as SOLID metallization, which is known per se. Compared to conventional bond pads in the top metal layer of a chip, these SOLID
Metallisierungen den Vorteil auf, daß diese wesentlich größer ausgeführt werden können. Die Bondpads bei konventionellen Chips sind üblicherweise in der obersten Metallebene auf der ersten Hauptseite des Chips ausgeführt. Die zur Verfügung stehende Fläche für das Bondpad ist deshalb aus Design- Gründen begrenzt. Die SOLID-Metalli-sierung hingegen ist auf der ersten Hauptseite des ersten Chips angeordnet und über eine wesentlich kleinere Durchkontaktierung mit dem Bondpad in der obersten Metallage des Chips elektrisch verbunden. Hierdurch kann fast die gesamte Fläche für die Bondpads im ersten Chip entfallen, da die zur Kontaktierung benötigte Fläche durch die SOLID-Metallisierung direkt auf der Passi- vierungsschicht des Chips bereitgestellt wird.Metallizations have the advantage that they can be made much larger. The bond pads in conventional chips are usually implemented in the top metal level on the first main side of the chip. The available area for the bond pad is therefore limited for design reasons. The SOLID metallization, however, is arranged on the first main side of the first chip and above a much smaller via is electrically connected to the bond pad in the top metal layer of the chip. As a result, almost the entire area for the bond pads in the first chip can be omitted, since the area required for contacting is provided directly on the passivation layer of the chip by the SOLID metallization.
SOLID-Metallisierungen zeichnen sich insbesondere dadurch aus, daß sie hoch temperaturfest sind. Die Metallisierungen überstehen unbeschadet Temperaturen über 600°C. Diese Eigenschaften erlauben es, bei der Kontaktierung des Halbleiterbauelementes mit einem Substrat anstatt der üblicherweise verwendeten Bondverbindungen kostengünstige Lötverfahren anzuwenden .SOLID metallizations are characterized in particular by the fact that they are highly temperature-resistant. The metallizations survive temperatures above 600 ° C without damage. These properties make it possible to use inexpensive soldering methods when contacting the semiconductor component with a substrate instead of the bond connections that are usually used.
Die Kontaktflächen bestehen beispielsweise aus AlSiCu oder sind bereits mit einer lötbaren Oberfläche, zum Beispiel Kupfer, metallisiert.The contact surfaces consist, for example, of AlSiCu or are already metallized with a solderable surface, for example copper.
Wie aus der nachfolgenden Beschreibung ersichtlich werden wird, ermöglicht es die Erfindung, das Halbleiterbauelement, das heißt insbesondere den ersten Chip, nach dem Prinzip des "Flip-Chip" mit dem Substrat zu kontaktieren.As will become apparent from the description below, the invention makes it possible to contact the semiconductor component, that is to say in particular the first chip, with the substrate on the principle of the “flip chip”.
In einer vorteilhaften Ausgestaltung ist der zumindest eine zweite Chip auf der ersten Hauptseite des ersten Chips angeordnet. Vorzugsweise befindet sich der zweite Chip folglich auf der Seite, auf der die mit dem Substrat zu verbindenden Kontaktflächen vorgesehen sind. Dieses Vorgehen ermöglicht, die Herstellung des Halbleiterbauelementes, solange die ersten Chips noch im Waferverbund vorliegen.In an advantageous embodiment, the at least one second chip is arranged on the first main side of the first chip. The second chip is therefore preferably located on the side on which the contact surfaces to be connected to the substrate are provided. This procedure makes it possible to manufacture the semiconductor component as long as the first chips are still present in the wafer assembly.
Vorzugsweise ist der zumindest eine zweite Chip so zu dem ersten Chip hin angeordnet, daß einander zugeordnete Kontakt- flächen des ersten und des zweiten Chips einander zugewandt und elektrisch miteinander verbunden sind, wobei der Abstand zwischen einer jeweiligen Kontaktfläche des ersten und des zweiten Chips weniger als 10 μm beträgt. Bei bevorzugten Ausführungsformen ist dieser Abstand nur höchstens halb so groß oder besser nur höchstens ein Viertel so groß. Ein typischer Abstand von 2 μm zwischen den Kontaktflächen bei gleichzeitig hoher Kontaktdichte kann durch das Verfahren der Diffusionslöttechnik (SOLID) , die an sich bekannt ist, erreicht werden.The at least one second chip is preferably arranged toward the first chip in such a way that contact areas of the first and second chips which are assigned to one another face one another and are electrically connected to one another, the distance between a respective contact area of the first and the second chip second chips is less than 10 microns. In preferred embodiments, this distance is only at most half as large or, better, only at most a quarter as large. A typical distance of 2 μm between the contact areas with a high contact density can be achieved by the method of diffusion soldering technology (SOLID), which is known per se.
Diese erfindungsgemäße Anordnung mit einem geringen Abstand zwischen einer jeweiligen Kontaktfläche des ersten und des zweiten Halbleiterchips ist insbesondere vorteilhaft bei einer Verwendung eines dünnen, flexiblen zweiten Chips. Besonders vorteilhaft ist es, wenn der erste Chip ebenfalls dünn und flexibel ausgeführt ist. Es wurde in Versuchen nachgewiesen, daß eine ganzflächige Verbindung von erstem und zweitem Chip zu einer zuverlässigen Kontaktierung führt, auch wenn der Abstand weniger als 10 μm beträgt und die Verbindungszone oder Verbindungsschicht aus einem Material besteht, das kein plastisches Fließen ermöglicht, wie zum Beispiel die intermetallischen Phasen des Verbindungsmaterials, das beim Diffusi- onslöten eingesetzt wird.This arrangement according to the invention with a small distance between a respective contact area of the first and the second semiconductor chip is particularly advantageous when using a thin, flexible second chip. It is particularly advantageous if the first chip is also thin and flexible. It has been demonstrated in tests that a full-surface connection of the first and second chip leads to reliable contacting, even if the distance is less than 10 μm and the connection zone or connection layer consists of a material that does not allow plastic flow, such as for example intermetallic phases of the connection material used in diffusion soldering.
Die so übereinander angeordneten ersten und zweiten Chips sind hinsichtlich ihres Biegeverhaltens optimiert. Darüber hinaus ergibt sich ein äußerst dünner Schichtstapel, welcher in allen zu miniaturisierenden Anordnungen vorteilhaft eingesetzt werden kann.The first and second chips arranged one above the other are optimized with regard to their bending behavior. In addition, there is an extremely thin layer stack, which can be used advantageously in all arrangements to be miniaturized.
Werden die Kontaktflächen des ersten Chips des Halbleiterbauelementes direkt mit den Kontaktflächen des Substrates über eine Diffusionslotschicht verbunden, so weist das Substrat vorzugsweise ebenfalls eine Ausnehmung auf, in die der zumindest eine zweite Chip hineinragt.If the contact areas of the first chip of the semiconductor component are connected directly to the contact areas of the substrate via a diffusion solder layer, then the substrate preferably likewise has a recess into which the at least one second chip projects.
Bei einer Verbindung über eine Diffusionslotschicht ist die Dicke des zweiten Chips in jedem Fall größer als die Dicke der Diffusionslotschicht. Ohne die genannte Ausnehmung müßte der zweite Chip auf der von dem Substrat abgewandten Haupt- seite des ersten Chips angeordnet werden. Hierdurch würde sich jedoch die elektrische Kontaktierung von erstem und zweitem Chip verkomplizieren.In the case of a connection via a diffusion solder layer, the thickness of the second chip is in any case greater than the thickness of the diffusion solder layer. Without the mentioned recess, the second chip would have to be on the main chip facing away from the substrate. side of the first chip. However, this would complicate the electrical contacting of the first and second chips.
Es folgt eine genauere Beschreibung von Beispielen der erfindungsgemäßen Anordnung anhand der Figuren 1 bis 5. Es zeigen:The following is a more detailed description of examples of the arrangement according to the invention with reference to FIGS. 1 to 5.
Figur 1 eine aus dem Stand der Technik bekannte Anordnung in perspektivischer Ansicht, wobei das Halbleiter- bauelement über Bonddrähte mit dem Substrat verbunden ist,1 shows a perspective view of an arrangement known from the prior art, the semiconductor component being connected to the substrate via bond wires, FIG.
Figur 2 ein erstes Ausführungsbeispiel der erfindungsgemäßen Anordnung, bei der das Halbleiterbauelement über eine Diffusionslotverbindung mit dem Substrat kontaktiert ist,FIG. 2 shows a first exemplary embodiment of the arrangement according to the invention, in which the semiconductor component is contacted with the substrate via a diffusion solder connection,
Figur 3 ein zweites Ausführungsbeispiel der erfindungsgemäßen Anordnung, bei der die Kontaktflächen des Halb- leiterbauelementes und des Substrates über Leitkleber oder Lotbumps miteinander verbunden sind,FIG. 3 shows a second exemplary embodiment of the arrangement according to the invention, in which the contact surfaces of the semiconductor component and of the substrate are connected to one another via conductive adhesive or solder bumps,
Figur 4 ein drittes Ausführungsbeispiel der erfindungsgemäßen Anordnung, bei der zwischen dem Halbleiterbau- element und dem Substrat ein Zwischenträger vorgesehen ist undFIG. 4 shows a third exemplary embodiment of the arrangement according to the invention, in which an intermediate carrier is provided between the semiconductor component and the substrate, and
Figur 5 einen vergrößerten Ausschnitt aus dem ersten Chip, der den Aufbau der SOLID-Metallisierung darstellt.FIG. 5 shows an enlarged section from the first chip, which represents the structure of the SOLID metallization.
Figur 1 zeigt eine aus dem Stand der Technik bekannte Anordnung in einer perspektivischen Darstellung. Auf der Bestük- kungsseite 31 eines Substrates 30 ist ein Halbleiterbauelement, bestehend aus einem ersten Chip 10 und einem auf dessen erster Hauptseite 11 aufgebrachten zweiten Chip 20 angeordnet. Der zweite Chip 20 weist, wie aus der Figur 1 gut ersichtlich ist, eine wesentlich kleinere Fläche als der erste Chip 10 auf. Erster und zweiter Chip sind " face-to-face" elektrisch miteinander verbunden. Der erste und der zweite Chip 10, 20 weisen somit jeweils einander zugeordnete Kontaktflächen auf, die elektrisch miteinander verbunden sind. Aus der in der Figur 1 gewählten perspektivischen Darstellung geht diese Art der Verbindung nicht hervor. Alternativ ist auch bekannt, den zweiten Chip 20 mit seiner Rückseite auf die erste Hauptseite 11 des ersten Chips 10 aufzubringen und eine elektrische Verbindung zwischen jeweiligen Kontaktflä- chen des ersten und zweiten Chips 10, 20 über Bonddrähte zu realisieren. In diesem Fall müßten die dem zweiten Chip zugeordneten Kontaktflächen benachbart dessen Berandung angeordnet sein.Figure 1 shows an arrangement known from the prior art in a perspective view. A semiconductor component consisting of a first chip 10 and a second chip 20 applied to its first main side 11 is arranged on the component side 31 of a substrate 30. As can be clearly seen in FIG. 1, the second chip 20 has a substantially smaller area than the first Chip 10 on. The first and second chips are electrically connected to one another "face-to-face". The first and the second chip 10, 20 thus each have associated contact areas which are electrically connected to one another. This type of connection does not emerge from the perspective illustration chosen in FIG. 1. Alternatively, it is also known to apply the rear side of the second chip 20 to the first main side 11 of the first chip 10 and to implement an electrical connection between the respective contact areas of the first and second chips 10, 20 via bonding wires. In this case, the contact surfaces assigned to the second chip would have to be arranged adjacent to the edge thereof.
Der erste Chip 10 weist auf dessen erster Hauptseite 11 Kontaktflächen 12 auf, die über Bonddrähte 51 mit Kontaktflächen 32 des Substrates 30 elektrisch verbunden sind. Die mechanische Befestigung des Halbleiterbauelementes mit dem Substrat erfolgt beispielsweise durch Klebung oder Lötung.The first chip 10 has on its first main side 11 contact areas 12 which are electrically connected to contact areas 32 of the substrate 30 via bond wires 51. The semiconductor component is mechanically attached to the substrate, for example, by adhesive bonding or soldering.
In der Figur 1 ist beispielhaft nur ein zweiter Chip 20 auf der ersten Hauptseite 11 des ersten Chips 10 dargestellt. Es ist auch bekannt, mehrere zweite Chips 20 jeweils auf der ersten Hauptseite 11 anzuordnen. Denkbar ist auch, daß der zweite Chip 20 als Chipstapel, also als mehrere übereinander angeordnete Chips, ausgebildet ist. Derartige Chipstapel und deren Kontaktierung untereinander sind aus dem Stand der Technik bekannt .1 shows, by way of example, only a second chip 20 on the first main side 11 of the first chip 10. It is also known to arrange a plurality of second chips 20 on the first main side 11. It is also conceivable that the second chip 20 is designed as a chip stack, that is to say as a plurality of chips arranged one above the other. Such chip stacks and their contacting with one another are known from the prior art.
Figur 2 zeigt ein erstes Ausführungsbeispiel der erfindungsgemäßen Anordnung. Das Halbleiterbauelement ist dabei prinzipiell wie in Figur 1 beschrieben, aufgebaut. Der erste und der zweite Chip 10, 20 sind vorzugsweise mittels Diffusions- löttechnik (SOLID) verbunden. Die jeweiligen Kontaktflächen 12, 22 sind dabei über Durchkontaktierungen, welche wesentlich kleiner als die Kontaktfläche selber ausgeführt sind, mit jeweiligen Kontaktpads in der obersten Metallage des er- sten Chips 10 bzw. zweiten Chips 20 verbunden. Dies geht beispielsweise aus der Figur 5 der Anmeldung hervor. Der Abstand zwischen einer jeweiligen Kontaktfläche des ersten und des zweiten Chips beträgt dabei weniger als lOμm. Der elektrische Kontakt mit Kontaktflächen 32 des Substrates 30 erfolgt nun "Flip-Chip" . Im gewählten Ausführungsbeispiel werden einander zugeordnete Kontaktflächen 12, 32 über eine Diffusionslotschicht 52 miteinander verbunden. Der Abstand zwischen den einander zugeordneten Kontaktflächen 12, 32 beträgt somit ma- ximal 10 μm. Da auch ein von seiner Rückseite her gedünnter zweiter Chip 20 eine größere Dicke Dl aufweist, ist in dem Substrat 30 eine Ausnehmung 33 vorgesehen, in die der zweite Chip 20 hineinragt. Die Ausnehmung 33 ist dabei vorteilhafterweise an die Größe des zweiten Chips 20 angepaßt. In der Figur 2 braucht der zweite Chip 20 nicht notwendigerweise von seiner Rückseite gedünnt sein. Eine Dünnung bringt jedoch Vorteile bezüglich seiner Flexibilität und somit bezüglich seiner Zuverlässigkeit mit sich.Figure 2 shows a first embodiment of the arrangement according to the invention. The semiconductor component is basically constructed as described in FIG. 1. The first and the second chip 10, 20 are preferably connected by means of diffusion soldering technology (SOLID). The respective contact surfaces 12, 22 are in this case via plated-through holes, which are much smaller than the contact surface itself, with respective contact pads in the uppermost metal layer of the Most chips 10 and second chips 20 connected. This can be seen, for example, from FIG. 5 of the application. The distance between a respective contact area of the first and the second chip is less than 10 μm. The electrical contact with contact surfaces 32 of the substrate 30 is now "flip chip". In the selected exemplary embodiment, contact areas 12, 32 which are assigned to one another are connected to one another via a diffusion solder layer 52. The distance between the mutually associated contact surfaces 12, 32 is thus a maximum of 10 μm. Since a second chip 20 thinned from its rear side also has a greater thickness D 1, a recess 33 is provided in the substrate 30, into which the second chip 20 projects. The recess 33 is advantageously adapted to the size of the second chip 20. In FIG. 2, the second chip 20 does not necessarily have to be thinned from the back. However, thinning has advantages in terms of its flexibility and thus in terms of its reliability.
In dem zweiten Ausführungsbeispiel gemäß Figur 3 sind einander zugeordnete Kontaktflächen 12, 32 mit einem Leitkleber oder Lotbumps 50 miteinander elektrisch und mechanisch verbunden. Die Dicke D2 des Leitklebers beziehungsweise der Lot- bumps 50 ist dabei regelmäßig größer als die Dicke Dl des zweiten Chips 20. Deshalb ist in diesem Ausführungsbeispiel das Vorsehen einer Ausnehmung in dem Substrat 30 nicht notwendig. Der zweite Chip 20 kommt somit in dem durch den ersten Chip 10, das Substrat 30 sowie den Leitkleber bezie- hungsweise die Lotbumps 50 gebildeten Hohlraum zum Liegen.In the second exemplary embodiment according to FIG. 3, mutually associated contact surfaces 12, 32 are electrically and mechanically connected to one another with a conductive adhesive or solder bumps 50. The thickness D2 of the conductive adhesive or the solder bump 50 is regularly greater than the thickness D1 of the second chip 20. Therefore, in this exemplary embodiment it is not necessary to provide a recess in the substrate 30. The second chip 20 thus comes to rest in the cavity formed by the first chip 10, the substrate 30 and the conductive adhesive or the solder bumps 50.
Eine weitere mechanische Befestigung des Halbleiterbauelementes mit dem Substrat, zum Beispiel mittels eines Underfill, ist nicht notwendig, aber denkbar, da durch die in SOLID- Technik hergestellten Kontaktflächen 12, 32 bereits eine aus- reichend großflächige Verbindung gegeben ist. Als Verbindungsmittel zwischen den einander zugeordneten Kontaktflächen 12, 32 könnte auch jedes andere beliebige Lötverfahren eingesetzt werden. Dies ist deshalb möglich, da die SOLID-Metallisierungen eine besonders hohe Temperaturfestig- keit aufweisen. Im Gegensatz zum Stand der Technik zeichnet sich die SOLID-Metallisierung dadurch aus, daß die Kontakt- pads 13 in der obersten Metallage des ersten Chips beziehungsweise des Substrates über Durchkontaktierungen 14 mit jeweiligen Kontaktflächen verbunden sind. Die Kontaktpads 13 brauchen ihrerseits nur eine geringe Fläche. Die in dem Substrat beziehungsweise Chip gewonnene Fläche in der obersten Metallage kann somit für andere Zwecke verwendet werden. Den Aufbau einer derartigen SOLID-Metallisierung zeigt die vorliegende Figur 5.A further mechanical fastening of the semiconductor component to the substrate, for example by means of an underfill, is not necessary, but is conceivable, since the contact surfaces 12, 32 produced using SOLID technology already provide a sufficiently large connection. Any other desired soldering method could also be used as the connecting means between the mutually assigned contact surfaces 12, 32. This is possible because the SOLID metallizations have a particularly high temperature resistance. In contrast to the prior art, the SOLID metallization is distinguished by the fact that the contact pads 13 in the uppermost metal layer of the first chip or of the substrate are connected to respective contact areas via vias 14. The contact pads 13 in turn need only a small area. The surface in the uppermost metal layer obtained in the substrate or chip can thus be used for other purposes. FIG. 5 shows the structure of such a SOLID metallization.
Figur 4 stellt ein drittes Ausführungsbeispiel der erfindungsgemäßen Anordnung dar. Das Halbleiterbauelement, bestehend aus dem ersten und dem zweiten Chip 10, 20 ist hierbei über einen Zwischenträger 40 mit dem Substrat 30 kontaktiert. Der Zwischenträger 40 ist mit seiner Unterseite 42 mit derFIG. 4 shows a third exemplary embodiment of the arrangement according to the invention. The semiconductor component, consisting of the first and the second chip 10, 20, is here contacted with the substrate 30 via an intermediate carrier 40. The intermediate carrier 40 is with its underside 42 with the
Bestückungsseite 31 des Substrates 30 verbunden. Auf seiner Unterseite 42 weist der Zwischenträger 40 Kontaktflächen 45 auf, die den Kontaktflächen 32 des Substrates zugeordnet sind. Die Kontaktflächen 45 sind über Durchkontaktierungen 46 mit Kontaktflächen 44 auf der Oberseite 41 elektrisch verbunden. Den Kontaktflächen 44 sind die Kontaktflächen 12 des ersten Chips 10 zugeordnet. Vorzugsweise erfolgt die elektrische Kontaktierung jeweils zugeordneter Kontaktflächen mittels einer Diffusionslotverbindung. Aufgrund der geringen Dicke einer Diffusionslotverbindung weist der ZwischenträgerEquipped side 31 of the substrate 30 connected. On its underside 42, the intermediate carrier 40 has contact surfaces 45 which are assigned to the contact surfaces 32 of the substrate. The contact surfaces 45 are electrically connected via contacts 46 to contact surfaces 44 on the upper side 41. The contact areas 12 of the first chip 10 are assigned to the contact areas 44. The electrical contacting of respectively assigned contact areas is preferably carried out by means of a diffusion solder connection. Due to the small thickness of a diffusion solder joint, the intermediate carrier
40 eine Ausnehmung 43 auf, in die der zweite Chip 20 hineinragen kann .40 has a recess 43 into which the second chip 20 can protrude.
Die Verwendung eines Leitklebers anstelle der auf den Kon- taktflächen aufgewachenen Kopferschicht ermöglicht ebenfalls geringe Dicken zwischen jeweils zugeordneten Kontaktflächen. Der Zwischenträger, ebenso wie die Lothöcker oder Studbumps übernehmen den Ausgleich einer thermischen Fehlanpassung zwischen dem Halbleiterbauelement und dem Substrat, wie dies bei konventionellen Anordnungen üblich ist. The use of a conductive adhesive instead of the head layer which has grown up on the contact areas also enables small thicknesses between the respectively assigned contact areas. The intermediate carrier, like the solder bumps or stud bumps, compensate for a thermal mismatch between the semiconductor component and the substrate, as is customary in conventional arrangements.
BezugszeichenlisteLIST OF REFERENCE NUMBERS
10 erster Chip10 first chip
11 erste Hauptseite 12 Kontaktfläche11 first main page 12 contact surface
13 Kontaktpad (in der obersten Metallage des Chips)13 contact pad (in the top metal layer of the chip)
14 Durchkontaktierung (Via)14 plated-through hole (Via)
20 zweiter Chip 21 erste Hauptseite20 second chip 21 first main page
22 Kontaktfläche22 contact surface
30 Substrat30 substrate
31 Bestückungsseite 32 Kontaktfläche31 Component side 32 contact area
33 Ausnehmung33 recess
40 Zwischenträger40 intermediate beams
41 Oberseite 42 Unterseite41 top 42 bottom
43 Ausnehmung43 recess
44 Kontaktfläche44 contact surface
45 Kontaktfläche45 contact surface
46 Durchkontaktierung46 plated-through holes
50 Leitkleber, Lothöcker, Studbumps50 conductive adhesives, solder bumps, stud bumps
51 Bonddraht51 bond wire
52 Diffusionslötverbindung52 Diffusion solder connection
Dl Dicke des zweiten ChipsDl thickness of the second chip
D2 Dicke des Verbindungsmittels D2 thickness of the lanyard

Claims

Patentansprüche claims
1. Anordnung eines Halbleiterbauelementes auf einem Substrat, bei der - das Substrat (30) auf einer Bestückungsseite (31) Kontaktflächen (32) aufweist, das Halbleiterbauelement aus einem ersten Chip (10) und zumindest einem zweiten Chip (20) besteht, wobei der zweite Chip (20) auf dem ersten Chip (10) angeordnet ist und wobei der erste und der zweite Chip (10, 20) elektrisch miteinander verbunden sind,1. Arrangement of a semiconductor component on a substrate, in which - the substrate (30) on a component side (31) has contact surfaces (32), the semiconductor component consists of a first chip (10) and at least a second chip (20), the second chip (20) is arranged on the first chip (10) and the first and second chips (10, 20) are electrically connected to one another,
- der erste Chip (10) auf seiner ersten Hauptseite (11) Kontaktflächen (12) aufweist und mit seiner ersten Hauptseite (11) der Bestückungsseite (31) des Substrates (30) zugewandt ist,the first chip (10) has contact surfaces (12) on its first main side (11) and its first main side (11) faces the component side (31) of the substrate (30),
- die Kontaktflächen (12) des ersten Chips (10) mit einander zugeordneten Kontaktflächen (32) des Substrates (30) über ein Verbindungsmittel (40, 50, 51, 52) elektrisch miteinander verbunden sind, wobei als Verbindungsmittel zwischen einander zugeordneten Kontaktflächen (12, 32) des ersten- The contact surfaces (12) of the first chip (10) with mutually associated contact surfaces (32) of the substrate (30) are electrically connected to one another via a connecting means (40, 50, 51, 52), the connecting means between mutually assigned contact surfaces (12 , 32) of the first
Chip (10) und des Substrats (30) ein Zwischenträger (40) vorgesehen ist, der auf seiner Ober- und Unterseite (41, 42) Kontaktflächen (44, 45) aufweist, die so ausgerichtet sind, daß sie den Kontaktflächen (12) des ersten Chips (10) bzw. den Kontaktflächen (32) des Substrates (30) zugewandt und mit diesen elektrisch verbunden sind, wobei jeweilige Kontaktflächen (44, 45) des Zwischenträgers (40) über Durchkontakte (46) elektrisch in Verbindung stehen.Chip (10) and the substrate (30) an intermediate carrier (40) is provided, which has on its top and bottom (41, 42) contact surfaces (44, 45) which are aligned so that they contact surfaces (12) of the first chip (10) or the contact surfaces (32) of the substrate (30) and are electrically connected to them, the respective contact surfaces (44, 45) of the intermediate carrier (40) being electrically connected via vias (46).
2. Anordnung eines Halbleiterbauelementes auf einem Substrat, bei der das Substrat (30) auf einer Bestückungsseite (31) Kontaktflächen (32) aufweist,2. Arrangement of a semiconductor component on a substrate, in which the substrate (30) has contact surfaces (32) on an assembly side (31),
- das Halbleiterbauelement aus einem ersten Chip (10) und zumindest einem zweiten Chip (20) besteht, wobei der zweite Chip (20) auf dem ersten Chip (10) angeordnet ist und wobei der erste und der zweite Chip (10, 20) elektrisch miteinander verbunden sind, der erste Chip (10) auf seiner ersten Hauptseite (11) Kontaktflächen (12) aufweist und mit - seiner ersten Hauptseite (11) der Bestückungsseite (31) des Substrates (30) zugewandt ist, die Kontaktflächen (12) des ersten Chips (10) mit einander zugeordneten Kontaktflächen (32) des Substrates (30) über ein Verbindungsmittel (40, 50, 51, 52) elektrisch mitein- ander verbunden sind, wobei als Verbindungsmittel Leitkleber, Lotbumps oder Studbumps vorgesehen ist und der zumindest eine zweite Chip (20) eine Dicke (Dl) aufweist, die geringer als die Dicke des Verbindungsmittels (D2) zwischen einander zugeordneten Kontaktflächen (12, 32) des ersten Chip (10) und des Substrats (30) ist.- The semiconductor component consists of a first chip (10) and at least one second chip (20), the second chip (20) being arranged on the first chip (10) and wherein the first and the second chip (10, 20) are electrically connected to one another, the first chip (10) has contact surfaces (12) on its first main side (11) and - the first side (11) of the component side (31) of the Facing substrate (30), the contact surfaces (12) of the first chip (10) with mutually associated contact surfaces (32) of the substrate (30) are electrically connected to one another via a connecting means (40, 50, 51, 52), wherein conductive adhesive, solder bumps or stud bumps are provided as connection means and the at least one second chip (20) has a thickness (Dl) that is less than the thickness of the connection means (D2) between mutually associated contact surfaces (12, 32) of the first chip (10) and the substrate (30).
3. Anordnung nach Anspruch 1 oder 2 , bei der der zumindest eine zweite Chip (20) auf der ersten Hauptseite (11) des ersten Chips (10) angeordnet ist.3. Arrangement according to claim 1 or 2, wherein the at least one second chip (20) on the first main side (11) of the first chip (10) is arranged.
4. Anordnung nach einem der Anspruch 1 bis 3, bei der der zumindest eine zweite Chip (20) so zu dem ersten Chip (10) hin angeordnet ist, daß einander zugeordnete Kontaktflächen (12, 22) des ersten und des zweiten Chips (10, 20) ein- ander zugewandt und elektrisch miteinander verbunden sind, wobei der Abstand zwischen einer jeweiligen Kontaktfläche des ersten und des zweiten Chips (10, 20) weniger als 10 μm beträgt .4. Arrangement according to one of claims 1 to 3, wherein the at least one second chip (20) is arranged towards the first chip (10) in such a way that mutually associated contact surfaces (12, 22) of the first and second chips (10 , 20) face one another and are electrically connected to one another, the distance between a respective contact surface of the first and second chips (10, 20) being less than 10 μm.
5. Anordnung nach einem der Ansprüche 1 bis 4, bei der der zumindest eine zweite Chip (20) auf der seinen Kontaktflächen (22) gegenüberliegenden Hauptseite dünn geschliffen ist .5. Arrangement according to one of claims 1 to 4, wherein the at least one second chip (20) on the main surfaces opposite its contact surfaces (22) is thinly ground.
6. Anordnung nach Anspruch 1 oder einem der Ansprüche 3 bis 5 jeweils in Verbindung mit Anspruch 1, bei der als Verbindungsmittel zwischen einander zugeordneten Kontaktflächen (12, 44) des ersten Chip (10) und des Zwischenträgers (40) und zwischen einander zugeordneten Kontaktflächen (45, 32) des Zwischenträgers und des Substrats (32) eine Diffusi- onslotschicht vorgesehen ist, wodurch der Abstand zwischen den einander zugeordneten Kontaktflächen (12, 44; 45, 32) weniger als 10 μm beträgt.6. Arrangement according to claim 1 or one of claims 3 to 5 in each case in connection with claim 1, in which a diffusion solder layer is provided as connecting means between mutually assigned contact surfaces (12, 44) of the first chip (10) and the intermediate carrier (40) and between mutually associated contact surfaces (45, 32) of the intermediate carrier and the substrate (32), whereby the Distance between the mutually assigned contact surfaces (12, 44; 45, 32) is less than 10 μm.
7. Anordnung nach einem der Ansprüche 1 bis 6, bei der das Substrat (30) bzw. der Zwischenträger (40) eine Ausnehmung (33, 43) aufweist, in die der zumindest eine zweite Chip (20) hineinragt. 7. Arrangement according to one of claims 1 to 6, wherein the substrate (30) or the intermediate carrier (40) has a recess (33, 43) into which the at least one second chip (20) protrudes.
PCT/DE2002/001896 2001-06-27 2002-05-23 Arrangement of a semiconductor component on a substrate WO2003003459A2 (en)

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DE10131011A1 (en) 2003-01-16

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