WO2002101548A1

WO2002101548A1 - System for compiling a computer program

Info

Publication number: WO2002101548A1
Application number: PCT/US2002/018217
Authority: WO
Inventors: Douglas J. Gilmore; Mei Ye; Evan Cheng
Original assignee: Equator Technologies, Inc.
Priority date: 2001-06-08
Filing date: 2002-06-07
Publication date: 2002-12-19

Abstract

According to one aspect of the present invention, a method is responsive to a data structure representing a sequence of instructions (fig.4c) representing a trace. The trace includes instructions comprising a conditional block (48A, 50) that represents at least a portion of a control flow construct. The trace may further include an instruction (34) that is positioned subsequent to the conditional block (48A, 50) and has a dependency to at least one of the instructions comprising the conditional block (120). The method comprises: removing, from the conditional block (48A, 50), at least one of the at least one of the at least one instructions (34) to the sequence at a position prior to the conditional block (48A, 50), the at least one predicated instruction having a correspondence with the at least one of the at least one instruction removed (34); and moving the instruction having a dependency to a position prior to the conditional block (48, 50).

Description

SYSTEM FOR COMPILING A COMPUTER PROGRAM.

Field of the Invention

The present invention relates to computer programs, and more particularly to systems and methods for use in compiling computer programs.

Related Art A compiler may be used to translate a computer program (sometimes referred to as computer code) from one computer language (e.g., a high-level computer language) into an intermediate-level computer language (e.g., assembly language) or a low level computer language (e.g., machine language), the computer program often having been written in a higher-level computer language as a matter of convenience. Some compilers (referred to herein as optimizing compilers) also rearrange operations within the program, for example, to help avoid inter-locks between instructions and/or to help maximize utilization of the resources to be used to run the program. This may, in turn, help reduce the execution time of the program. For example, some processors, e.g., super sealer and VLIW (very large instruction word) architectures, offer a high degree of parallelism. An optimizing compiler may be used to rearrange operations within a computer program to help take advantage of such parallelism. The rearrangement of operations is sometimes referred to as code motion.

Fig. 1 shows an example of a portion of a computer program 20 written in a high- level programming language. The computer program 20 is made up of a sequence of instructions (sometimes referred to as statements, orders or commands) indicated at 22 through 36. Instruction 22 is the first instruction in the sequence. Instructions 24 through 30, which are positioned subsequent to instruction 22, form a control flow construct, more particularly, an if-then-else construct 40. The if-then-else construct operates as follows: if the expression (C) is at a logic true state, then instruction 26 will be executed (i.e., instruction 26 will be effective). On the other hand, if the expression (C) is at a logic false state, then the instruction 30 will be executed (i.e., instruction 30 will be effective). Instruction 24 is sometimes referred to as the commit point for the if- then-else construct 40.

Instructions 32 through 36 are positioned subsequent to the if-then-else construct 40. Instruction 34 generates a value for a variable, k. The value of k (i.e., the result of instruction 34) is needed for the execution of instruction 36. Consequently, instruction 36 is said to be dependent on instruction 34, or more simply, said to depend on instruction 34. Note that instruction 34 is itself dependent upon instruction 26.

Because instruction 36 is dependent on instruction 34, it may be desirable to have the result of instruction 34 available when instruction 36 is to be executed. Otherwise, execution of instruction 36 may need to be postponed somewhat, until the result of instruction 34 is available. Thus, in at least some situations, it may be desirable to move instruction 34 to an earlier position (in the sequence) that would allow the instruction to be executed earlier yet preserving the program behavior, so that the result of instruction 34 may be available when instruction 36 is to be executed. Note that in this situation, instruction 34 is a multiplication instruction, which may have a relatively long execution time.

Various compiler methods are capable of rearranging instructions. Figs. 2A through 2B show an example of steps carried out by one compiler to move instruction 34 of the computer program of Fig. 1. This type of compiler first eliminates control flow constructs by 1) removing instructions associated with branches and 2) converting the other instructions in the control flow constructs to predicated or guarded form. The compiler then performs code motion. In the case of the computer program 20 of Fig. 1, the compiler removes instruction 24 and instruction 28 (see Fig. 2A), which are associated with control instructions of the control flow construct 40, and converts instruction 26 and instruction 30, which are the operation instructions in the control flow constructs of the computer program 20 of Fig. 1, to corresponding predicated forms, represented by instruction 26A and instruction 30 A, respectively (see Fig. 2A).

Referring to Fig. 2B, the compiler then performs code motion by moving instruction 34 to an earlier position in the sequence of instructions. For example, the instruction 34 may be moved as shown to a position between instruction 26A and instruction 30A. Alternatively, instruction 34 may be moved to a position between instruction 30A and instruction 32, but is not moved to a position prior to instruction 26A because instruction 34 is dependent on instruction 26A. See also, J.R. Allen et al., "Conversion of control dependence to data dependence," In Conf. Rec. of the Tenth Ann. ACM Svmp. on Principles of Programming Languages, pages 177-189, Austin, TX, January 24-26, 1983. Figs. 2 A through 2B thus evidence a compiler that is fully capable of rearranging operations. Often times however, an optimizing compiler that does not eliminate all control flow constructs is preferred because doing so requires all paths to be executed.

One compiler method that does not eliminate all control flow constructs is referred to as trace scheduling. Trace scheduling is well known. See, for example, J. Fisher, "Trace scheduling: A technique for global microcode compaction," IEEE

Transactions on Computers, C-30, 7 (July 1981), pages 478-490; and P.G. Lowney et al., "The multiflow trace scheduling compiler," The Journal of Supercomputing, 7(1-2):51- 142, May 1993. Trace scheduling includes: 1) selecting a trace, i.e., selecting a path through the branches in the program, and 2) applying code motion, as appropriate, to instructions comprising the trace. Figs. 3 A through 3F show an example of steps that may be carried out by a trace scheduling compiler to relocate or hoist instruction 34 to a location in the computer program 20 of Fig. 1 at which it will be executed earlier than normal. The accompanying discussion refers occasionally to blocks of instructions and conditional blocks of instructions. In referring to such, it should be understood that we are referring to a way of viewing a computer program to facilitate explanation.

However, it should also be understood that trace scheduling may be employed without any express reference to blocks of instructions and/or conditional blocks of instructions. Referring now to Fig. 3A, the computer program 20 may be viewed as having a series of blocks of instructions. For example, a first instruction block 42 includes an instruction 22. It should be understood that there may be additional instruction(s) in the first block 42 of instructions, but are not shown here so as to keep the presentation clear. The control flow construct 40 (i.e., the if-then-else construct) includes a second instruction block 44 and a third instruction block 46. The second block 44 forms the if- then portion of the if-then-else construct 40. The third block 46 forms the else portion of the if-then-else construct 40. The second block 44 is itself comprised of an instruction block 48 and an instruction block 50. Block 48 is made up of instruction 24, which is the commit point for the if-then-else construct 40. As with the first block 42, each of these blocks, as well as blocks discussed hereinbelow, may include additional instruction(s) that are not shown so as to keep the presentation clear.

Block 50 is made up of instruction 26, which is effective only if the expression

(C) is at a logic true state, and is therefore referred to as a conditional block. A conditional block is comprised of a group of instructions that are effective only if a specified logical expression has a specified logic state, i.e., a group of instructions that are effective only in the presence of a specified condition. A conditional block may be preceded, for example, by a conditional branch instruction that initiates, in the absence of the specified condition, a branch around said group of instructions. Except where stated otherwise, the phrase "in the presence of a specified condition" means in the presence of at least a specified condition. The specified condition may be a single condition or a set of conditions.

The third block 46 includes an instruction block 52 and an instruction block 54.

Block 52 includes the instruction 28, which may be viewed as an entry point to the else- portion of the if-then-else construct 40. Block 54 includes the instruction 30, which is effective only if the expression (C) is at a logic false state, and is therefore another conditional block of instructions.

A fourth instruction block 56 includes the instructions 32 through 36. As discussed above, the instruction 36 is dependant upon the instruction 34. Instruction 34 is itself dependent upon instruction 26, which is now seen to be within the conditional block 50.

Trace scheduling compilers are able to select instructions to be moved, and able to determine whether the instructions selected are dependent upon an instruction (or instructions) in a conditional block (or blocks). However, as will be seen hereinbelow, trace scheduling compilers have a drawback that is exhibited in association with moving an instruction (e.g., instruction 34) that is dependent upon an instruction (e.g., instruction

26) in a conditional block.

Fig. 3B is a control flow diagram of the portion of the computer program 20 (Fig.

1). The diagram 60 begins with block 42. Block 42 is followed by a block 48A, which represents a conditional branch associated with the commit point of the if-then-else construct 40. If the logic state of the expression (C) is true, then execution proceeds to block 50, and then proceeds to block 56. On the other hand, if at block 48 A, the logic state of the expression (C) is false, then execution proceeds to block 54, and then proceeds to block 56. Because block 56 succeeds each of block 50 and block 54, block 56 is sometimes referred to as a common successor block.

Referring again to Fig. 3B, the trace scheduling compiler selects a path, represented by a dotted line 62, through the blocks of the computer program. Often times, the goal is to try to select the path that is the one that is most likely to occur, or likely to occur most frequently. Any strategy may be used to select the path. In some instances, the path that is most likely to occur (or likely to occur most frequently) is specified to the compiler (for example by a developer of the computer program to be compiled). In some other instances, the compiler uses a heuristic, which may or may not be predetermined, to make a determination as to which path is most likely to occur (or likely to occur most frequently). In some other instances, testing is performed to make a determination as to which path is most likely to occur (or likely to occur most frequently). There is of course no guarantee that the selected path will be one the one path that actually occurs, or even the path that occurs most frequently.

Blocks traversed by a path are sometimes referred to as a trace. The blocks traversed by the selected path are sometimes referred to as a "main trace". Blocks not traversed by the selected path are also typically referred to as traces, sometimes referred to as "off traces". If a computer program has a control flow construct with multiple paths, the main trace can include only one of the paths of such control flow construct. As to this example, path 62 traverses through blocks 42, 48A, 50, and 56. These blocks may be referred to as a "main trace". Block 54 is not traversed by the selected path 62 and therefore may be referred to as an "off trace".

Fig. 3C shows the blocks in main trace 64, i.e., blocks 42, 48A, 50, and 56. Block 48A and block 50 may be viewed as a single block 44A, where block 44A includes conditional block 50 and a conditional branch instruction 24 A that initiates, if the expression (C) is at a logic false state, a branch around the conditional block 50. The term "conditional branch instruction" includes, but is not limited to, conditional branch instruction(s) that initiate a branch around a group of instructions by branching to the off trace. Fig. 3D shows off trace 66, which is formed by block 54 and block 52A (which includes a branch instruction). Blocks 54 and 52A may be viewed as a single block 46A. Fig. 3E is a trace graph 68 showing main trace 64 and off trace 66 of Figs. 3C and 3D, respectively, prior to any code motion. A line 70 represents the execution path through main trace 64. Line 70 has a series of marks, i.e., marks 72 through 76, and marks 82 through 86. Each mark is associated with an instruction from the main trace. Thus, for example, mark 72 is associated with the instruction 22. Mark 74 is associated with the instruction 24. Mark 76 is associated with the instruction 26. Mark 82 is associated with the instruction 32. Mark 84 is associated with the instruction 34. Mark 86 is associated with the instruction 36.

A line 88 represents the conditional branch path from main trace 64 to off trace 66. The conditional branch path 88 is the path taken if the expression (C) is at a false logic state. A line 90 represents the return path from off trace 66 to main trace 64.

Referring to Fig. 3F, the trace scheduling compiler moves instruction 34 to a position after instruction 26 in the conditional block 50. The instruction 34 is not moved ahead of instruction 26 because the instruction 34 is dependent on the result of instruction 26.

However, because instruction 34 has been moved from the common successor block 56 into the conditional block 50, compensation must be provided so as to preserve the desired operation of the program. The compensation is in the form of an instruction 100, which is a copy of the instruction 34, that is added to off trace 66. The need to compensate the off trace is a drawback to trace scheduling. The need to compensate the off trace results in an increase in the number of instructions, which can cause an increase in the amount of memory needed to run and/or store the program. If the need to compensate the off trace arises often enough, the increased memory requirements may exceed the capacity of the storage media. This, in turn, may cause a significant increase in running time, as larger but slower media are required for program storage. In systems that incorporate very fast, but small instruction catches, this problem, which is sometimes referred to as code explosion, may be particularly acute. These drawbacks are known. See, S. Freudenberger et al., "Avoidance and Suppression of Compensation Code in a Trace Scheduling Compiler," TOPLAS, 16(4): 1156-1214 (1994).

It may of course be possible to restrict code motion in trace scheduling such that the instruction 34 may be swapped with instruction 32 without moving instruction 34 into the conditional block. This restriction would preclude the need to compensate the off trace. However, such restriction would also seriously hinder the ability of the compiler to rearrange the instructions, and thereby hinder, for example, the ability of the compiler to help avoid inter-locks between instructions and/or to help maximize utilization of the resources to be used to run the program.

Summary

Notwithstanding the discussion above, we have determined that code motion can be incorporated into trace scheduling in a way that provides the capability of moving an instruction that is dependent upon an instruction in a conditional block, without the need to add compensation code to an off trace.

According to one aspect of the present invention, a method for use in a compiler of a trace scheduling type is responsive to a data structure representing a sequence of instructions representing a trace, the trace including instructions comprising a conditional block that represents at least a portion of a control flow construct, wherein the trace may further include an instruction that is positioned subsequent to the conditional block and has a dependency to at least one of the instructions comprising the conditional block. The method comprises: removing, from the conditional block, at least one of the at least one instructions upon which there is a dependency; adding at least one predicated instruction to the sequence at a position prior to the conditional block, the at least one predicated instruction having a correspondence with the at least one of the at least one instruction removed; and moving the instruction having a dependency to a position prior to the conditional block.

According to another aspect of the present invention, a trace scheduling compiler is responsive to a data structure representing a sequence of instructions representing a trace, the trace including instructions comprising a conditional block that represents at least a portion of a control flow construct, wherein the trace may further include an instruction that is positioned subsequent to the conditional block and has a dependency to at least one of the instructions comprising the conditional block. The trace scheduling compiler removes, from the conditional block, at least one of the at least one instruction upon which there is a dependency. The trace scheduling compiler adds at least one predicated instruction to the sequence at a position prior to the conditional block, the at least one predicated instruction having a correspondence with the at least one of the at least one instruction removed, and moves the instruction having a dependency to a position prior to the conditional block.

According to another aspect of the present invention, a trace scheduling compiler is responsive to a data structure representing a sequence of instructions representing a trace, the trace including instructions comprising a conditional block that represents at least a portion of a control flow construct, wherein the trace may further include an instruction that is positioned subsequent to the conditional block and has a dependency to at least one of the instructions comprising the conditional block. The trace scheduling compiler comprises instructions to carry out the method of: removing, from the conditional block, at least one of the at least one instructions upon which there is a dependency; adding at least one predicated instruction to the sequence at a position prior to the conditional block, the at least one predicated instruction having a correspondence with the at least one of the at least one instruction removed; and moving the instruction having a dependency to a position prior to the conditional block.

According to another aspect of the present invention, a trace scheduling compiler is responsive to a data structure representing a sequence of instructions representing a trace, the trace including instructions comprising a conditional block that represents at least a portion of a control flow construct, wherein the trace may further include an instruction that is positioned subsequent to the conditional block and has a dependency to at least one of the instructions comprising the conditional block. The trace scheduling compiler comprises: means for removing, from the conditional block, at least one of the at least one instructions upon which there is a dependency; means for adding at least one predicated instruction to the sequence at a position prior to the conditional block, the at least one predicated instruction having a correspondence with the at least one of the at least one instruction removed; and means for moving the instruction having a dependency to a position prior to the conditional block.

According to another aspect of the present invention, a computer program is compiled by a trace scheduling compiler method that is responsive to a data structure representing a sequence of instructions representing a trace, the trace including instructions comprising a conditional block that represents at least a portion of a control flow construct, wherein the trace may further include an instruction that is positioned subsequent to the conditional block and has a dependency to at least one of the instructions comprising the conditional block. The trace scheduling compiler method comprises: removing, from the conditional block, at least one of the at least one instructions upon which there is a dependency; adding at least one predicated instruction to the sequence at a position prior to the conditional block, the at least one predicated instruction having a correspondence with the at least one of the at least one instruction removed; and moving the instruction having a dependency to a position prior to the conditional block.

According to another aspect of the present invention, a computer program product is compiled by a trace scheduling computer program compiler that is responsive to a data structure representing a sequence of instructions representing a trace, the trace including instructions comprising a conditional block that represents at least a portion of a control flow construct, wherein the trace may further include an instruction that is positioned subsequent to the conditional block and has a dependency to at least one of the instructions comprising the conditional block. The trace scheduling compiler comprises instructions to carry out the method of: removing, from the conditional block, at least one of the at least one instructions upon which there is a dependency; adding at least one predicated instruction to the sequence at a position prior to the conditional block, the at least one predicated instruction having a correspondence with the at least one of the at least one instruction removed; and moving the instruction having a dependency to a position prior to the conditional block.

According to another aspect of the present invention, a method for use in a compiler of a trace scheduling type is responsive to a data structure representing a sequence of instructions representing a trace, the trace including instructions comprising a conditional block that represents at least a portion of a control flow construct, wherein the trace may further include an instruction that is positioned subsequent to the conditional block and has a dependency to at least one of the instructions comprising the conditional block. The method comprises: scheduling a first instruction, which corresponds to the instruction that has the dependency, for execution prior to the conditional block.

According to another aspect of the present invention, a trace scheduling compiler is responsive to a data structure representing a sequence of instructions representing a trace, the trace including instructions comprising a conditional block representing at least a portion of a control flow construct, wherein the trace may further include an instruction positioned subsequent to the conditional block and has a dependency to at least one of the instructions comprising the conditional block. The trace scheduling compiler schedules a first instruction, which corresponds to the instruction that has the dependency, for execution prior to the conditional block.

According to another aspect of the present invention, a trace scheduling compiler is responsive to a data structure representing a sequence of instructions representing a trace, the trace including instructions comprising a conditional block that represents at least a portion of a control flow construct, wherein the trace may further include an instruction that is positioned subsequent to the conditional block and has a dependency to at least one of the instructions comprising the conditional block. The trace scheduling compiler comprises instructions to carry out the method of: scheduling a first instruction, which corresponds to the instruction that has the dependency, for execution prior to the conditional block.

According to another aspect of the present invention, a trace scheduling compiler is responsive to a data structure representing a sequence of instructions representing a trace, the trace including instructions comprising a conditional block that represents at least a portion of a control flow construct, wherein the trace may further include an instruction that is positioned subsequent to the conditional block and has a dependency to at least one of the instructions comprising the conditional block, the trace scheduling compiler including means for scheduling a first instruction, which corresponds to the instruction that has the dependency, for execution prior to the conditional block.

According to another aspect of the present invention, a computer program is compiled by a trace scheduling compiler method that is responsive to a data structure representing a sequence of instructions representing a trace, the trace including instructions comprising a conditional block that represents at least a portion of a control flow construct, wherein the trace may further include an instruction that is positioned subsequent to the conditional block and has a dependency to at least one of the instructions comprising the conditional block. The trace scheduling compiler method comprises: scheduling a first instruction, which corresponds to the instruction that has the dependency, for execution prior to the conditional block. According to another aspect of the present invention, a computer program product is compiled by a trace scheduling computer program compiler that is responsive to a data structure representing a sequence of instructions representing a trace, the trace including instructions comprising a conditional block that represents at least a portion of a control flow construct, wherein the trace may further include an instruction that is positioned subsequent to the conditional block and has a dependency to at least one of the instructions comprising the conditional block. The trace scheduling compiler comprises instructions to carry out the method of: scheduling a first instruction, which corresponds to the instruction that has the dependency, for execution prior to the conditional block.

According to another aspect of the present invention, a method for use in a compiler of a trace scheduling type is responsive to a data structure representing a sequence of instructions representing a trace, the trace including instructions comprising a conditional block that represents at least a portion of a control flow construct, wherein the trace may further include an instruction that is positioned subsequent to the conditional block and has a dependency to at least one of the instructions comprising the conditional block. The method comprises performing processing to: remove from the conditional block, at least one of the at least one instruction upon which there is a dependency; add at least one predicated instruction to the sequence at a position prior to the conditional block, the at least one predicated instruction having a correspondence with the at least one of the at least one instruction removed; and move the instruction having a dependency to a position prior to the conditional block.

While trace scheduling compilers and methods have, until now, focused on moving the dependent instruction into the conditional block (and subsequent to the instruction upon which there is a dependency) thereby resulting in the need to compensate the off trace, we have determined that the instruction having the dependency can be moved ahead of the conditional block, thereby eliminating the need to compensate the off trace.

One or more embodiments of the present invention may be used to move an instruction that is dependent upon an instruction in a conditional block, without the need to add compensation code to an off trace, thereby avoiding the excessive increase in the amount of memory needed to store and run the program, caused by prior art trace scheduling compilers and methods. Nevertheless, it should be understood that the present invention is not limited to such embodiments, and that there is no requirement that any discussed aspect of the present invention address the drawbacks of the prior art.

Brief Description Of The Drawings

Fig. 1 illustrates a portion of a computer program having a sequence of instructions written in a high-level programming language;

Fig. 2A through 2B is a representation of steps carried out in a first prior art compiler method; Figs. 3 A through 3F, is a representation of steps carried out in a prior art trace scheduling method;

Figs. 4A through 4C, is a representation of steps carried out by a trace scheduling compiler according to a first embodiment of the present invention; and

Figs. 5 A through 5B show the main and off traces after the code motion represented by Figs. 4A through 4C;

Figs. 6 A through 6D, is a representation of steps carried out by a trace scheduling compiler according to a second embodiment of the present invention; and

Figs. 7A through 7D, is a representation of steps carried out by a trace scheduling compiler according to a third embodiment of the present invention.

Detailed Description Figs. 4A through 4C are trace graphs showing a representation of code motion as carried out by a trace scheduling compiler according to one embodiment of the present invention. Referring now to Fig. 4A, a trace graph 68A includes a main trace 64A and an off trace 66 A for the portion of the computer program 20 of Fig 1. Main trace 64A may be selected in any manner including, but not limited to, for example, as described hereinabove with respect to Figs. 3A through 3E. In this embodiment, main trace 64A includes blocks 42, 44A (which includes blocks 48 A, 50) and 56. Off trace 66A includes block 46A. Main trace 64A includes the instruction 34 which is to be moved to an earlier position in the sequence, for example, so that the result of instruction 34 may be available when instruction 36 is to be executed. The instruction 34 is dependent upon the instruction 26, which is positioned in the conditional block 50.

Referring to Fig. 4B, the instruction 26 is removed from the conditional block 50. An instruction 120, having an appropriate predicated form so as to correspond to the instruction 26 removed from the conditional block 50, is added at a position prior to the conditional block 50.

Referring now to Fig. 4C, the instruction 34 is moved to block 42 so as to be positioned between instruction 120 and the conditional block 50. However, because the instruction 34 has not been moved into the conditional block 50, there is no need to add instructions to the off trace 66 A to preserve the desired operation of the program, thereby avoiding the drawback associated with the prior art.

Figs. 5 A and 5B show main trace 64A and off trace 66A after the code motion of Figs. 4B and 4C.

It should be understood that the acts of removing, adding, and moving can be carried out in any order. Thus, although the discussion above mentions removing instruction 26, adding instruction 120, and moving instruction 34, the order is not limited to such. Some embodiments may, for example, use an ordering of: removing instruction 26, moving instruction 34 to a position prior to the conditional block 50, and then adding instruction 120 at a position prior to instruction 34. Of course other orderings may also be used. It should also be understood that, in some embodiments, two or more of these acts may be carried out concurrent with one another.

In some embodiments the acts of removing an instruction from the conditional block and adding an instruction having an appropriate predicated form comprise a) converting the instruction in the conditional block to a predicated form and b) then moving the predicated instruction to a position prior to the conditional block, or a) moving the instruction from the conditional block to a position prior to the conditional block and b) then converting the instruction to a predicated form.

It should be understood that the position of each instruction within a sequence of instructions may be defined in any of various ways including, but not limited to, by a physical ordering of the instructions, by use of pointers that define the position or ordering of the instructions in the sequence, or any combination thereof. Instructions may be removed from the sequence by, for example, physically removing the instructions from a physical ordering, by updating any pointers that may define the position or ordering, or combinations thereof. Similarly, instructions may be added to the sequence by, for example, physically adding the instructions to a physical ordering, updating any pointers that may define the position or ordering of the instructions, or combinations thereof. Instructions may be moved in various ways including, but not limited to, by physically moving the instructions into and/or out of a physical ordering, by updating any pointers that may define the position or ordering of the instructions, or combinations thereof. Instructions may also be moved by for example, removing the instructions and adding corresponding instructions, or any combination of the above. In addition, it should be understood that the phrase "moving an instruction to a position," is not limited to moving the instruction directly to the position but also includes moving the instruction to the position, indirectly.

For example, Figs. 6A through 6D show code motion as carried out by a trace scheduling compiler according to a second embodiment, in which an instruction is moved to a position, indirectly.

Referring now to Fig. 6A, a trace graph 68B includes a main trace 64A and an off trace 66A for the portion of the computer program 20 of Fig 1. As in the first embodiment, main trace 64A may be selected in any manner including, but not limited to, for example, as described hereinabove with respect to Figs. 3A through 3E. Main trace 64 A includes the instruction 34 which is to be moved to an earlier position in the sequence, for example, so that the result of instruction 34 may be available when instruction 36 is to be executed. The instruction 34 is dependent upon the instruction 26, which is positioned in the conditional block 50.

Referring now to Fig. 6B, the trace scheduling compiler moves the instruction 34 into the conditional block 50. The instruction 34 will not be retained in the conditional block 50, as discussed below, and therefore, unlike the code motion of Fig. 3F, there is no need to add an instruction similar to instruction 100 (Fig. 3F) to the off trace (i.e., compensation) to preserve the desired operation of the program.

Referring to Fig. 6C, the instruction 26 is removed from the conditional block 50. An instruction 120 having an appropriate predicated form so as to correspond to the instruction 26 removed from the conditional block 50, is added at a position prior to the conditional block 50. Referring now to Fig. 6D, the instruction 34 is moved to block 42 so as to be positioned between instruction 120 and the conditional block 50. Because the instruction 34 is not retained in the conditional block 50, there is no need to compensate the program by adding instructions to the off trace. That is, there is no need to add an instruction similar to instruction 100 (Fig. 3F), to the off trace 66A. Consequently, if a compensation instruction had been added, it may be deleted.

Figs. 6A through 6D thus demonstrate one example of a compiler method in which the instruction 34 is moved to a position, indirectly, by way of an intermediate position. It should also be recognized that the terms moving, removing and/or adding instructions to a sequence of instructions include not only moving, removing, and/or adding instructions in a data structure representing the sequence of instructions, but also includes creating a target data structure in which the instructions are moved, removed, and/or added, compared to a source data structure. Figs. 7A through 7C show code motion as carried out by a trace scheduling compiler according to a third embodiment in which a target data structure is used.

Referring now to Fig. 7A, a trace graph 68C for a source data structure includes a main trace 64A and an off trace 66A for the portion of the computer program 20 of Fig 1. As in the first embodiment, main trace 64A may be selected in any manner including, but not limited to, for example, as described hereinabove with respect to Figs. 3 A through 3E. In this embodiment, main trace 64A includes blocks 42, 44A (which includes blocks 48A, 50) and 56. Main trace 64A includes the instruction 34 which is to be moved to an earlier position in the sequence, for example, so that the result of instruction 34 may be available when instruction 36 is to be executed. The instruction 34 is dependent upon the instruction 26, which is positioned in the conditional block 50.

Referring now to Fig. 7B, a copy of block 42 (Fig. 7 A) from the source data structure (Fig. 7A) and a copy of the instruction 34 from the source data structure (Fig. 7 A) are stored in a block 142 of a target data structure 140. An instruction 120 having an appropriate predicated form so as to correspond to the instruction 26 in the conditional block 50 of the source data structure (Fig. 7A) is also stored in block 142 of the target data structure 140. Referring now to Fig. 7C, a copy of the block 44 A of the source data structure (Fig. 7A), except for the instruction 26 (Fig. 7A), is stored in a block 144A of the target data structure 140. Block 144A includes a block 148A, which includes the copy of the conditional branch instruction 24A of the block 48 A of the source data structure (Fig. 7A). Block 144 A also includes a conditional block 150, which includes the copy of the conditional block 50 of the source data structure (Fig. 7 A) except for the instruction 26 (Fig. 7A).

Referring now to Fig. 7D, a copy of block 56 of the source data structure (Fig. 7A), except for the instruction 34 (Fig. 7A), is generated and stored in a block 156 of the target data structure 140. Thus, moving, removing and/or adding instructions may be carried out with or without making any modifications to a source data structure, such as in this example simply creating a target data structure with the desired changes (additions, deletions, and movements), compared to the source data structure.

The term "representing a sequence of instructions in a trace" means representing at least a sequence of instructions in a trace so as not to preclude also representing instructions that are not in the trace, for example, instructions forming an off trace.

As used herein, the terms comprising, having, and including are defined as meaning comprising at least, having at least, and including at least, respectively.

A computer program may have any form, including, but not limited to, a sequence of binary values, i.e. a bit string. Furthermore, A computer program may be in one or more high level languages, one or more low level languages, one or more intermediate forms, or any combination thereof. The method and apparatus of the present invention is not limited to use with any particular high level language, any particular low level language, or any particular intermediate language or form, but rather may be used with any type of computer program in any type of computer program language and in any form. Intermediate representation can have any form including, but not limited to, text based (e.g., three address code), graphic based, or combinations thereof. Code motion is typically done on an intermediate representation.

In practice, computer programs often include any number of control flow constructs, including, but not limited to, branches, loops, if-then constructs, if-then-else constructs. Each control flow construct may include one or more instruction blocks. The number of conditional blocks needed to form a control flow construct depends on the type of control flow construct to be formed. For example, a single conditional block and an instruction representing a conditional branch around the conditional block may be used to form an if-then construct. On the other hand, multiple conditional blocks are be needed to form some other control flow constructs. For example, at least two conditional blocks are needed to form an if-then-else construct. One of the conditional blocks forms at least a portion of the if-then portion, while the other of the conditional blocks forms at least a portion of the else-portion of the construct.

It should be understood that various control flow constructs can be represented by if-then or if-then-else constructs. As stated above, although the discussion herein refers to blocks of instructions, we are referring to a way of viewing a computer program to facilitate explanation. It should be understood that trace scheduling may be employed without any express reference to blocks of instructions.

A computer program compiler may be implemented on any type of data processor. For example, the data processor may be programmable or nonprogrammable, general purpose or special purpose, dedicated or non-dedicated, distributed or non-distributed, shared or not shared, or any combination thereof. A data processor may comprise hardware, software, firmware, hardwired circuits or any combination thereof. The compiler may or may not include one or more computer programs with one or^'a plurality of subroutines, or modules, each of which includes a plurality of instructions to be executed by the data processor. If the compiler includes more than one module, then the modules may be parts of one computer program, or may be parts of separate computer programs. The one or more computer programs may or may not be implemented as a computer program product tangibly embodied in a machine-readable storage device for execution by a computer.

Furthermore, a data processor is not limited to a particular computer platform, particular processor, or a particular programming language. Computer programming languages may include, but are not limited to, procedural programming languages, object-oriented programming languages, or combinations thereof. A general purpose computer system may or may not execute a program called an operating system, which may or may not control the execution of other computer programs and may or may not provide scheduling, debugging, input/output control, accounting, compilation, storage assignment, data management, communication control, related services or any combination thereof. In some embodiments, a data processor comprises at least a processing unit connected to a memory system via an interconnection mechanism. A memory system may include a computer-readable and writable recording medium. The medium may or may not be non-volatile. Examples of non-volatile medium include a magnetic disk, a flash memory, and tape. A disk may be removable, known as a floppy disk, or fixed, known as a hard drive. Examples of volatile memory include, but are not limited to, random access memory (RAM), such as a dynamic random access memory (DRAM) or static memory (SRAM), which may or may not be of a type that uses one or more integrated circuits to store information. A variety of mechanisms are known for managing information movement between the disk and an integrated circuit memory element.

While there have been shown and described various embodiments, it will be understood by those skilled in the art that the present invention is not limited to such embodiments, which have been presented by way of example only, and that various changes and modifications may be made without departing from the spirit and scope of the invention. Accordingly, the invention is limited only by the appended claims and equivalents thereto.

What is claimed is:

Claims

1. A method for use in a compiler of a trace scheduling type responsive to a data structure representing a sequence of instructions representing a trace, the trace including instructions comprising a conditional block that represents at least a portion of a control flow construct, wherein the trace may further include an instruction that is positioned subsequent to the conditional block and has a dependency to at least one of the instructions comprising the conditional block, the method comprising: removing, from the conditional block, at least one of the at least one instructions upon which there is a dependency; adding at least one predicated instruction to the sequence at a position prior to the conditional block, the at least one predicated instruction having a correspondence with the at least one of the at least one instruction removed; and moving the instruction having a dependency to a position prior to the conditional block.

2. The method of claim 1 wherein, after adding the at least one predicated instruction and moving the instruction having the dependency, the at least one predicated instruction is positioned prior to the instruction having a dependency.

3. The method of claim 1 wherein the conditional block represents at least a portion of an if-then construct or a portion of an if-then-else construct.

4. The method of claim 1 further comprising retaining the conditional block of instructions.

5. The method of claim 1 wherein the data structure further represents a sequence of instructions in an off trace including instructions representing a second conditional block.

6. The method of claim 5 wherein the first conditional block and the second conditional block represent at least a portion of an if-then-else construct.

7. The method of claim 6 further comprising retaining the if-then-else construct.

8. The method of claim 1 further comprising generating the trace

9. The method of claim 4 further comprising generating the off trace.

10. A trace scheduling compiler that is responsive to a data structure representing a sequence of instructions representing a trace, the trace including instructions comprising a conditional block that represents at least a portion of a control flow construct, wherein the trace may further include an instruction that is positioned subsequent to the conditional block and has a dependency to at least one of the instructions comprising the conditional block, wherein the trace scheduling compiler removes, from the conditional block, at least one of the at least one instruction upon which there is a dependency, the trace scheduling compiler adds at least one predicated instruction to the sequence at a position prior to the conditional block, the at least one predicated instruction having a correspondence with the at least one of the at least one instruction removed, and the trace scheduling compiler moves the instruction having a dependency to a position prior to the conditional block.

11. A trace scheduling compiler responsive to a data structure representing a sequence of instructions representing a trace, the trace including instructions comprising a conditional block that represents at least a portion of a control flow construct, wherein the trace may further include an instruction that is positioned subsequent to the conditional block and has a dependency to at least one of the instructions comprising the conditional block, the trace scheduling compiler comprising instructions to carry out the method of: removing, from the conditional block, at least one of the at least one instructions upon which there is a dependency; adding at least one predicated instruction to the sequence at a position prior to the conditional block, the at least one predicated instruction having a correspondence with the at least one of the at least one instruction removed; and moving the instruction having a dependency to a position prior to the conditional block.

12. A trace scheduling compiler responsive to a data structure representing a sequence of instructions representing a trace, the trace including instructions comprising a conditional block that represents at least a portion of a control flow construct, wherein the trace may further include an instruction that is positioned subsequent to the conditional block and has a dependency to at least one of the instructions comprising the conditional block, the trace scheduling compiler comprising: means for removing, from the conditional block, at least one of the at least one instructions upon which there is a dependency; means for adding at least one predicated instruction to the sequence at a position prior to the conditional block, the at least one predicated instruction having a correspondence with the at least one of the at least one instruction removed; and means for moving the instruction having a dependency to a position prior to the conditional block.

13. A computer program compiled by a trace scheduling compiler method responsive to a data structure representing a sequence of instructions representing a trace, the trace including instructions comprising a conditional block that represents at least a portion of a control flow construct, wherein the trace may further include an instruction that is positioned subsequent to the conditional block and has a dependency to at least one of the instructions comprising the conditional block, the trace scheduling compiler method comprising: removing, from the conditional block, at least one of the at least one instructions upon which there is a dependency; adding at least one predicated instruction to the sequence at a position prior to the conditional block, the at least one predicated instruction having a correspondence with the at least one of the at least one instruction removed; and moving the instruction having a dependency to a position prior to the conditional block.

14. A computer program product compiled by a trace scheduling computer program compiler responsive to a data structure representing a sequence of instructions representing a trace, the trace including instructions comprising a conditional block that represents at least a portion of a control flow construct, wherein the trace may further include an instruction that is positioned subsequent to the conditional block and has a dependency to at least one of the instructions comprising the conditional block, the trace scheduling compiler comprising instructions to carry out the method of: removing, from the conditional block, at least one of the at least one instructions upon which there is a dependency; adding at least one predicated instruction to the sequence at a position prior to the conditional block, the at least one predicated instruction having a correspondence with the at least one of the at least one instruction removed; and moving the instruction having a dependency to a position prior to the conditional block.

15. A method for use in a compiler of a trace scheduling type responsive to a data structure representing a sequence of instructions representing a trace, the trace including instructions comprising a conditional block that represents at least a portion of a control flow construct, wherein the trace may further include an instruction that is positioned subsequent to the conditional block and has a dependency to at least one of the instructions comprising the conditional block, the method comprising: scheduling a first instruction, which corresponds to the instruction that has the dependency, for execution prior to the conditional block.

16. The method of claim 15, further comprising: scheduling a second instruction, which corresponds to the instruction that is in the conditional block and upon which there is the dependency, for execution prior to the first instruction and the conditional block; and predicating the effectiveness of the second instruction on the presence of the specified condition.

17. A trace scheduling compiler that is responsive to a data structure representing a sequence of instructions representing a trace, the trace including instructions comprising a conditional block representing at least a portion of a control flow construct, wherein the trace may further include an instruction positioned subsequent to the conditional block and has a dependency to at least one of the instructions comprising the conditional block, and wherein the trace scheduling compiler schedules a first instruction, which corresponds to the instruction that has the dependency, for execution prior to the conditional block.

18. The trace scheduling compiler of claim 17, wherein the trace scheduling compiler schedules a second instruction, which corresponds to the instruction that is in the conditional block and upon which there is the dependency, for execution prior to the first instruction and the conditional block, and the trace scheduling compiler predicates the effectiveness of the second instruction on the presence of the specified condition.

19. A trace scheduling compiler responsive to a data structure representing a sequence of instructions representing a trace, the trace including instructions comprising a conditional block that represents at least a portion of a control flow construct, wherein the trace may further include an instruction that is positioned subsequent to the conditional block and has a dependency to at least one of the instructions comprising the conditional block, the trace scheduling compiler comprising instructions to carry out the method of: scheduling a first instruction, which corresponds to the instruction that has the dependency, for execution prior to the conditional block.

20. The trace scheduling compiler of claim 19, further comprising instructions to carry out the method of: scheduling a second instruction, which corresponds to the instruction that is in the conditional block and upon which there is the dependency, for execution prior to the first instruction and the conditional block; and predicating the effectiveness of the second instruction on the presence of the specified condition.

21. A trace scheduling compiler responsive to a data structure representing a sequence of instructions representing a trace, the trace including instructions comprising a conditional block that represents at least a portion of a control flow construct, wherein the trace may further include an instruction that is positioned subsequent to the conditional block and has a dependency to at least one of the instructions comprising the conditional block, the trace scheduling compiler including means for scheduling a first instruction, which corresponds to the instruction that has the dependency, for execution prior to the conditional block.

22. The trace scheduling compiler of claim 21 , further comprising: means for scheduling a second instruction, which corresponds to the instruction that is in the conditional block and upon which there is the dependency, for execution prior to the first instruction and the conditional block; and means for predicating the effectiveness of the second instruction on the presence of the specified condition.

23. A computer program compiled by a trace scheduling compiler method responsive to a data structure representing a sequence of instructions representing a trace, the trace including instructions comprising a conditional block that represents at least a portion of a control flow construct, wherein the trace may further include an instruction that is positioned subsequent to the conditional block and has a dependency to at least one of the instructions comprising the conditional block, the trace scheduling compiler method comprising: scheduling a first instruction, which corresponds to the instruction that has the dependency, for execution prior to the conditional block.

24. The computer program of claim 23, wherein the trace scheduling compiler method further comprises: scheduling a second instruction, which corresponds to the instruction that is in the conditional block and upon which there is the dependency, for execution prior to the first instruction and the conditional block; and predicating the effectiveness of the second instruction on the presence of the specified condition.

25. A computer program product compiled by a trace scheduling computer program compiler responsive to a data structure representing a sequence of instructions representing a trace, the trace including instructions comprising a conditional block that represents at least a portion of a control flow construct, wherein the trace may further include an instruction that is positioned subsequent to the conditional block and has a dependency to at least one of the instructions comprising the conditional block, the trace scheduling compiler comprising instructions to carry out the method of: scheduling a first instruction, which corresponds to the instruction that has the dependency, for execution prior to the conditional block.

26. The computer program product of claim 25, wherein the trace scheduling compiler further comprises instructions to carry out the method of : scheduling a second instruction, which corresponds to the instruction that is in the conditional block and upon which there is the dependency, for execution prior to the first instruction and the conditional block; and predicating the effectiveness of the second instruction on the presence of the specified condition.

27. The method of claim 1 wherein the moving the instruction having the dependency is performed after the adding the at least one predicated instruction.

28. The method of claim 1 wherein the adding the at least one predicated instruction is performed after moving the instruction having a dependency.

29. A method for use in a compiler of a trace scheduling type responsive to a data structure representing a sequence of instructions representing a trace, the trace including instructions comprising a conditional block that represents at least a portion of a control flow construct, wherein the trace may further include an instruction that is positioned subsequent to the conditional block and has a dependency to at least one of the instructions comprising the conditional block, the method comprising: performing processing to: remove from the conditional block, at least one of the at least one instruction upon which there is a dependency; add at least one predicated instruction to the sequence at a position prior to the conditional block, the at least one predicated instruction having a correspondence with the at least one of the at least one instruction removed; and move the instruction having a dependency to a position prior to the conditional block.

30. The method of claim 29 wherein, after the at least one predicated instruction is added and the instruction having the dependency is moved, the instruction having a dependency is at a position between the at least one predicated instruction and the conditional block.