WO2002093747A3 - Improved frequency divider with reduced jitter and apparatus based thereon - Google Patents

Improved frequency divider with reduced jitter and apparatus based thereon Download PDF

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Publication number
WO2002093747A3
WO2002093747A3 PCT/IB2002/001745 IB0201745W WO02093747A3 WO 2002093747 A3 WO2002093747 A3 WO 2002093747A3 IB 0201745 W IB0201745 W IB 0201745W WO 02093747 A3 WO02093747 A3 WO 02093747A3
Authority
WO
WIPO (PCT)
Prior art keywords
signal
frequency
mode control
frequency dividing
clock
Prior art date
Application number
PCT/IB2002/001745
Other languages
French (fr)
Other versions
WO2002093747A2 (en
Inventor
Zhenhua Wang
Original Assignee
Koninkl Philips Electronics Nv
Zhenhua Wang
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Zhenhua Wang filed Critical Koninkl Philips Electronics Nv
Priority to US10/477,983 priority Critical patent/US6842054B2/en
Priority to JP2002590506A priority patent/JP2005508577A/en
Priority to EP02769540A priority patent/EP1490973A2/en
Publication of WO2002093747A2 publication Critical patent/WO2002093747A2/en
Publication of WO2002093747A3 publication Critical patent/WO2002093747A3/en

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K23/00Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
    • H03K23/667Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by switching the base during a counting cycle

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

Apparatus (70) for generating an output signal (fdiv) whose frequency is lower than the frequency of an input signal (CK1). The apparatus (70) comprises a chain of frequency dividing cells (71-76), wherein each of the frequency dividing cells (71-76) has a predefined division ratio and comprises a clock input (Cki) for receiving an input clock (Ckin); a divided clock output (Cki+1) for providing an output clock (Ckout) to a subsequent frequency dividing cell; a mode control input (Mki) for receiving a mode control input signal (Mdin) from the subsequent frequency dividing cell; and a mode control output for providing a mode control output signal (Mdout) to a preceding frequency dividing cell. The apparatus further comprises a latch (77) for altering the division ration and - a D-Flip-Flop (50) circuitry with two latches (51, 52). The first latch (51) is clocked by a first signal (CK3) and the second latch (52) is clocked by a second signal (CK1), whereby the frequency of the first signal (CK3) is lower than the frequency of the second signal (CK1).
PCT/IB2002/001745 2001-05-17 2002-05-17 Improved frequency divider with reduced jitter and apparatus based thereon WO2002093747A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US10/477,983 US6842054B2 (en) 2001-05-17 2002-05-17 Frequency divider with reduced jitter and apparatus based thereon
JP2002590506A JP2005508577A (en) 2001-05-17 2002-05-17 Frequency divider improved to reduce jitter and apparatus based thereon
EP02769540A EP1490973A2 (en) 2001-05-17 2002-05-17 Improved frequency divider with reduced jitter and apparatus based thereon

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP01112125 2001-05-17
EP01112125.8 2001-05-17

Publications (2)

Publication Number Publication Date
WO2002093747A2 WO2002093747A2 (en) 2002-11-21
WO2002093747A3 true WO2002093747A3 (en) 2004-10-21

Family

ID=8177460

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2002/001745 WO2002093747A2 (en) 2001-05-17 2002-05-17 Improved frequency divider with reduced jitter and apparatus based thereon

Country Status (5)

Country Link
US (1) US6842054B2 (en)
EP (1) EP1490973A2 (en)
JP (1) JP2005508577A (en)
CN (1) CN1269311C (en)
WO (1) WO2002093747A2 (en)

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JP4386725B2 (en) * 2001-08-29 2009-12-16 エヌエックスピー ビー ヴィ Improved frequency divider with reduced jitter and transmitter based thereon
DE10251703B4 (en) * 2002-11-06 2005-08-04 Infineon Technologies Ag Circuit arrangement for frequency division and phase locked loop with the circuit arrangement
US6836169B2 (en) * 2002-12-20 2004-12-28 Cypress Semiconductor Corporation Single ended clock signal generator having a differential output
CN1697324B (en) * 2004-05-10 2010-04-07 华为技术有限公司 Method and device for redlization of debouncing for transmission signal
US7061286B2 (en) * 2004-06-24 2006-06-13 Teradyne, Inc. Synchronization between low frequency and high frequency digital signals
WO2006016312A1 (en) * 2004-08-06 2006-02-16 Koninklijke Philips Electronics N.V. Frequency divider
US7173470B2 (en) * 2005-03-11 2007-02-06 Analog Devices, Inc. Clock sources and methods with reduced clock jitter
US7403048B2 (en) * 2005-06-01 2008-07-22 Wilinx Corporation Divider circuits and methods using in-phase and quadrature signals
US7298183B2 (en) * 2005-06-01 2007-11-20 Wilinx Corp. High frequency divider circuits and methods
US7532065B2 (en) * 2005-07-12 2009-05-12 Agere Systems Inc. Analog amplifier having DC offset cancellation circuit and method of offset cancellation for analog amplifiers
US7560957B2 (en) * 2005-07-12 2009-07-14 Agere Systems Inc. High-speed CML circuit design
US7388406B2 (en) * 2005-07-12 2008-06-17 Agere Systems Inc. CML circuit devices having improved headroom
US7336114B2 (en) * 2006-04-05 2008-02-26 Wionics Research High-speed latching technique and application to frequency dividers
US7924069B2 (en) * 2006-06-28 2011-04-12 Qualcomm Incorporated Multi-modulus divider retiming circuit
US8081018B2 (en) * 2008-08-21 2011-12-20 Qualcomm Incorporated Low power radio frequency divider
EP2363952A1 (en) 2010-03-02 2011-09-07 Nxp B.V. Methods and systems for generating local oscillator signals
US8248118B2 (en) * 2010-08-09 2012-08-21 Texas Instruments Incorporated High-speed frequency divider and a phase locked loop that uses the high-speed frequency divider
US8406371B1 (en) * 2012-01-04 2013-03-26 Silicon Laboratories Inc. Programmable divider circuitry for improved duty cycle consistency and related systems and methods
KR101453015B1 (en) 2013-01-25 2014-10-22 (주)에프씨아이 Extended mult-modulus divider
US9118333B1 (en) * 2013-08-29 2015-08-25 Integrated Device Technology Inc. Self-adaptive multi-modulus dividers containing div2/3 cells therein
US20190379359A1 (en) * 2018-06-08 2019-12-12 Nxp B.V. Frequency division circuitry and methods
CN109586716A (en) * 2018-11-30 2019-04-05 新奥科技发展有限公司 Phase frequency divider and radio-frequency power system
CN110739963B (en) * 2019-10-23 2021-09-10 西安电子科技大学 GaAs pHEMT 2/3 dual-mode frequency division circuit
US11632119B1 (en) * 2022-04-25 2023-04-18 Cadence Design Systems, Inc. Programmable fractional ripple divider
US11955982B2 (en) * 2022-06-29 2024-04-09 Ati Technologies Ulc Granular clock frequency division using dithering mechanism
CN116647233B (en) * 2023-05-18 2024-04-02 成都电科星拓科技有限公司 Multimode frequency divider, phase-locked loop and chip for reducing phase difference of different frequency division ratios

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DE10013633A1 (en) * 2000-03-18 2001-09-20 Inst Halbleiterphysik Gmbh Static frequency divider with switchable division ratio prevents metastable states using two D=type flip-flops with alternately activatable inputs

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Non-Patent Citations (4)

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Title
CHEN W-Z ET AL: "A 2-V, 1.8-GHZ BJT PHASE-LOCKED LOOP", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE INC. NEW YORK, US, vol. 34, no. 6, June 1999 (1999-06-01), pages 784 - 789, XP000913032, ISSN: 0018-9200 *
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Also Published As

Publication number Publication date
US6842054B2 (en) 2005-01-11
US20040140831A1 (en) 2004-07-22
WO2002093747A2 (en) 2002-11-21
CN1269311C (en) 2006-08-09
EP1490973A2 (en) 2004-12-29
JP2005508577A (en) 2005-03-31
CN1593008A (en) 2005-03-09

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