WO2002089913A2

WO2002089913A2 - Fully implantable cochlear implant system and electronic circuits therefor

Info

Publication number: WO2002089913A2
Application number: PCT/GB2002/002030
Authority: WO
Inventors: Christofer Toumazou; Julius Georgiou
Original assignee: Toumaz Technology Limited
Priority date: 2001-05-05
Filing date: 2002-05-03
Publication date: 2002-11-14
Also published as: GB0111267D0; WO2002089913A3

Abstract

A cochlear implant system for implanting into a user, the system comprising a microphone, signal processing means for converting a signal output from the microphone into a set of signals having different centre frequencies, electrodes for stimulating neurons in the cochlear, and signal distribution means for distributing the set of signals to the electrodes, the microphone, signal processing means, signal distribution means and electrodes all being implantable, wherein the signal processing means is configured to provide an output which will be acceptable to some users, and the implant is further provided with means for receiving a signal generated by an external microphone and external signal processing means, the implantable system being provided with control means operative to pass the externally generated signal to the signal distribution means.

Description

ELECTRONIC CIRCUIT

The present invention relates to electronic circuits, and particularly though not exclusively to one or more electronic circuits included in or suitable for inclusion in a cochlear implant hearing aid system.

Cochlear implants induce hearing in persons who are profoundly deaf, and are also used in persons for which conventional hearing aids provide inadequate improvement to residual hearing. The majority of cases of severe hearing loss or profound deafness arise when the sensitivity of the cochlea in the internal ear is reduced due to loss of hair cells [1].

Figure la illustrates schematically the human hearing system. In a healthy hearing system, sound vibrates the eardrum, which is mechanically coupled to the stapes, an ossicle that exerts pressure on a membrane covering an opening in the cochlea, called the oval window. The cochlear chamber is a spiralling chamber which is partitioned along its length into two main fluid filled sub-chambers known as the scala tympani and the scala vestibuli.

A cross-sectional view of the .cochlear chamber is shown in figure lb. It can be seen in figure lb that the scala vestibuli and scala typmani sub-chambers are separated by a membrane, known as the basilar membrane. The thickness of the basilar membrane is not constant, but instead reduces gradually from a maximum at the outer end of the cochlear to a minimum at the centre of the cochlear. The pressure transmitted via the oval window into one of the sub-chambers couples into the other sub-chamber by flexing the basilar membrane. A given frequency will induce movement of the basilar membrane at -the particular location which is' most susceptible to movement at that frequency. In this way pressure waves (i.e. sound) is separated in frequency to provide movement of different locations of the basilar membrane. The locations at which different frequencies ^' induce movement of the basilar membrane is shown schematically in figure 2. Referring again to figure lb, movements of the basilar membrane are transduced into electrical signals in the auditory nerve, by hair cells situated in a structure on the basilar membrane called the organ of corti.

Hearing loss in the majority of cases can be attributed to either a problem in the mechanical coupling from the eardrum to the oval window, or to damage of hair cells in the cochlea. In the first case, classified as conducting hearing loss, surgery can sometimes partially rectify the problem and with some assistance from a conventional hearing aid, some hearing can be restored. In the second case, classified as sensorineural hearing loss, the restoration of the auditory path can only be achieved by electrical stimulation of nerves, via an electrode array, usually inserted in the Scala Tympani. The electrode array provides stimulation of nerves in a pattern which is calculated to provide a patient with hearing which represents sounds detected by a microphone. To do this, detected sounds are separated into frequency bands, each of which is used to activate a different electrode. The acoustical dynamic range of detected sounds is mapped to the electrical dynamic range of a particular patient's nervous system. Systems which provide these functions are known as cochlear implant devices, although it will be appreciated that in the vast majority of known devices signal processing is carried out externally of a patients body.

There are numerous prior art cochlear implant systems. Early single channel/electrode systems, for example as described in U.S. Pat. No. 3,751,605 and U.S. Pat. No. 3,752,939 have been superseded by multi-channel/multi electrode systems which provide greatly improved speech perception (see for example U.S. Patents: 4,284,856; 4,617,913; 4,918,745; 5,271,397; 5,549,658; 5,569,307; 5,603,726; 5,601,617; 5,776,172; 5,824,022; 5,938,691; 5,983,139; 6,002,066.)

The common elements found in all prior art multi-channel systems include the following:

1) An external (i.e. not implanted) speech-processing unit that converts an acoustic input into an electrical signal and further manipulates this into a processed signal, the processed signal being intended to increase speech intelligibility. -

2) A means of transmitting the processed signal from the external speech processing unit to an implanted device. The transmitting means can take various forms, such as a "through the skin" connector, by mutual induction between an implanted and an external coil, by radio frequency coupling, or even by infrared transmission.

3) A means of transmitting power to the implanted device. In common with the signal transmitting means, this can take various forms such as a "through the skin" connector or by mutual induction. It is not uncommon for the power and data transfer to share the same link.

4) An implanted receiver/stimulator unit

Numerous stimulation strategies have been developed for the speech-processing units of cochlear implants. State of the art strategies are: the Continuous Interleaved Sampling (CIS) strategy, the N of M strategy and the Simultaneous Analog Stimulation (SAS) strategy. Especially good results in terms of speech understanding have been shown for the majority of the users using CIS, or N of M strategy.

The trend in terms of the size of the external processor has been downward for obvious reasons related both, to practical and also psychological effects on the user. In addition the size of the implanted part has reduced, providing additional benefits in terms of surgical factors. Current state of the art external processors are sufficiently small to be worn behind the ear, although processors of this size generally have reduced computational abilities in comparison tσ larger body worn processors.

Further miniaturisation of the external processor whilst retaining the main processing capabilities is difficult using a purely digital signal processing solution. An alternative solution would be to use low power analog circuits, which would allow the size and power consumption of the processor to be reduced significantly. A disadvantage of the analog approach is that analog circuits systems are much less re- configurable than digital systems. This means that, whilst it may be possible to provide an analog system which provides a majority of patients with acceptable hearing using circuits which provide one or two commonly appropriate neuron stimulation strategies, the analog ^' system will not have the flexibility needed to provide the acceptable hearing for a minority of patients who have other

Purely analog systems are described in U.S. Patents 4,400,590 and 4,617,91. Early prior art systems contain components that are too large and power hungry to implant such as large resistors and potentiometers that cannot be put on a single chip. The neuron stimulation strategies used by these implants are also outdated. More recent prior art in which analog weak inversion FET solutions are proposed^' [2, 3] are incomplete and lacking critical components for a feasible single chip, system level, implementation. In addition they do not provide for an alternative more flexible system, capable of implementing strategies needed for difficult cases.

It is an object of the present invention to provide one or more circuits suitable for use in a cochlear implant, the circuits may together or separately address some of the above problems.

According to the invention there is provided a cochlear implant system for implanting into a user, the system comprising a microphone, signal processmg means for converting a signal output from the microphone into a set of signals having different centre frequencies, electrodes for stimulating neurons in the cochlear, and signal distribution means for distributing the set of signals to the electrodes, the microphone, signal processing means, signal distribution means and electrodes all being implantable, wherem the signal processing means is configured to provide an output which will be acceptable to some users, and the implant is further provided with means for receiving a signal generated by an external microphone and external signal processing means, the implantable system being provided with control means operative to pass the externally generated signal to the signal distribution means.

Suitably, the control means is arranged to monitor the receiving means to determine whether a signal is being received. Suitably, the receiving means comprises a transcutaneous inductive link.

Suitably, the external processor is a digital processor which may be programmed in accordance with the requirements of a given user.

Suitably, the external processor is a hybrid digital-analogue processor which may be programmed in accordance with the requirements of a given user.

The invention also provides a cochlear implant system for implanting into a user, the system comprising a microphone, signal processmg means for converting a signal output from the microphone into a set of signals having different central frequencies, electrodes for stimulating neurons in the cochlear, and signal distribution means for distributing the set of signals to the electrodes, the microphone, signal processing means, signal distribution means and electrodes all being implantable, wherein the signal processing means is configured to operate in an analog current processing mode.

The invention also provides a circuit which converts a voltage signal to- a current signal, the circuit comprising a differential pair which generates an output current including an ac signal that is substantially proportional to an ac voltage input signal, the output current of the differential pair further including an unwanted dc current component which is dependent upon the ac-gain provided by the differential pair, wherein the circuit is provided with a current mirror which operates to significantly reduce or eliminate the ac gain dependent dc current component by subtracting it from the output current at an output node.

Suitably, the circuit is provided with a dc bias current source, the dc bias current being used to determine how much dc component should be retained to bias the ac signal current. Suitably, the differential pair comprises a pair of transistors.

Suitably, the transistors are field effect transistors, and are biased to operate in the weak inversion region.

Suitably, the transconductance gain of the differential pair is adjusted by adjusting the tail current.

Suitably, the voltage to current conversion circuit forms part of a cochlear implant.

The invention also provides a filter stage for converting an input signal into a set of signals having different centre frequencies, the filter stage comprising a plurality of filters each arranged to output a signal with a different centre frequency, wherein one or more of the filters is biased with a first bias current, and one or- more of the remaining filters is biased with a second different bias current, the bias currents being x selected in combination with capacitances of the filters to provide required centre frequencies.

Suitably, the filters are constructed using field effect transistors operating in the weak inversion region.

Suitably, the first bias current is lower than the second bias current, and is provided to one or more filters with centre frequencies that are lower than the centre frequencies of the one or more remaining filters.

Suitably, more than two bias currents are provided.

Suitably, one or more of the bias currents may be adjusted, thereby adjusting the centre frequencies of the filters to which those bias currents are provided.

Suitably, the adjustment of the bias currents is used to move the central frequencies of the filters towards frequencies which carry useful speech information. Suitably, the set of signals output from the filter stage are passed to a clipping detection circuit which is arranged to determine whether any of the signals are suffering from clipping.

Suitably, the filter stage forms part of a cochlear implant.

The invention also provides a clipping detection circuit comprising a signal current ^• input, a current mirror which mirrors the signal current to a node, and a current source arranged to draw double an appropriate bias- current from the node such that the node provides an output voltage when the signal current exceeds current drawn by the current source, the output voltage indicating that clipping of the signal current is occurring.

Suitably, the signal current input comprises a signal output from the filter stage, and the clipping detection circuit controls the transconductance gain of the voltage to current conversion circuit.

Suitably, the output voltage is passed to an input of a counter which decrements in response to the output voltage, the output of the counter passing to a digital to analogue converter which reduces the transconductance gain of the voltage to current conversion circuit in accordance with the output of the counter.

Suitably, the number of decrements of the counter is limited.

Suitably, a clock is connected to a second input of the counter which increments in response to the clock voltage, the output of the counter passing to the digital to analogue converter which increases the transconductance gain of the voltage to current conversion circuit in accordance with the output^'of the counter.

Suitably, the second input of the counter is allowed once the counter has ceased to decrement. Suitably, the second input of the counter is allowed a predetermined period of time after the counter began to decrement.

The invention also provides a rectification circuit comprising a first current mirror arranged to copy an input signal to provide two input signals, a differential pair arranged to invert a first input signal, a second current mirror arranged to output to a node only positive phases of the first input signal, and a third current mirror arranged to output to the node only positive phases of the second input signal, an output from the rectification circuit being taken from the node.

Suitably, the input signal is inverted prior to copying by the first current mirror.

Suitably, the rectification circuit is provided with a bias current source arid a fourth current mirror which mirrors the bias current such that the bias current is drawn from a node to which the first input signal is provided, thereby removing an unwanted bias current from the first input signal.

Suitably, the rectification circuit is provided with a bias current source and a fifth current mirror which mirrors the bias current such that the bias current is drawn from a node to which the second input signal is provided, thereby removing an unwanted bias current from the second input signal.

Suitably, the current mirrors are formed from field effect transistors biased to operate in the weak inversion region.

Suitably, the rectification circuit forms part of a cochlear implant.

The invention also provides a current gain circuit comprising two field effect transistors (FET's) connected in series between a voltage source and a current signal input, the FET's being biased to operate in the weak inversion region, and a third FET connected between the voltage source and a current signal output point, wherein the gate^'s of the first and third FET's are connected together such that the third FET is biased to operate in the strong inversion region, thereby providing an output current signal which is at least an order'of magnitude greater than the current input signal.

Suitably, the output current signal is approximately three orders of magnitude greater than the current input signal.

Suitably, a capacitor is connected between the gates of the first and third FET's and the voltage source, the capacitance of the capacitor and the output resistances of the first and second FET's together determining the frequency response of the circuit.

Suitably, the capacitance of the capacitor is selected such that the cut-off frequency of the circuit is 600Hz or less.

Suitably, the circuit provides a compression which is approximately a 4^th root compression.

Suitably, the current gain circuit forms part of a cochlear implant.

The invention also provides a current gain circuit comprising two bipolar transistors connected in series between a voltage source and a current signal input, and a third field effect transistor connected between the voltage source and a current signal output point, wherein the gates of the first and third transistors are connected- together thereby providing an output current signal which is at least an order of magnitude greater than the current input signal.

Suitably, a capacitor is connected between the gates of the first and third transistors and the voltage source, the capacitance of the capacitor and the output resistances of the first and second transistors together determining the frequency response of the circuit. A specific embodiment of the invention will now be described by way of example only with reference to the accompanying figures, in which:

Figure la is a schematic illustration of the anatomy of the human ear;

Figure lb is a schematic cross-sectional illustration of the cochlea of the human ear;

Figure 2 is a schematic illustration of the locations at which acoustic frequencies induce movement of the basilar membrane of the cochlear; Figure 3 is a schematic illustration of a cochlear implant system which embodies the invention; Figure 4 is a further schematic illustration of a cochlear implant system which embodies the invention; Figure 5 is a schematic illustration of a voltage to current conversion circuit of the cochlear implant system Figure 6 is a schematic illustration of a filter of the cochlear implant system; Figure 7 is a schematic illustration of a clipping detection circuit of the cochlear implant system Figure 8 is a schematic illustration of a rectifier circuit of the cochlear implant system; Figure 9 is a graph which illustrates operation of the rectifier circuit of figure 8; Figure 10 is a schematic illustration of a combined gain, compression and filter circuit of the cochlear implant system ; Figure 11 is a graph which illustrates operation of the circuit of figure 10; and Figure 12 is a further illustration of the cochlear implant system chip layout.

The electric circuits which embody the invention may be used as stages of cochlear implant hearing aid system (the system as a whole may embody some aspects of the invention). The cochlear implant system is fully implantable (i.e. does not require external processing systems), has very low power requirements and operates in the current mode. In order to keep the power requirements low the implant uses predominantly analog processing.

The cochlear implant system is represented schematically in figure 3 as a series of stages. The first stage of the system is microphone 1 which detects an audio signal and outputs a voltage signal representative of the audio signal. In common with the other stages of the system the microphone is implanted. A suitable microphone such as the commercially available electret microphone Knowles FG-3329 is appropriately packaged in biocompatible material such that its acoustic properties are more or less maintained. An additional advantage of having an implanted microphone rather than an external microphone is that it does not suffer from wind noise.

A voltage to current conversion stage 2 converts the voltage signal output by the microphone to a current signal. The use of a current signal is preferred as compared to the use of a voltage signal because a current signal is ultimately required to stimulate the cochlear, and the conversion to current signal is more easily carried out prior to processing than after processing.

•The current signal is output to a set of filters 3 which separate the signal into a set of filtered, signals centred on different frequencies: The filters 3 provide feedback to an automatic gain control stage 4 which controls the gain of the current conversion stage 2. The automatic gain control stage 4 is operative to temporarily reduce the gain of the current conversion stage when it is determined that clipping of one or more of the filtered signals is occurring.

The filtered signals are passed to a rectifier stage 5 which removes bias current from the filtered signals, and provides full wave rectification of the filtered signals.

The rectified signals are passed to a combined current compression, gain and low pass filtering stage 6. This gain provided by this stage converts the rectified signals, which are of the order of nA's to signals suitable for stimulating neurons, a current of the order of μA's. The current compression provided by the stage reflects the logarithmic response of neurons to stimulation, by applying a 4^th root compression. The low pass filter is set at around 400Hz.

The remaining stages of the cochlear implant are generally the same as is used in prior art implants, i.e. an offset and gain stage 7 which can be adjusted in consultation with a patient after fitting of the implant, a Continuous Interleaved Sampling (CIS) signal generation stage 8, which generates pulses of current in accordance with an input current signal, and a set of sixteen electrodes 9 to which the pulses of current are passed. The electrodes 9 are located in the cochlear, and stimulate neurons in the cochlear thereby providing the patient with hearing.

The cochlear implant system uses ultra low power CMOS technology. Figure 4 shows schematically the specific setup of stages 2 to 6 of a sixteen channel embodiment of the system. The low power processor includes a voltage and current reference subsystem 11 and a low battery voltage monitor 12. There are a variety of known low power,- low current reference circuits which can be used for the voltage and current reference 11. In this embodiment, a peaking reference is used since it is more robust in terms of power supply rejection ratio (PSRR). The low battery voltage monitor 12 has the function of turning off all circuitry (also the electrode driving circuits via pin 12a) with the exception of the data setting register, so as to prevent the battery from being damaged by excessive discharge. Low power battery voltage monitors are well known in the art.

Stages 2 to 6 of the system, as described in relation to figure 3, are separated into first and second parallel parts. The first parallel part 13, 14 includes filter stages for the eight lowest frequency bands, and is provided with a lOnA bias. The second parallel part 15, 16 includes filter stages for the eight highest frequency bands, and is provided with a 50nA bias. The reasoning behind the use of different bias currents is to do with preserving the required dynamic range for the system. In general there are two ways of tuning log-domain filters: one method is to adjust the bias currents and another method is to adjust the size of the filtering capacitors. In general in the past it has been seen as much more convenient to tune currents. However, since the dynamic range of weak inversion operation is limited, the embodiment of the invention achieves the logarithmic distribution of filter frequencies in the audio band with capacitor scaling. Since the higher frequencies in speech have a lower power-content, the dynamic range of the higher frequencies is increased by increasing the bias current for the filter stages for the eight highest frequency bands. Because a lower current is used for the low frequency filters, the surface areas of the capacitors of the filters is correspondingly reduced. The power consumption of the low frequency filters is also reduced.

The microphone (not shown in figure 4) is supplied with power from the voltage and current reference subsystem 11 via a conductive connection 11a. A voltage signal representing acoustical information is passed via connections 13a, 15a to the voltage to current conversion stages which are included to the parallel parts 13, 15. Output from the parallel parts 14, 16, which comprises μA current signals are output via connections 14a, 16a (a different connection is provided for each frequency band signal).

Those stages of the cochlear implant system which embody inventions will now be described in detail. Stages of the system which comprise known prior art are not described in detail.

The filter stage 3 comprises log domain bandpass filters which operate in the current mode, and require an input comprising an ac- current signal riding on a dc bias current equivalent to the bias current of the filter. The voltage to current conversion stage 2 used to provide the required input is based on a differential pair, which when operated in the weak inversion region has a transconductance of g_m= Wn^"Vτ where I_taii is the differential pair's tail current, n is the sub-threshold parameter and^'Vr is the thermal voltage. It will be noted that increasing the tail current increases the transconductance g_m, and the gain provided by the voltage to current conversion stage 2 is thereby increased. The ac current signal generated by the differential pair is superimposed on half the tail current, and it is necessary to subtract this from the signal, so that the tail current is not included in the input to the bandpass filters.

Referring to figure 5, the voltage to current conversion stage is constructed using FET's which are biased to operate in the weak inversion region. The weak inversion region is preferred to the strong inversion region because it provides a better transconductance and has a lower power consumption. The voltage _. to current conversion stage includes a differential pair 20 comprising a first FET 21 and a second FET 22. A voltage signal representing acoustical information riding on a DC bias voltage (i.e. the output of the microphone) is connected to the gate of the first FET 21. A DC voltage is connected to the gate of the second FET 22. The current drawn through the second FET 22 is I_taii/2 + I_ac, where I_ac comprises a current signal representing the acoustical information, and I_tau is the current provided at the tail of the differential pair 20.

The transconductance gain of the differential amplifier is determined by the tail current 1^. The tail current is controlled by a current source 49 which provides a current _ai_n. The current I_gaj_n is determined by the automatic gain control stage 4 shown schematically in figure 3. Two copies of I_gai_n are made, by a first current mirror 32 comprising three FET's 33-35; these copies of I_gai_n are given the designation I_taiV2 in figure 5. I_taii_/2 is copied by a second current mirror 28 comprising three FETS's 29- 31 which is arranged to double the current to provide I_taji which is drawn from the tail of the differential pair 20. In this manner the gain of the differential pair 20 is controlled by the current source 49.

The current Itail/2 provided by the first current mirror 32 is fed to a node A.

A third current mirror 23 comprising four FET's 24-27 is connected to the right hand side of the differential pair.20 (i.e. connected to the drain of FET 22). The current mirror 23 provides a current of 1^ 2 + I_ac to a node B.

A bias current I_bi_as, which is required for the input of the bandpass filters, is generated by a current source 36. A fourth current mirror 37 comprising a pair of FET's 38, 39 is connected to the current source, and draws a current I i_as from the node A. Node A comprises three connections. The first connection is provided with a current W2 by the¹ first current mirror 32, and a current I^_as is drawn from the second connection. It- follows from Kirshoff's current law that the current passing from the third connection of the node A is I_taii/2 - I i _s • The current 1^/2 - I i_as passes from the node A to a fifth current mirror 40 comprising four FET's -41-44. The fifth current mirror 40 draws a current 1,^/2 - I_bias from the node B.

The Node B has three connections. A current I_taii/2 + I_a is provided to the node B by the third current mirror 23. A current I_tau/2 - I_bi_as is drawn from the node B by the fifth ^■ current mirror 40. From Kirshoff s current law it can be seen that the current passing from the third connection of node B is I_taii/2 + I_ac - (Itau 2 - I ias) = I ias+Iac- This is the input that is required by the bandpass filters. The current I_bia_s+I_ac is passed to the input of each filter of the filter stage (only one filter is shown in figure 5).

The voltage to current conversion stage shown in figure 5 provides variable-ac-gaiή (via adjustment of the current I_gai_n provided by the current source 49) together with a fixed dc-bias. The stage may be used in any suitable application area, and is not limited to cochlear implants. Variations of the voltage to current conversion stage could include, a complementary implementation, use of different current mirrors to reduce the copying error and techniques to increase the output resistance etc.

The current I i_as+I_ac generated by the voltage to current conversion stage is copied into sixteen signals, and fed into sixteen bandpass filters (the filter stage), representative of different frequency bands. The bandpass filters are second order log domain bandpass filters, each of which is centred at a different frequency. The central frequencies of the filters are spaced over the band 300Hz to 6300Hz in equal log increments as set out below:

The 3dB points of adjacent bands are set to be approximately equal. The Q of each filter^' is approximately 5. The frequency band over which the filters extend, 300Hz to 6300Hz, is used because it provides good quality hearing. It has previously been shown that adequate hearing may be provided by a band having an uppermost frequency restricted to 3500Hz. It will be appreciated that and suitable frequency band may be selected by suitable modification of the filter, and that similarly any suitable frequency spacing between the filters may be selected.

Each filter provides an output signal which is ultimately used to excite a particular electrode located in the cochlear, as described in more detail further below. It will be appreciated that even if the outermost three electrodes (the highest frequency electrodes) are not successfully implanted in the cochlear, a patient should still receive sufficient information to provide adequate hearing (i.e. a frequency band of 300-3500Hz).

A schematic illustration of one of the filters comprising the filter stage is shown in figure 6. The filter comprises a second order log domain circuit implemented with FET devices biased in the weak inversion region. These are used instead of conventional linearised circuits because they do not incur a power overhead for linearisation. Because the filters operate in the current mode they provide very good high frequency performance.

The filter comprises first and second non-inverting cells 50, 51 and first and second inverting cells 52, 53 (filters of this type are described in [4] and [5]). An input signal comprising the current Ibi_as+Iac is introduced via an FET 54, and a bandpass output signal l_ou_t is obtained from an FET 55. The centre frequency of the filter is determined by the time required for capacitors d and C₂ to charge, which in turn is determined by their capacitances and the by the bias current provided via the bias cell 61. As mentioned above, the eight lowest frequency band filters are provided with a lOnA bias, and the eight highest frequency band filters are provided with a 50nA bias.

The filter includes state elimination circuitry 56 which is arranged to constrain the filter such that it has only one stable operating point. The state elimination circuitry comprises an FET 57 for selectively sinking current into capacitor C₂ and a voltage comparator 58 which is configured to drive the FET 57 when voltage -Vci exceeds a predetermined threshold voltage, which in the present, embodiment is 3.2V. The FET 57 is switched on to sink current into the capacitor C₂. Current is sunk into the capacitor C₂ until voltage Vci is below the threshold voltage 3.2V.

If several electrodes of the cochlear implant are not successfully implanted in ^'the cochlear, for example if only eight electrodes are successfully implanted, then the central frequencies of the filters may be adjusted after the implant is fitted in order to maximise the useful information provided to the patient. Usually, it is the low frequency electrodes are successfully implanted. In this example this means that some of the higher frequency bands which carry important speech information, for example 1580Hz - 2810Hz, are lost. The centre frequencies of all of the filters are moved upwards, by adjusting the bias current applied provided by the bias cell 59. This upward movement of the central frequencies of the filters allows the most important part of audio information to be passed to the electrodes that have successfully been implanted. Some low frequency information will be lost so as to centre the available electrode's frequencies, onto the most important band for speech recognition.

The filters are all adjusted together, an adjustment typically reducing the central frequency of each filter by around 10%. More than one adjustment may be made. Referring to figure 4, the adjustment is made using inputs 19. It will be appreciated that, since the bias currents provided to the eight lower frequency filters and the eight higher frequency filters are different, they may be adjusted independently thereby providing independent adjustment of the central frequencies for each set of eight filters.

The filter includes a circuit that detects clipping of the output signal I_out- The output signal I_0ttt from the FET 55 is mirrored by a current mirror comprising FET 55 and a further FET 60. The FET 60 provides a copy of the output signal I_out to a node C. A current source 61 draws twice the nominal bias current from the node C. When the output signal I_out exceeds twice the nominal bias current, the voltage at the node C goes high. The high voltage V_cι indicates that clipping of the signal generated by the filter is occurring (i.e. the output current of a filter exceeds twice the bias current).

The output 62 of the clipping detection circuit is passed to the automatic gain control stage which reduces the gain of the voltage to current conversion stage so that clipping is eliminated. The automatic gain control stage is separated into two parts which operate in parallel, one for the eight lowest frequency band filters and one for the eight highest frequency band filters. The automatic gain control stage for the eight lowest frequency band filters is shown schematically in figure 7 (the other is identical).

^' Referring to figure 7, each filter has an output 62 which goes high when clipping of the output signal from that filter occurs. All of the outputs 62 from the eight lower frequency filters are passed to an OR gate 63 having a single output. The output from the OR gate is fed back to a 4-bit digital counter 70. The sound which produces the output current that exceeds twice the nominal bias current is likely to have an associated frequency. This means that the clipping output 62 is likely to carry a series of pulses. Each time a pulse is received at the 4-bit digital counter 70, the number output from the digital counter is stepped down by one binary increment (the initial output of the 4-bit counter is llll). The number output by the counter 70 is passed to a digital-to-analog (D/A) converter 72. The output from the D/A converter determines the gain of the V to I conversion circuit shown in figure 5. The gain is stepped down in increments determined by the output of the D/A converter until clipping output 62 ceases to go high, or until the gain has been reduced to its minimum (the maximum number of steps is sixteen, leading to an output of 0000 from the 4-bit counter).

A glitch filter (not shown) with a time constant of around 60ms is included in the automatic gain control stage so that the gain of the voltage to current conversion stage is not changed instantaneously (for example as the result of a power supply glitch). Once it has been determined that clipping of the filter output has ceased (i.e. when no more pulses are generated on the clipping output 62), the gain of the voltage to current conversion stage is incremented. The incrementation of the gain is controlled by inputting pulses to the counter 70. The pulses are generated by a clock, the output frequency of which is around 83Hz. This provides full recovery of the gain, i.e. 16 output steps, in around 200ms. _r

The positioning of the feedback for the gain control, at the output of the filters, is advantageous- because it allows 2^nd order band-pass filters to be used instead of 4^X order band-pass filters, as are commonly used in current state of the art cochlear implants. As mentioned above, the approximate quality factor of the filters is about 5, and consequently there is an inherent gain in the filters. Detecting clipping at the output reduces the output error by the gain of the filter.

The signals output by the filters are passed to the rectifier stage which is constructed from FET's operating in the weak inversion region. Figure 8 shows schematically a circuit which produces a full wave rectified copy of an input signal, and hard limits the output current to the allowable signal value. The output_. current I ia_s + lac-_f from the filter is connected to a node D, which is also connected to a left hand side of a current mirror 101 which draws 2I_bi_as (the right hand side of the current mirror 101 is connected to a current source 102. which provides I_bi_as)- From Kirshoff's current law it is apparent that the current drawn through the third connection of the node D is as- I_ac-f. The maximum current that can be drawn through the third connection of the node is limited to 2I_bi_as (this occurs when I_ac.f = -Ibias)- The current I ias- Iac-f is drawn through the left hand side of a current mirror 103 which mirrors the current I_Di_as- Iac-f to a node E.

A current source 104 pulling I i_as s connected to node E. From Kirshoff's current law it is apparent that the current passed to the third connection of the node E is -I_ac-f- This current is passed to a current mirror 105 configured to mirror only the positive phases of -I_ac-f. In other words, half wave rectification of the current -I_ac-_f is carried out. A current mirror 106 is arranged to direct a copy of I_bi_asTac-f towards the left hand side of a differential pair 107. A current source 108 of value 2I_bi_as is connected to the tail of a differential pair 107. The current drawn through the right hand side of the differential pair is consequently 2I_bi_as - (Ibias - Iac-f ), which is Ibi _s+ - This current is mirrored by a current mirror 109, and is thereby passed to a node F.

A current source 110 pulling I_bias is connected to node F, and the output of node F is thus + I_ac-_f. current mirror 111 is configured to mirror only positive phases of + I_ac- f-

The current mirrors 105 and 111 are both connected to node G which provides the output of the rectification stage.

Figure 9 shows a simulation of the effect of a large amplitude 5kHz input signal.- The uppermost graph of figure 9 shows the signal prior to being input to the filter stage. The second graph shows the output of the 5.120kHz filter, which is oscillating. The automatic gain control stage is turned off. The outputs of the current mirrors 105 and 111 of the rectification stage are shown in the third and fourth graphs, and the output from the node G is shown in the fifth graph. It can be seen that the outputs of the current mirrors 105, 111 and the output taken from the node G are limited to 50nA.

The rectified signal I_aC-f-r is passed to a combined current compression, gain and low pass filtering stage. The stage is shown schematically in Figure 10.

The stage is based upon a current mirror comprising three FET's 302-304. First and second FET's 302, 303 are connected together in series between the input 301 (which carries I_ac-f-_r) and a voltage rail. The gate of the first FET 302 is connected to the gate of the third FET 304 which is connected between the voltage rail and the output. A capacitor 305 is connected between the gates of the first and third FET's 302, 304 and the voltage rail. The arrangement of the FET's 302-304 is such that the voltage between the gate and the source of the third FET 304 is twice the voltage between the gate and the source of the first FET 302. This means that the first^' FET 302 is operating in the weak inversion region whilst the third FET 304 is in strong inversion. The consequence of this difference is that the current provided by the third FET 304 is orders of magnitude larger than that provided at the first FET 302. The current provided by the third FET 304, L.c-f-_r-g» is taken from an output 306. Typically, the input current I_ac-f-r is stepped up from nA to μA, the order of magnitude necessary for stimulation of neurons (currents of μA orders of magnitude are not used during processing because they will lead to a far greater power consumption).

As mentioned previously, the circuit provides 4^th root compression of the current. The 4^th root compression arises from the fact that the first and second FET's 302, 303 are operating in the weak inversion region whilst the third FET 304 is in strong inversion. The compression is required so that linear increases of sound volume when converted to electrical signals provide a roughly linearly perceived sound for a patient (the compression is 4^th root compression).

It will be appreciated that it may be possible to use other suitable components in place of the FET's. Where this is done the compression provided will be different.

The capacitor 305 together with the output resistance of the first and second FET's 302, 303 determine the RC characteristic of the circuit. Typically, the value of the capacitor is chosen such that the cut-off frequency of the circuit is around 400Hz.

The AC response and DC response of the combined current compression, gain and low pass filtering stage are shown in figure I

The signal output from the compression stage is converted into biphasic pulses which is passed to electrodes in the cochlear to stimulate neurons. The manner in which the electrodes are turned on and off can be selected from one of several known stimulation strategies. In addition, in common with known implants, the biphasic pulses are mapped onto the patients dynamic range by adjusting threshold and gain settings in consultation with the patient. The stimulation strategy may be Continuous Interleaved Sampling (CIS) strategy or N of M strategy. In the CIS strategy M out of M electrodes are fired non-simultaneously, whilst in the N of M strategy only the strongest N of the M channels are fired non-simultaneously. If necessary all 16 channels can be fired at the same time but this will in general increase power consumption of the implant to non sustainable levels, and unwanted electrode interactions occur; this is called a Simultaneous Analog Stimulation (SAS) strategy.

Interleaved Sampling (CIS) strategy or N of M strategy. In the CIS strategy only one electrode at a time is fired, whilst in the N of M strategy only the strongest N of the M channels are used. If necessary all 16 channels can be fired at the same time but this will in general increase power consumption of the implant to non sustainable levels. Simultaneous Analog Stimulation (SAS) strategy may be used.

The part of the implant which provides the stimulation strategy is separated from the analog processing stages described above. This is to avoid unwanted interference between the two parts. The separation is shown schematically as a broken line X in figure 1, and is also indicated by connectors in figure 4. The separation is preferably provided by locating a heavily doped semiconductor region which is connected to ground. The separation may be provided by an air gap, although this may make the system a little fragile since bonding wires would be required to cross the gap.

The cochlear implant system provides threshold and gain adjustment following fitting. The system also allows the centre frequencies of the filters to be shifted, which is useful in transferring important acoustical information to active electrodes in situations where not all electrodes have been successfully implanted. These adjustments provide a sufficient level of patient-to-patient adjustment to accommodate the needs of the majority of the patients. Thus, the system can be implanted, adjusted, and then simply left alone. A primary advantage of the system from a patient's point of view is that it is completely implanted and therefore does not restrict the patient's lifestyle. The system is powered by a battery (not shown in the figures) which must be periodically charged. Charging is preferably provided via a transcutaneous inductive link.

The adjustments provided by the cochlear implant system may be insufficient in some instances to meet the needs of a patient, for example where that the patient has few surviving neurons, or when bone growth has occurred in the cochlear. Where this is the case the invention allows the analog processing part of the system to be bypassed, with the stimulation part of the system being connected directly to an external digital processor. The external digital processor may be programmed to provide a signal which reflects the needs of the patient.. The external digital processor transmits both power and stimulation data via a transcutaneous inductive link.

Figure 12 illustrates schematically an embodiment of the invention which includes the above described cochlear implant system, and an external part. The implanted system is shown in box 400, and the external part is shown in box 401. The external part 401 includes a microphone 402, a digital signal processor 403 and an induction coil 404. The implanted system includes the stages described above, together with an induction coil 405, a power and data receiver 406 and a data flow and operating mode controller 407. The data flow and operating mode controller 407 is configured to direct the digitally processed signal direct to electrode drivers 408, bypassing the analog signal processing stages.

The embodiment of the invention shown in figure 11 provides full flexibility, since it allows a fully implantable system to be implanted in a patient, and in the event that the analog signal processing provided by the fully implanted system is not sufficient, allows an external digital signal processor to be added.

Where digital signal processing is not required, the induction coils 404. 405 are used to input power to the implanted system 400, and thereby charge a rechargeable battery 409. Variations of the system could include moving more flexible signal processing capabiiities into the implant by adding further features to the internal processor, and when operating with a more power hungry strategy e.g. SAS instead of CIS, employing an external device such as a discreet external battery and power transmitter in order to top up the power needs of the implanted system. Without the external link it is unlikely the power stored would be adequate to drive a large number of electrodes at the same time.

An advantage of the invention, which stems from the fact that it may be operated in as a fully implanted system is- that the usual bottleneck, i.e. the passage of data via a transcutaneous inductive link, is avoided.

An advantage of the invention which stems from the fact that it uses analog processing is that the trade-off between update rate and resolution which is usually seen in conventional cochlear implant systems is avoided (in conventional systems the more frequency bands that are added to the implant, the longer the duration between updates). Since the invention uses analog processing, information in analog channels is continuous and is not limited by a filter update rate. Consequently, there is no conflict between the number of active electrodes (spectral detail) and channel envelope resolution (temporal detail).

It will be appreciated that in the embodiments of the invention pmos devices may be replaced by nmos devices without affecting the operation of the embodiments (the connections are turned 'upside down').

The term 'node' as used above is intended to mean a point at which more than two conductive connections are made, and is not intended to imply any particular voltage or current at that point. REFERENCES

1. Chapter 3 of Niparko J.K. et al "Cochlear Implants: Principles & Practices", ISBN: 0781717825.

2. Toumazou C, Nargamil I and Lande TS "Micropower log-domain filter for electronic' cochlea" Electronic letters, Vol 30, No 22, ppl839-1841, 1994.

3. Wang R, Sarpeshkar R et al "A Low Power Analog Front End Module for Cochlear Implants", presented at XVI World Congress on Otolaryngology, Sydney, March 1997.

4. Frey DR "Exponential state space filters: a generic current mode design strategy" IEE Trans. CAS I, vol. 43, pp. 32-34, lanuary 1996.

5. R.M. Fox and M. Nagarajan, "Multiple Operating Points in Log-Domain ^' Filters", Proc. ISCAS ^"'99, 1999, vol. 2, pp689-92.

Claims

1. A cochlear implant system for implanting into a user, the system comprising a microphone, signal processing means for converting a signal output from the microphone into a set of signals having different central frequencies, electrodes for stimulating neurons in the cochlear, and signal distribution means for distributing the set of signals to the electrodes, the microphone, signal processing means, signal distribution means and electrodes all being implantable, wherein the signal processing means is configured to provide an output which will be acceptable to some users, and the implant is further provided with means for receiving a signal generated by an external microphone and extemal signal processing means, the implantable system being provided with control means operative to pass the externally generated signal to the signal distribution means. _.

2. A cochlear implant system according to claim 1, wherein the control means is arranged to monitor the receiving means to determine whether a signal is being received.

3. A cochlear implant system according to claim 1 or claim 2, wherein the receiving means comprises a transcutaneous inductive link.

4. A cochlear implant system according to any of claims 1 to 3, wherein the external signal processing means is a digital processor which may be programmed in accordance with the requirements of a given user.

5. A cochlear implant system according to any of claims l_. to 3, wherein the external signal processing means is a hybrid digital-analogue processor which may be programmed in accordance with the requirements of a given user.

6. A cochlear implant system for implanting into a user, the system comprising a microphone, signal processing means for converting a signal output from the microphone into a set of signals having different central frequencies, electrodes for stimulating neurons^' in the cochlear, and signal distribution means for distributing the set of signals to the electrodes, the microphone, signal processing means, signal distribution means and electrodes all being implantable, wherein the signal processing means is configured to operate in an analog current processing mode.

7. A circuit which converts a voltage signal to a current signal, the circuit comprising a differential pair which generates an output current including an ac signal that is substantially proportional to an ac voltage input signal, the output current of the differential pair further including an unwanted dc current component which is dependent upon the ac-gain provided by the differential pair, wherein the circuit is provided with a current mirror which operates to significantly reduce or eliminate the ac gain dependent dc current component by subtracting it from the output current at an output node.

8. A circuit according to claim 7, the circuit is provided with a dc bias current source, the dc bias current being used to determine how much dc component should be retained to bias the ac signal current.

9. A circuit according to claim 7 or claim 8, wherein the differential pair comprises a pair of transistors.

10. A circuit according to claim 9, wherein the transistors are field effect transistors, and are biased to operate in the weak inversion region.

11. A circuit according to any of claims 7 to 10, wherein the transconductance gain of the differential pair is adjusted by adjusting the tail current.

12. A circuit according to any of claims 7 to 11, wherein the voltage to current conversion circuit forms part of a cochlear implant.

13. A filter _. stage for converting an input signal into a set of signals having different central frequencies, the filter stage comprising a plurality of filters each arranged to output a signal with a different central frequency, wherein one or more of the filters is biased with a first bias current, and one or more of the remaining filters is biased with a second different bias current, the bias currents being selected in combination with capacitances of the filters to provide required central frequencies.

14. A filter stage according to claim 13, wherein the filters are constructed using - field effect transistors operating in the weak inversion region.

15. A filter stage according to claim 13 or claim 14, wherein the first bias current is lower than the second bias current, and is provided to one or more filters with centre frequencies that are lower than the central frequencies of the one or more remaining filters.

16. A filter stage according to any of claims 13 to 15, wherein more than two bias currents are provided.

17. A filter stage according to any of claims 13 to 16, wherein one or more of the bias currents may be adjusted, thereby adjusting the central frequencies of the filters to which those bias currents, are provided.

18. A filter stage according to .claim 17, wherein the adjustment of the bias currents is used to move the central frequencies of the filters towards frequencies which carry useful speech information.

19. A filter stage according to any of claims 13 to 18, wherein the set of signals output from the filter stage are passed to a clipping detection circuit which is arranged to determine whether any of the signals are suffering from clipping.

20. A filter stage according to any of claims 13 to 19 wherein the filter stage forms part of a cochlear implant.

21. A clipping detection circuit comprising a signal current input, a current mirror which mirrors the signal current to a node, and a current source arranged to draw double an appropriate bias current from the node such that the node provides an output voltage when the signal current exceeds current drawn by the current source, the output voltage indicating that clipping of the signal current is occurring.

22. A circuit comprising the clipping detection circuit according to claim 21, together with a circuit which converts a voltage signal to a current signal, and a filter stage, the conversion circuit comprising a differential pair which generates an output current including an ac signal that is substantially proportional to an ac voltage input signal, the output current of the differential pair further including an unwanted dc current component which is dependent upon the ac-gain provided by trie differential pair, the conversion circuit being provided with a current mirror which operates to significantly reduce or eliminate the ac gain dependent dc current component by subtracting it from the output current at an output node, the filter stage comprising a plurality of filters each arranged to output a signal with a different central frequency, one or more of the filters being biased with a first bias current, and one or more of the remaining filters is biased with a second different bias current, the bias currents being selected in combination with capacitances of the filters to provide required central frequencies, wherein the signal current input comprises a signal output from the filter stage, and the clipping detection circuit controls the transconductance gain of the voltage to current conversion circuit.

23. A clipping detection circuit according to claim 22, wherein the output voltage is passed to an input of a counter which decrements in response to the output voltage, the output of the counter passing to a digital to analogue converter which reduces the transconductance gain of the voltage to current conversion circuit in accordance with the output of the counter.

24. A clipping detection circuit according to claim 23, wherein the number of decrements of the counter is limited.

25. A clipping detection circuit according to claim 23 or claim 24, wherein a clock is connected to a second input of the counter which increments in response to the clock voltage, the output of the counter passing to the digital to analogue converter which increases the transconductance gain of the voltage to current conversion circuit in accordance with the output of the counter.

26. A clipping detection circuit according to claim 25, wherein the second input of the counter is allowed once the counter has ceased to decrement.

27. A clipping detection circuit according to claim 25, wherein the second input of the counter is allowed a predetermined period of time after the counter began to decrement.

28. A rectification circuit comprising a first current mirror arranged to copy an input signal to provide two input signals, a differential pair arranged to invert a first input signal, a second current mirror arranged to output to a node only positive phases of the first input signal, and a third current mirror arranged to output to the node only positive phases of the second input signal, an output from the rectification circuit being taken from the node.

29. A rectification circuit according to claim 28, wherein the input^, signal is inverted prior to copying by the first current mirror.

30. A rectification circuit according to claim 28 or claim 29, wherein the rectification circuit is provided with a bias current source and a fourth current mirror which mirrors the bias current such that the bias current^' is drawn from a node to which the first input signal is provided, thereby removing an unwanted bias current from the first input signal.

31. A rectification circuit according to any of claims 28 to 30, wherein the rectification circuit is provided with a bias current source and a fifth current mirror which mirrors the bias current such that the bias current is drawn from a node to which the second input signal is provided, thereby removing an unwanted bias current from the second input signal.

^'32. A rectification circuit according to any of claims 28 to 31, wherein the current mirrors are formed from field effect transistors biased to operate in the weak inversion region.

33. A rectification circuit according to any of claims 28 to 32, wherein the rectification circuit forms part of a cochlear implant.

34. A current gain circuit comprising two field effect transistors (FET's) connected in series between a voltage source and a current signal input, the FET's being biased to operate in the weak inversion region, and a third FET connected between the voltage source and a current signal output point, wherein the gates of the first and third FET's are connected together such that the third FET is biased to operate in the strong inversion region, thereby providing an output current signal which is at least an order of magnitude greater than the current input signal.

35. A current gain circuit according to claim 34, wherein the Output current signal is approximately three orders of magnitude greater than the current input signal.

36. A current gain circuit according to claim 34 or claim 35, wherein a capacitor is connected between the gates of the first and third FET's and the voltage source, the capacitance of the capacitor and the output resistances of the first and second FET's together determining the frequency response of the circuit.

37. A current gain circuit according to claim 36, wherein the capacitance of the capacitor is selected such that the cut-off frequency of the circuit is 600Hz or less.

38. A current gain circuit according to any of claims 34 to 37, wherein the circuit provides a compression which is approximately a 4^th root compression.

39. A current gain circuit according to any of claims 34 to 38, wherein the current gain circuit forms part of a cochlear implant.

40. A current gain circuit comprising two bipolar transistors connected in series between a voltage source and a current signal input, and a third field effect transistor connected between the voltage source and a current signal output point, wherein the gates of the first and third transistors are connected together thereby providing an output current signal which is at least an order of magnitude greater than the current input signal.

41. A current gain circuit according to claim 39, wherein a capacitor is connected between the gates of the first and third transistors and the voltage source, the capacitance of the capacitor and the output resistances of the first and second transistors together determining the frequency response of the circuit.

42. A cochlear implant system substantially as hereinbefore described with reference to the accompanying figures.