WO2002089256A1

WO2002089256A1 - Reconfigurable artificial magnetic conductor

Info

Publication number: WO2002089256A1
Application number: PCT/US2002/013542
Authority: WO
Inventors: William E. Mckinzie, Iii; Victor C. Sanchez; Mark Reed; Steven L. Garrett
Original assignee: E-Tenna Corporation
Priority date: 2001-04-30
Filing date: 2002-04-30
Publication date: 2002-11-07

Abstract

An electronically reconfigurale artificial magnetic conductor (RAMC) includes a frequency selective surface (FSS) having an effective sheet capacitance which is variable to control resonant frequency of the RAMC(1600). In one embodiment, the RAMC (1600) further includes a conductive backplane structure and a spacer layer (1604) separating the conductive backplane structure and the FSS(1602). The spacer layer (1604) includes conductive vias (1608) extending between the conductive backplane structure and the FSS (1602), and voltage variable capacitive circuit elements coupled with the FSS (1602) and responsive to bias voltages applied on one or more bias signal lines routed through the conductive backplane structure and the conductive vias (1608). In another embodiment, the RAMC (1600) includes a FSS (1602) and including a periodic pattern of bias node patches alternating with ground node patches, the ground node patches being in electrical contact with respective vias of the plurality of vias (1608), and components between selected bias node patches and ground node patches, the components having a capacitance which is variable in response to a bias voltage. A network of bias resistors between adjacent bias node patches provides the tuning voltage.

Description

RECONFIGURABLE ARTIFICIAL MAGNETIC CONDUCTOR

BACKGROUND

The present invention relates to the development of reconfigurable artificial magnetic conductor (RAMC) surfaces for low profile antennas. This device operates as a high-impedance surface over a tunable frequency range, and is electrically thin relative to the frequency of interest, λ.

A high impedance surface is a lossless, reactive surface, realized as a printed circuit board, whose equivalent surface impedance is an open circuit which inhibits the flow of equivalent tangential electric surface currents, thereby approximating a zero tangential magnetic field. A high-impedance surface is important because it offers a boundary condition which permits wire antennas (electric currents) to be well matched and to radiate efficiently when the wires are placed in very close proximity to this surface (<λ/100 away). The opposite is true if the same wire antenna is placed very close to a metal or perfect electric conductor (PEC) surface. It will not radiate efficiently. The radiation pattern from the antenna on a high-impedance surface is confined to the upper half space above the high impedance surface. The performance is unaffected even if the high-impedance surface is placed on top of another metal surface. The promise of an electrically-thin, efficient antenna is very appealing for countless wireless device and skin-embedded antenna applications.

One embodiment of a thin, high-impedance surface 100 is shown in FIG. 1. It is a printed circuit structure forming an electrically thin, planar, periodic structure, having vertical and horizontal conductors, which can be fabricated using low cost printed circuit technologies. The high-impedance surface or artificial magnetic conductor (AMC) 100 includes a lower permittivity spacer layer 104 and a capacitive frequency selective surface (FSS) 102 formed on a metal backplane 106. Metal vias 108 extend through the spacer layer 104, and connect the metal backplane to the metal patches of the FSS layer. The thickness of the high impedance surface 100 is much less than λ/4 at resonance, and typically on the order of λ/50, as is indicated in FIG. 1.

The FSS 102 of the prior art high impedance surface 100 is a periodic array of metal patches 110 which are edge coupled to form an effective sheet capacitance. This is referred to as a capacitive frequency selective surface (FSS).

Each metal patch 110 defines a unit cell which extends through the thickness of the high impedance surface 100. Each patch 110 is connected to the metal backplane 106, which forms a ground plane, by means of a metal via 108, which can be plated through holes. The spacer layer 104 through which the vias 108 pass is a relatively low permittivity dielectric typical of many printed circuit board substrates. The spacer layer 104 is the region occupied by the vias 108 and the low permittivity dielectric. The spacer layer is typically 10 to 100 times thicker than the FSS layer 102. Also, the dimensions of a unit cell in the prior art high- impedance surface are much smaller than λ at the fundamental resonance. The period is typically between λ/40 and λ/ 12.

Another embodiment of a thin, high-impedance surface is disclosed in U.S. patent application serial number 09/678,128, entitled "Multi-Resonant, High- Impedance Electromagnetic Surfaces," filed on October 4, 2000, commonly assigned with the present application and incorporated herein by reference. In that embodiment, an artificial magnetic conductor is resonant at multiple resonance frequencies. That embodiment has properties of an artificial magnetic conductor over a limited frequency band or bands, whereby, near its resonant frequency, the reflection amplitude is near unity and the reflection phase at the surface lies between +/- 90 degrees. At the resonant frequency of the AMC, the reflection phase is exactly zero degrees. That embodiment also offers suppression of transverse electric (TE) and transverse magnetic (TM) mode surface waves over a band of frequencies near where it operates as a high impedance surface.

Another implementation of a high-impedance surface, or an artificial magnetic conductor (AMC), which has nearly an octave of +/- 90° reflection phase, was developed under DARPA Contract Number F19628-99-C-0080. The size of this exemplary AMC is 10 in. by 16 in by 1.26 in thick (25.4 cm x 40.64 cm x 3.20 cm). The weight of the AMC is 3 lbs., 2oz. The 1.20 inch (3.05 cm) thick, low permittivity spacer layer is realized using foam. The FSS has a period of 298 mils (0.757 cm), and a sheet capacitance of 0.53 pF/sq. The FSS substrate had a thickness of .060 inches, and was made using Rogers R04003 material. The

FSS was fabricated using two layers of metallization, where the overlapping patches were essentially square in shape.

The measured reflection coefficient phase of this broadband AMC, referenced to the top surface of the structure is shown in FIG. 2 as a function of frequency. A ±90° phase bandwidth of 900 MHz to 1550 MHz is observed.

Three curves are traced on the graph, each representing a different density of vias within the spacer layer. For curve AMC 1-2, one out of every two possible vias is installed, and only the upper patches are connected to the vias. For curve AMC1- 4, one out of every four vias is installed. In this case, only half of the upper patches are connected to vias, and the patches connected form a checkerboard pattern. For curve AMCl-18, one out of every 18 vias is installed. In this third case, only one in every 9 of the upper patches has an associated via. As expected from the effective media model described in application serial number 09/678,128, the density of vias does not have a strong effect on the reflection coefficient phase. Transmission test set-ups are used to experimentally verify the existence of a surface wave bandgap for this broadband AMC. In each case, the transmission response (S₂₁) is measured between two Nivaldi-notch radiators that are mounted so as to excite the dominant electric field polarization for transverse electric (TE) and transverse magnetic (TM) modes on the AMC surface. For the TE set-up, the antennas are oriented horizontally. For the TM set-up, the antennas are oriented vertically. Absorber is placed around the surface-under-test to minimize the space wave coupling between the antennas. The optimal configuration - defined empirically as "that which gives the smoothest, least-noisy response and cleanest surface wave cutoff - is obtained by trial and error. The optimal configuration is obtained by varying the location of the antennas, the placement of the absorber, the height of absorber above the surface-under-test, the thickness of absorber, and by placing a conducting foil "wall" between layers of absorber to mitigate free space coupling between test antennas. The measured S₂₁ for both configurations is shown in FIG. 3. As can be seen, a sharp TM mode cutoff occurs near 950 MHz, and a gradual TE mode onset occurs near 1550 MHz. The difference between these two cutoff frequencies is referred to as a surface wave bandgap. This measured bandgap is correlated closely to the +/- 90-degree reflection phase bandwidth of the AMC illustrated in FIG. 2.

The resonant frequency of the prior art AMC, shown in FIG. 1, is given by Sievenpiper et. al. (IEEE Trans. Microwave Theory and Techniques, Vol. 47, No.

11, Nov 1999, pp. 2059-2074), (also see "High Impedance Electromagnetic Surfaces," dissertation of Daniel F. Sievenpiper, University of California at Los

Angeles, 1999) as f₀ = l/(2π fLC) where is the equivalent sheet capacitance of the FSS layer in Farads per square, and L = μ₀h is the permeance of the spacer layer, with h denoting the height or thickness of this layer.

In most wireless communications applications, it is desirable to make the antenna ground plane as small and light weight as possible so that it may be readily integrated into physically small, light weight platforms such as radiotelephones, personal digital assistants and other mobile or portable wireless devices. The relationship between the instantaneous bandwidth, BW, of an AMC with a non-magnetic spacer layer and its thickness is given by

where λ₀ is the free space wavelength at resonance where a zero degree reflection phase is observed. Thus, to support a wide instantaneous bandwidth, the AMC thickness must be relatively large. For example, to accommodate an octave frequency range (BW/f₀ = 0.667), the AMC thickness must be at least 0.106 λ₀, corresponding to a physical thickness of 1.4 inches at a center frequency of 900 MHz. This thickness is too large for many practical applications.

Accordingly, there is a need for an AMC which allows for a larger reflection phase bandwidth for a given AMC thickness.

BRIEF SUMMARY

The present invention provides a means to electronically adjust or tune the resonant frequency, f₀ , of an artificial magnetic conductor (AMC) by controlling the effective sheet capacitance C of its FSS layer.

By way of introduction only, one present embodiment provides an artificial magnetic conductor (AMC) which includes a frequency selective surface (FSS) having an effective sheet capacitance which is variable to control the resonant frequency of the AMC.

Another embodiment provides an AMC which includes a frequency selective surface (FSS), a conductive backplane structure, and a spacer layer separating the conductive backplane structure and the FSS. The spacer layer includes conductive vias extending between the conductive backplane structure and the FSS. The AMC further includes voltage variable capacitive circuit elements coupled with the FSS and responsive to one or more bias signal lines routed through the conductive backplane structure and the conductive vias. Another embodiment provides an AMC which includes a frequency selective surface (FSS) including a periodic array of conductive patches, a spacer layer including vias extending therethrough in association with predetermined conductive patches of the FSS, and a conducting backplane structure including two or more bias signal lines. The FSS is characterized by a unit cell which includes, in a first plane, a pattern of three or more conductive patches, one conductive patch of which is electrically coupled with an associated conductive via, and voltage variable capacitive elements between laterally adjacent conductive patches. In a second plane, the FSS is characterized by a conductive backplane segment extending in a plane substantially parallel to a plane including the three or more conductive patches and the associated conductive via extending from the one conductive patch to one of the two or more bias signal lines.

Another embodiment provides an AMC which includes a frequency selective surface (FSS) including a periodic array of conductive patches, a spacer layer including vias extending therethrough in association with predetermined conductive patches of the FSS, and a conducting backplane structure including two or more bias signal lines. The FSS is characterized by a unit cell which includes, in a first plane, a pattern of three or more conductive patches disposed on a first side of a dielectric layer, each conductive patch being electrically coupled with an associated conductive via, and voltage variable capacitive elements between laterally adjacent conductive patches. Each conductive patch overlaps at least in part a spaced conductive patch of a plurality of spaced conductive patches disposed on a second side of the dielectric layer. In a second plane, a conductive backplane segment extends in a plane substantially parallel to a plane including the three or more conductive patches and the associated conductive vias extending from the each conductive patch to one of the two or more bias signal lines. Another embodiment provides a method for reconfiguring an AMC including a frequency selective surface (FSS) having a pattern of conductive patches, a conductive backplane structure and a spacer layer separating the FSS and the conductive backplane structure. The method comprises applying control bias signals to voltage variable capacitive elements associated with the FSS; and thereby, reconfiguring the effective sheet capacitance of the FSS.

Another present embodiment provides an AMC which includes a frequency selective surface (FSS) including a single layer of conductive patches, with one group of conductive patches electrically coupled to a reference potential and a second group of conductive patches forming bias nodes. The FSS further includes voltage variable capacitive elements coupling patches of the one group of conductive patches with patches of the second group and decoupling resistors between the patches of the second group. Another embodiment provides an AMC which includes a ground plane, a spacer layer disposed adjacent the ground plane and a plurality of vias in electrical contact with the ground plane and extending from a surface of the ground plane in direction of the spacer layer. The AMC further includes a FSS disposed on the spacer layer and including a periodic pattern of bias node patches alternating with ground node patches. The ground node patches are in electrical contact with respective vias of the plurality of vias. The AMC further includes components between selected bias node patches and ground node patches, the components having a capacitance which is variable in response to a bias voltage. The AMC still further includes a network of bias resistors between adjacent bias node patches. Another embodiment provides an AMC which includes a means for forming a backplane for the AMC and a FSS including means for varying capacitance of the FSS. The AMC further includes a spacer layer separating the means for forming a back plane and the FSS. The spacer layer includes a plurality of vias extending substantially normal to the FSS. Another embodiment provides an AMC including a FSS including a ferroelectric thin film, a first layer of conductive patches on one side of the ferroelectric thin film, and a second layer of conductive patches on a second side of the ferroelectric film. The patches of the second layer overlapping at least in part patches of the first layer. The AMC further includes a spacer layer including first vias associated with patches of the first layer and second vias associated with patches of the second layer and a backplane conveying bias signals to the first vias and the second vias.

Still another embodiment provides an artificial magnetic conductor (AMC) which includes a frequency selective surface (FSS) having a pattern of conductive patches, a conductive backplane structure, and a spacer layer separating the FSS and the conductive backplane structure. The spacer layer includes conductive vias associated with some but not all patches of the pattern of conductive patches to create a partial forest of vias in the spacer layer.

The foregoing summary has been provided only by way of introduction. Nothing in this section should be taken as a limitation on the following claims, which define the scope of the invention. BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS FIG. 1 is a perspective view of a prior art high impedance surface; FIG. 2 illustrates measured reflection coefficient phase of a non- reconfigurable high-impedance surface;

FIG. 3 illustrates transmission response for a high-impedance surface; FIG 4 is a top view of one embodiment of a reconfigurable artificial magnetic conductor;

FIG. 5 is a cross sectional view taken along line A-A in FIG. 4; FIG. 6 is a top view of a second embodiment of a reconfigurable artificial magnetic conductor;

FIG. 7 illustrates reflection phase measurements for a reconfigurable artificial magnetic conductor in accordance with one embodiment of the present invention; FIG. 8 is a plot of measured TE and TM mode surface wave transmission for a physical embodiment of the reconfigurable artificial magnetic conductor of FIG. 6 with a bias voltage of 50 V;

FIG. 9 is a plot of measured TE and TM mode surface wave transmission for a physical embodiment of the reconfigurable artificial magnetic conductor of FIG. 6 with a bias voltage of 20 V;

FIG. 10 is a plot of measured TE and TM mode surface wave transmission for a physical embodiment of the reconfigurable artificial magnetic conductor of FIG. 6 with a bias voltage of 0 V;

FIG. 11 is a top view of a third embodiment of a reconfigurable artificial magnetic conductor;

FIG. 12 is a cross sectional view taken along line A-A in FIG. 11; FIG. 13 is a top view of another embodiment of a frequency selective surface for use in a reconfigurable artificial magnetic conductor;

FIG. 14 is a top view of another embodiment of a frequency selective surface for use in a reconfigurable artificial magnetic conductor; FIG. 15 is a side view of the frequency selective surface of FIG. 14;

FIG. 16 is a cross sectional view of a prior art artificial magnetic conductor;

FIG. 17 is a cross sectional view of a first embodiment of an artificial magnetic conductor with a reduced number of vias in the spacer layer; and

FIG. 18 is a cross sectional view of a second embodiment of an artificial magnetic conductor with a reduced number of vias in the spacer layer;

FIG. 19 is a top view of the prior art artificial magnetic conductor of FIG. 16; FIG. 20 is a top view of the first embodiment of the artificial magnetic conductor of FIG. 17;

FIG. 21 is a top view of the second embodiment of the artificial magnetic conductor of FIG. 18;

FIG. 22 is a top view of an alternative embodiment of the artificial magnetic conductor of FIG. 18; and

FIG. 23 is a top view of another alternative embodiment of the artificial magnetic conductor of FIG. 18.

FIG 24 is a top view of one embodiment of a reconfigurable artificial magnetic conductor; FIG. 25 is a cross sectional view taken along line A-A in FIG. 24;

FIG. 26 is a top view of a second embodiment of a reconfigurable artificial magnetic conductor;

FIG. 27 is a cross sectional view taken along line A-A in FIG. 26;

FIG. 28 is a top view of a third embodiment of a reconfigurable artificial magnetic conductor;

FIG. 29 is a cross sectional view taken along line A-A in FIG. 28;

FIG. 30 is a top view of an alternate embodiment of a reconfigurable artificial magnetic conductor;

FIG. 31 is a cross sectional view taken along line A-A in FIG. 30; FIG. 32 is a top view of an alternate embodiment of a reconfigurable artificial magnetic conductor; FIG 33 is a cross sectional view taken along line A-A in FIG. 32;

FIG. 34 is a top view of an alternate embodiment of a reconfigurable artificial magnetic conductor; and

FIG. 35 is a cross sectional view taken along line A-A in FIG. 34; FIG. 36 is a cross sectional view of an alternate embodiment of a reconfigurable artificial magnetic conductor;

FIG 37 is a top view of an alternate embodiment of a reconfigurable artificial magnetic conductor; and

FIG. 38 is a cross sectional view taken along line A-A in FIG. 11.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED

EMBODIMENTS

The embodiments of a reconfigurable artificial magnetic conductor (RAMC) described here allow a broader frequency coverage than a passive artificial magnetic conductor (AMC) by varying the capacitance of its frequency selective surface (FSS) in a controlled way to adjust the resonant frequency.

Approaches for tuning the capacitance of the FSS layer include (1) the integration of varactor diodes into a single layer FSS where the bias voltage is applied using a resistive lattice which is coplanar with the diode array, and (2) the use of tunable dielectric films in a two-layer FSS. The merit of building a RAMC is to permit adjacent wire or strip antenna elements to radiate efficiently over a relatively broad tunable bandwidth, up to approximately 3:1 in resonant frequency, when the elements are placed in close proximity to the RAMC surface (as little as λ₀/200 separation where λ₀ is the AMC resonant wavelength). FIG 4 is a top view of one embodiment of a reconfigurable artificial magnetic conductor (RAMC) 400. FIG. 5 is a cross sectional view of the RAMC 400 taken along line A-A in FIG. 4. The RAMC 400, like other artificial magnetic conductors, forms a high impedance surface having particular applicability, example, in conjunction with antennas and other electromagnetic devices. The RAMC 400 has a frequency selective surface (FSS) 402, which has a variable effective sheet capacitance to control resonant frequency of the RAMC. The capacitance of the FSS 402 is variable under control of a control circuit which operates in conjunction with the RAMC 400. For example, the RAMC 400 may be integrated with a radio transceiver, which controls tuning, reception and transmission of radio signals through an antenna formed in part by the RAMC 400. As part of the tuning process, which selects a frequency for reception or transmission, the control circuit applies appropriate signals to control the capacitance of the FSS 402 to control the resonant frequency of the RAMC 400. The RAMC 400 further includes a spacer layer 404, a radio frequency (RF) backplane 406 and metal vias 408. The FSS 402 includes a pattern of conductive patches 410. In preferred embodiments, the FSS 402 includes a periodic array of patches 410. In the illustrated embodiment, the conductive patches 410 are made of a metal or metal alloy. In other embodiments, other conductive materials may be used. Further, in the illustrated embodiment, the conductive patches 410 are arranged in a regular pattern and the patches themselves are substantially square in shape. In alternative embodiments, other patch shapes, such as circular, diamond, hexagonal or triagonal, and other patch patterns may be used. Furthermore, all the patches need not be identical in shape. For instance, the patches to which vias 408 are connected may be larger in surface area, while the patches without vias may be reduced in size, without changing the period of the RAMC 400. Still further, a pattern of conductive patches includes patches on a single layer as well as patches disposed in two or more layers and separated by particular materials.

Particular geometrical configurations may be chosen to optimize performance factors such as resonance frequency or frequencies, size, weight, and so on. In one embodiment, the FSS 402 is manufactured using a conventional printed circuit board process to print the patches 410 on one or both surfaces of the FSS and to produce plated through holes to form the vias. Other manufacturing technology may be substituted. The vias selectively excite patches 410 of the FSS 402 with a bias voltage applied through the RF backplane 406. The vias 408 are used to route DC bias currents and voltage from stripline control lines 420 buried inside the RF backplane. The RF backplane 406 includes one or more ground planes and one or more conductive striplines 420 or a stripline circuit with one or more bias control signals routed in between ground planes of the stripline circuit. The conductive striplines 420 may be biased using one or more external voltage sources such as voltage source 422. In the illustrated embodiment, the voltage source 422 applies a bias voltage V _ias between a bias stripline and a ground plane at the surface of the RF backplane 406. Selected vias 408 are electrically coupled with the bias stripline and first alternating patches so that the first alternating patches are a potential V_Was. Similarly, other selected vias 408 are electrically coupled with the ground plane or a grounded stripline of the RF backplane 406 and with second alternating patches so that the second alternating patches are at ground potential. In this manner, the bias voltage V_bias is applied between the alternating patches. Thus, the bias voltages are applied to the FSS 402 through the RF backplane 406 using the stripline or other conductors of the backplane 406 and the vias 408. In alternative embodiments, other bias voltages including time varying biasing signals may be applied in this manner through the RF backplane 406. Using time varying bias control signals, it is possible to modulate the reflection phase of the RAMC, and to convey information to a remote transponder via the phase of the monostatic or bistatic radar cross section presented by the RAMC. No RF transmit power is required at the RAMC. The process of reflecting a modulated signal for communication purposes is known as passive telemetry.

Further, the RAMC 400 includes variable capacitive elements 412, ballast resistors 414 and bypass capacitors 416. In the illustrated embodiment of FIG. 4, the variable capacitive elements are embodied as varactor diodes. A varactor or varactor diode is a semiconductor device whose capacitive reactance can be varied in a controlled manner by application of a bias voltage. Such devices are well known and may be chosen to have particular performance features. The varactor diodes 412 are positioned between and connected to adjacent patches of the FSS 402. The varactor diodes 412 add a voltage variable capacitance in parallel with the intrinsic capacitance of the FSS 402, determined primarily by edge-to-edge coupling between adjacent patches. The bias voltage for the varactor diodes 412 may be applied using the bias voltage source 422. More than one bias voltage may be applied and routed in the RAMC 400 using striplines 420 of the backplane 406 and vias 408. The magnitude of the bias signals may be chosen depending on the materials and geometries used in the RAMC 400. Thus, the local capacitance of the FSS 402 may be varied to control the overall resonant frequency of the RAMC 400. In an alternative embodiment, the conductive backplane structure comprises a stripline circuit and distributed or lumped RF bypass capacitors inherent in the design of the stripline circuit. The RF bypass capacitors 416 are coupled between stripline conductors of the backplane 406 and a ground plane of the backplane 406. Any suitable capacitor may be used but such a capacitor is preferably chosen to minimize size and weight of the RAMC 400. In appropriate configurations, the bypass capacitors may be soldered directly to the printed circuit board forming the RF backplane 406 or they may be integrated into the structure of the RF backplane

406. Such integrated bypass capacitors may be realized by using low impedance striplines, where the capacitance per unit length is enhanced by employing wider striplines and higher dielectric constant materials. The bypass capacitors 416 are required to decouple RF current at the base of the biasing vias. The ballast resistors 414 are electrically coupled between adjacent patches

410. The ballast resistors generally have a large value (typically 1 MΩ) and ensure an equal voltage drop across each series diode in the strings of diodes that are found between the biasing vias and the grounded vias.

The basic pattern illustrated in FIGS. 4 and 5 may be repeated any number of times in the x anάy directions (defined by the coordinate axes shown in FIG. 4).

FIGS. 4 and 5 illustrate an RF unit cell 426. The RAMC 400 is characterized by a unit cell 426, which includes, in a first plane including the surface ^"of the FSS 402, a pattern of three or more conductive patches and voltage variable capacitive elements between laterally adjacent conductive patches. One conductive patch of the unit cell is electrically coupled with an associated conductive via 408. In a second plane, the unit cell 426 includes a conductive backplane segment extending substantially parallel to a plane including the three or more conductive patches. The unit cell further includes the associated conductive via extending from the one conductive patch to one of the bias signal lines or grounded vias extending from the RF backplane 406.

FIG. 6 is a top view of a second embodiment of a reconfigurable artificial magnetic conductor 400. In the second embodiment, the varactor diodes 426 are installed in a thinned pattern so as to reduce the capacitance per unit area, as well as the cost, weight and complexity of the RAMC 400. In the exemplary embodiment of FIG. 6, every second and third row and column are not used for integration of the varactor diodes 426. The result is a pattern of strings of diodes 412 and ballast resistors 414 arranged across the surface of the RAMC 400. Alternative embodiments may be designed skipping one, three or N rows of patches between diode strings. Although FIG. 6 implies that patches are uniform in size and shape, this need not be the case. For instance, patches associated with vias may be substantially larger in surface area than patches not associated with vias.

A physical implementation of this embodiment has been fabricated. The best mode of this RAMC is fabricated by sandwiching a 250 mil thick foam core (ε_r=l .07) between two printed circuit boards. The upper board is single-sided 60 mil Rogers R04003 board and forms the FSS. Plated through holes are located in the center of one out of every nine square patches, 300 mils on a side with a period of 360 mils. Tuning diodes are M A-COM GaAs MA46H202 diodes, and the ballast resistors are each 2.2 MΩ chips. The RAMC is assembled by installing 22 AWG wire vias between the FSS board and the RF backplane on 1080 mil centers.

The RF backplane is a 3 layer FR4 board, 62 mils thick, which contains an internal stripline bias network. Ceramic decoupling capacitors are used on the bottom side of the RF backplane, one at every biasing via. The total thickness of this fabricated RAMC is approximately 0.375 inches excluding the surface mounted components. The measured reflection coefficient phase angle versus frequency is shown in FIG. 7 with the varactor bias voltage as a parameter. At each bias level, the instantaneous +/- 90-degree bandwidth of the device is relatively narrow. However, as the bias voltage changes, the instantaneous +/- 90-degree bandwidth continuously moves across a much wider frequency band, from 600 MHz to 1920

MHz in resonant frequency.

FIGS. 8, 9 and 10 show the measured S₂₁ for the transverse electric (TE) and transverse magnetic (TM ) surface wave coupling for 50, 20 and 0 volt bias levels, respectively. The range of frequencies satisfying the +/- 90 degree reflection phase criterion is indicated on each plot. The surface wave bandgaps observed are correlated closely to the +/- 90-degree reflection phase bandwidths at each bias level. Broadband antennas, such as spirals, can be mounted in close proximity to the RAMC surface and exhibit good impedance and gain performance over the range of frequencies associated with the surface wave bandgap. As the RAMC is tuned over a wide range of frequencies, the spiral antenna can operate efficiently, even though the entire structure is only λo/52 thick at the lowest frequency.

FIG. 11 and FIG. 12 illustrate a second embodiment of a reconfigurable artificial magnetic conductor (RAMC) 1100. FIG. 11 is a top view of the RAMC 1100. FIG. 12 is a cross sectional view taken along line A-A in FIG. 11.

The RAMC 1100 includes a frequency selective surface (FSS) 1102, a spacer layer 1104 and a radio frequency (RF) backplane 1106. An antenna element 1103 is placed adjacent to the RAMC 1100 to form an antenna system. The backplane 1106 includes one or more bias voltage lines 1120 and a ground plane 1122. In one embodiment, the backplane is fabricated using printed circuit board technology to route the bias voltage lines. The spacer layer is pierced by conductive vias 1108. The conductive vias 1108 electrically couple bias control signals, communicated on the bias voltage lines 1120 of the conductive backplane, with adjacent conductive patches 1110 of the FSS 1102. The bias signals are labeled V_cl and V_c2 in FIGS. 11 and 12. The bias control signals may be DC or AC signals or a combination of these. In general, the bias signals are generated elsewhere in the circuit including the RAMC 1100. In other embodiments, more or fewer bias signals may be used. The magnitude of the bias signals may be chosen depending on the electronic components and materials used in the RAMC 1100. The backplane 1106 further includes RF bypass capacitors 1116 between respective bias voltage lines 1120 and the ground plane 1122.

The FSS 1102 includes a periodic array of conductive patches 1110. In the embodiment of FIGS. 11 and 12, the FSS 1102 is a two-layer FSS. The FSS 1102 includes a dielectric layer 1130, a first layer 1132 of conductive patches disposed on a first side of the dielectric layer 1130 and a second layer 1134 of conductive patches disposed on a second side of the dielectric layer 1130. Portions of the second layer 1134 of conductive patches overlap portions of the first layer 1132 of conductive patches. The FSS 1102 further includes diode switches between selected patches of the first layer 1132 of conductive patches. Access holes 1138 are formed in the patches of the inside or second layer

1134 and the dielectric layer 1130 so that the vias 1108 may electrically contact adjacent patches of the outside or first layer 1132. As indicated, the patches of the first layer 1132 are alternately biased to ground or a bias voltage such as V_cl V_c2. In this manner, the capacitance of the FSS 1102 is variable to control resonant frequency of the FSS 1102.

The FSS 1102 further includes PIN diodes 1140. A PIN diode is a semiconductor device having a p-n junction with a doping profile tailored so that an intrinsic layer is sandwiched between a p-doped layer and an n-doped layer. The intrinsic layer has little or no doping. PIN diodes are known to be used in microwave applications as RF switches. They provide a series resistance and series capacitance which is variable with applied voltage, and they have high power-handling capacity. Thus, the PIN diodes are voltage variable capacitive circuit elements. Other suitable types of voltage variable capacitive circuit elements may be substituted for the PIN diodes 1140, such as MEMS switches or MEMS variable capacitors. Thus, this embodiment of the RAMC 1100 is realized by using PIN diode switches in a two-layer FSS. FIGS. 11 and 12 show the general layout and the biasing scheme. The basic concept is to reconfigure the effective sheet capacitance of the FSS 1102 by using PIN diode switches 1140 to change the density of overlapping printed patches 1110 on the layers 1132, 1134. The vias

1108, indigenous to the high-impedance surface, are used to route bias currents and voltages from stripline control lines 1120 buried inside the RF backplane 1106. Thus, the AMC 1100 has a first set 1132 of conductive patches on one side of an FSS dielectric layer 1130 and a second set 1134 of conductive patches on a second side of the FSS dielectric layer 1130.

The RAMC 1100 may be described as repeated instances of a unit cell 1142. There are four diodes per unit cell. The unit cell includes, in a first plane, a pattern of three or more conductive patches 1110 disposed on a first side of the dielectric layer 1130. Each conductive patch is electrically coupled with an associated conductive via 1108. Also in the first plane, the unit cell includes RF switches, such as the PIN diodes 1140, between selected laterally adjacent conductive patches 1110, each conductive patch overlapping at least in part a spaced conductive patch 1134 on a second side of the dielectric layer 1130. The unit cell 1142 further includes, in a second plane, a conductive backplane 1106 segment extending in a plane substantially parallel to a plane including the three or more conductive patches 1110, with the associated conductive vias extending from the each conductive patch to a bias signal line of the conductive backplane.

Other geometrical configurations of the patches 1110 on the two sides of the dielectric layer 1130 may be selected in order to vary the resonant frequency of the RAMC 1100. In an alternate embodiment, the patches 1110 of a given unit cell 1142 may not be exactly four in number, and they may have a variety of dimensions. For instance, there may be 6 patches in a given unit cell, all of unique dimensions and surface area. The dissimilar surface area is advantageous when the design goal is to offer both fine and coarse tuning choices. An example is illustrated below in FIG. 13. Consider a large array comprised of the RAMC 1100 as described in FIGS. 11 and 12. The density of "on" cells defines tuning states for a wide range of effective capacitance as seen by x or y -polarized E fields. For instance, the lowest effective FSS capacitance is realized when all PIN diodes are turned off (reverse biased). This results in the highest RAMC resonant frequency, and is referred to as a discrete tuning state of the RAMC. The highest effective FSS capacitance is realized when all of the PIN diodes are turned on (forward biased). This results in the lowest RAMC resonant frequency. Another tuning state, yielding an intermediate resonant frequency, is achieved when only half of the diodes are turned on. Such is the case when all diodes of a given unit cell are either on or off, but the unit cells which are turned on map into a checkerboard pattern across the face of the RAMC. More than two distinct control lines 1120 may be required in the RF backplane 1106, depending on the number of desired tuning states, and the amount of forward bias current that each line is designed to source.

FIG. 13 is a top view of an alternative embodiment of a unit cell of a frequency selective surface 1300 for use in a reconfigurable artificial magnetic conductor. The FSS 1300 provides an alternate realization of the approach to the RAMC design shown in FIGS. 11 and 12. In the embodiment of FIG 13, the FSS 1300 includes conductive concentric square loops 1302, 1304, 1306, 1308 arranged on a first side of a dielectric layer and conductive square patches 1312, 1314, 1316, 1318 arranged on the second side of the dielectric layer. Each of the concentric loops includes a segment, which at least overlaps one of the patches 1312, 1314, 1316, 1318 and non-overlapping end segments. Non-overlapping segments are coupled at their ends by PIN diodes 1320 or other suitable RF switches. Bias voltages are applied to portions of the respective loops 1302, 1304, 1306, 1308 so as to bias individual PIN diodes into their on or off state. Other geometries may be substituted, for example, using triangular, rectangular, circular or hexagonal loops in place of the square loops 1302, 1304, 1306, 1308. The embodiment of FIG. 13 achieves sixteen discrete tuning states using four DC control voltages by using a set of overlapping concentric square loops. This assumes that every unit cell receives the same pattern of control signals. Preliminary analysis with a full- wave simulation tool indicates that it may be possible to achieve a tunable bandwidth of greater than 10:1 using embodiments similar to that of FIG. 13. FIG. 14 is a top view of another embodiment of a frequency selective surface 1400 for use in a reconfigurable artificial magnetic conductor (RAMC). FIG. 15 is a side view of the FSS 1400 of FIG. 14. In the embodiment of FIG. 14, a first periodic array of conductive patches 1402 is disposed on a first side of a dielectric layer 1406. A second periodic array of conductive patches 1404 is disposed on the second side of the dielectric layer 1406. Patches 1402 of the first array on the first side of the dielectric layer 1410 overlap patches 1404 of the second array on the second side. The geometries and relative dimensions shown in FIGS. 14 and 15 are exemplary only and may be varied to provide particular operational characteristics. The FSS 1400 further includes micro-electromechanical systems (MEMS) switches 1410 disposed between adjacent patches 1402 of the first array. MEMS switches are electromechanical devices, which can provide a high ratio of ON to OFF state capacitance between terminals of the device. So the capacitive reactance between RF terminals can be controlled or adjusted over a very large ratio. Another broad class of MEMS switch is a type that provides an ohmic contact, which is either open (OFF) or closed (ON). An ohmic contact MEMS switch most closely emulates the function of a PIN diode since the series resistance between RF terminals is switched between low (typically < 1Ω) and high (typically >10 MΩ) values. MEMS switches are known for use in switching applications, including in RF communications systems. RF MEMS switches have electrical performance advantages due to their low parasitic capacitance and inductances, and absence of nonlinear junctions. This results in improved insertion loss, isolation, high linearity and broad bandwidth performance. Published MEMS RF switch designs use cantilever switch, membrane switch and tunable capacitor structures. The capacitance ratio of a capacitive type MEMS switch is variable in response to a control voltage, typically 25: 1 minimum. As in the embodiments of FIG. 4 and FIG. 11, the control voltages for the MEMS switches may be routed through the vias that are intrinsic to the spacer layer of the RAMC including the FSS 1400 (not shown in FIG. 14). FIG. 16 is a cross sectional view of a prior art artificial magnetic conductor

(AMC) 1600. FIG. 19 is a top view of the AMC 1600. The AMC 1600 includes a frequency selective surface (FSS) 1602, a spacer layer 1604, and a ground plane 1606. The FSS 1602 includes a first pattern of first patches 1610 on a first side of a dielectric layer 1614 and a second pattern of second patches 1612 on a second side of the dielectric layer 1614. The spacer layer 1604 is pierced by a forest of vias including vias 1608 associated with first patches 1610 and vias 1609 associated with second patches 1612. Each via 1608, 1609 has a one-to-one association with a first patch 1610 and a second patch 1612, respectively, of the FSS 1602. That is, each patch 1610, 1612 has associated with it one and only one via 1608, 1609, and each via 1608, 1609 is associated with one and only one patch

1610, 1612.

FIG. 17 is a cross sectional view of a first embodiment of an artificial magnetic conductor (AMC) 1600 with a reduced number of vias 1608 in the spacer layer 1604. FIG. 20 is a top view of this same embodiment, hi the embodiment of FIGS. 17 and 20, vias 1609 connect only to the lower or second patches 1612. The vias 1608 which in the embodiment of FIG. 16 had been associated with the upper or first patches 1610 are omitted. The vias 1609 are associated only with the second patches 1612. The vias 1609 may be electrically coupled with their associated patches or they may be separated from the patches 1612 by a dielectric. This can be achieved, for example, if the patches 1612 are annular with the via passing through the central region. Thus, in FIG. 17, the spacer layer of the AMC 1600 has conductive vias associated with some or all of only the first set of conductive patches formed on one side of the dielectric layer of the FSS. Also, in FIG. 17, the vias 1609 are shown extending above the plane of the patches 1612 to the plane of the patches 1610. Alternatively, the vias 1609 may be truncated at any suitable level in the cross section of the AMC 1600.

FIG. 18 is a cross sectional view of a second embodiment of an artificial magnetic conductor (AMC) 1600 with a reduced number of vias in the spacer layer 1604. FIG. 21 shows a top view of this same embodiment. In the embodiment of FIGS. 18 and 21, the vias 1608 are associated only with patches 1610 of the first or upper layer of patches. Patches 1612 of the second or lower layer of patches do not have vias 1608 associated with them. As in FIGS. 17 and 20, the vias 1608 may or may not electrically connect with the patches 1610 and the length of the vias 1608 may be selected according to performance and manufacturing requirements. Thus, in FIG. 18, the spacer layer 1604 of the AMC 1600 has conductive vias associated with some or all of only the second set of conductive patches foπned on one side of the dielectric layer of the FSS. Further, in the embodiments both FIGS. 17, 20 and FIGS. 18, 21 , the ground plane 1606 illustrated in the figures may be replaced with an RF backplane of the type described above and including one or more ground planes and one or more striplines or other circuits or devices.

FIG. 22 and FIG. 23 show an alternative embodiment of an AMC featuring a partial forest of vias 1608. In the embodiment of FIG. 21, one-half the total number of vias was provided in the spacer layer by omitting vias associated with the second layer of patches 1612. In the embodiment of FIG. 22, one in every four vias is installed by including only some vias associated with the first layer of patches 1610 (omitting all vias associated with the second layer of patches 1612). In FIG. 22, the installed vias 1608 form a checkerboard pattern, with a via present for every other patch 1610 along the rows and columns of patches. Similarly, FIG. 23 shows one of every eighteen vias installed, relative to a fully populated forest of vias as shown in FIG. 19. Other configurations such as non- checkerboard patterns could be used as well. For example, the patterns could be non-uniform along rows or columns of patches 1610 or in varying regions of the

AMC 1600. A pattern of vias associated with one or both layers of patches 1610, 1612 may be chosen to achieve particular performance goals for the AMC or associated equipment.

Thus, the present embodiments provide an artificial magnetic conductor (AMC) which includes a partial forest of vias in the spacer layer. By partial forest, it is meant that some of the vias of the AMC are omitted. The omitted vias may be those related to patches on a particular layer or to patches in a particular region of the plane of the spacer layer. The resulting partial forest of vias may be uniform across the structure of the AMC or may be non-uniform.

The AMC of the embodiments illustrated herein includes a frequency selective surface (FSS) having a pattern of conductive patches, a conductive backplane structure, and a spacer layer separating the FSS and the conductive backplane structure. The spacer layer includes conductive vias associated with some but not all patches of the pattern of conductive patches. While the illustrated embodiments show omission of vias associated with patches on a single layer, other patterns of via omission may be implemented as well, including omitting vias from a region of the AMC when viewed from above.

Other embodiments may be substituted as well, as indicated above. In one embodiment, the backplane includes one or more ground planes and conductive vias are in electrical contact with the ground plane. In another embodiment, the backplane includes bias signal lines which are in electrical contact with a subset or all of the vias. By selective application of bias signals, the effective sheet capacitance of the AMC may be varied to tune the AMC. In still another embodiment, the backplane includes both a ground plane or ground planes and bias signal lines. In still another embodiment, the AMC includes a single layer of conductive patches on one side of a dielectric layer. In the simplest embodiment, a subset of the patches have associated with them vias in the spacer layer shorted to a ground plane. For example, alternate patches may have vias omitted from the forest of vias creating a partial forest of vias in a checkerboard pattern. Other patterns may be chosen as well to tailor the performance of the AMC. In other embodiments, the dielectric layer is tunable so that the AMC is resonant at more than one selectable frequency or bands of frequencies. In such an embodiment, some or all of the vias may be electrically biased to control the tuning of the AMC. Biasing signals may be applied from the backplane or generally from behind the AMC, or biasing signals may be applied from in front of the AMC such as through a biasing network of resistors or other components. In yet another embodiment, the AMC includes first and second layers of conductive patches on opposing sides of a dielectric film.

Referring now to FIG 24, it shows a top view of one embodiment of a reconfigurable artificial magnetic conductor (RAMC) 2400. FIG. 25 is a cross sectional view of the RAMC 2400 taken along line A-A in FIG. 24. The RAMC

2400 has a frequency selective surface (FSS) 2402 which has a capacitance which is variable to control resonant frequency of the FSS. The capacitance of the FSS 2402 is variable under control of a control circuit which operates in conjunction with the RAMC 2400. For example, the RAMC 2400 may be integrated with a radio transceiver which controls tuning, reception and transmission of radio signals through an antenna formed in part by the RAMC 2400. As part of the tuning process, which selects a frequency for reception or transmission, the control circuit applies appropriate signals to control the capacitance of the FSS 2402 to control the resonant frequency of the RAMC 2400. The RAMC 2400 further includes a spacer layer 2404, a ground plane 2406 and metal vias 2408. The spacer layer 2404 separates the ground plane 2406 and the FSS 2402. The spacer layer is preferably a dielectric material which, in combination with the vias 2408, forms a rodded medium. Each via 2408 is preferably associated with a patch 2410 of the FSS. The lower terminus of each via is in electrical contact with the ground plane 2406. The vias 2408 extend through the spacer, electrically coupling one group 2412 of conductive patches with the ground plane 2406.

The FSS 2402 includes a pattern of conductive patches 2410. In the illustrated embodiment, the FSS 2402 includes a single layer of conductive patches disposed on one side of the spacer layer 2408. One group 2412 of conductive patches is electrically coupled with a reference potential, which is ground potential in the embodiment of FIGS. 24 and 25. Each patch of the one group 2412 is electrically coupled with the via 2408 which is associated with the patch.

A second group 2416 of conductive patches 2410 forms a set of bias nodes. Each patch of the second group 2416 is not electrically coupled with its associated via 2408. In the illustrated embodiment, this is achieved by leaving a space 2417 between the patch and the associated via. This may be achieved in any other suitable manner, such as keeping a layer of insulator material between the top of the via 2408 and the conductive patch 2410. In this manner, the patches of the second group 2416 may be biased at a voltage separate from ground or another reference voltage at which the first group 2412 of patches is biased by electrically contacting the associated via 2408.

The RAMC 2400 further includes a bias line 2418 to convey a bias voltage, labeled V_bj_as in FIG. 24. The RAMC 2400 still further includes bias resistance elements in the form of decoupling resistors 2420 between the patches of the second group 2416 and between the bias line 2418 and a first row 2422 of conductive patches of the second group 2416. Any suitable resistors may be used. Their purpose is to provide a common bias voltage to the voltage variable capacitive elements, and yet inhibit the flow of RF current between the patches considered to be bias nodes. In one embodiment, the bias resistance elements are formed using decoupling resistors fabricated using a resistive film. In another embodiment, the bias resistance elements are formed using surface mounted chip resistors. The chip resistors may be preferred in some applications because they provide sufficiently accurate resistance values and are small, lightweight and inexpensive to use. Also, a chip resistor's parasitic shunt capacitance is typically

0.05 pF or less, which is sufficiently low so as not to influence the low capacitance limit of the tunable FSS 2402. Typical values for the resistors 2420 are in the range 10 KΩ to 2.2 MΩ.

The FSS 2402 further includes voltage variable capacitive elements 2414 coupling patches of the one group 2412 of conductive patches with patches of the second group 2416. In the illustrated embodiment of FIG. 24, the voltage variable capacitive elements 2414 are embodied as varactor diodes, however microelectrical-mechanical systems (MEMS) based variable capacitors can also be used in this application. (Refer to A. Dec and K. Suyma, "Micromachined Electro-Mechanically Tunable Capacitors and Their Applications to RF ICs," IEEE Trans. Microwave Theory and Techniques, Vol 46, No. 12, Dec 1998, p.

2587.)

One suitable varactor diode is the MA46H202 GaAs tuning diode available from M/A Com of Lowell, Massachusetts. A varactor or varactor diode is a semiconductor device whose capacitive reactance can be varied in a controlled manner by application of a reverse bias voltage. Such devices are well known, and may be chosen to have particular performance features. The varactor diodes 2414 are positioned between alternating patches of the FSS 2402. The varactor diodes 2414 add a voltage variable capacitance in parallel with the intrinsic capacitance of the FSS 2402. The bias voltage for the varactor diodes 2414 may be applied using the bias line 2418. In the illustrated embodiment, a single bias voltage is shown biasing all patches of the second group 2416 of patches. However, in some embodiments, more than one bias voltage may be applied and routed in the RAMC 2400 using bias lines such as bias line 2418. The magnitude of the bias signals provided on the bias line 2418 may be chosen depending on the materials and geometries used in the RAMC 2400. Thus, the local capacitance of the FSS 2402 may be varied to control the overall resonant frequency of the RAMC 2400.

In alternative embodiments, the voltage variable capacitive elements may be formed from or using microelectrical-mechanical switch (MEMS) capacitors, thick film or thin film capacitors, or a bulk tunable dielectric material such as ferroelectric ceramic capacitors. Substitution of these materials and devices is within the purview of those ordinarily skilled in the art of circuit design.

In preferred embodiments, the FSS 2402 includes a periodic array of patches 2410. In the illustrated embodiment, the conductive patches 2410 are made of a metal or metal alloy. In other embodiments, other conductive materials may be used. Further, in the illustrated embodiment, the conductive patches 2410 are arranged in a regular pattern and the patches themselves are substantially square in shape. In alternative embodiments, other patch shapes, such as circular, hexagonal, diamond, or triagonal, and other patch patterns may be used. Also, the grounded patches 2412 and the bias node patches 2416 are not necessarily the same size and shape. Increasing the size of patches 2412, while simultaneously decreasing the size of patches 2416 and maintaining the same period, will lower the TM mode cutoff frequency, resulting in a larger surface wave bandgap. Particular geometrical configurations may be chosen to optimize performance factors such as resonance frequency or frequencies, size, weight, and so on. In one embodiment, the FSS 2402 is manufactured using a conventional printed circuit board process to print the patches 2410 on one or both surfaces of the FSS and to produce plated through holes to form the vias. Other manufacturing technology may be substituted for this process.

In the illustrated embodiment, the first group 2412 of conductive patches and the second group 2416 of conductive patches are arranged in a checkerboard pattern, with patches of the first group 2412 alternating with patches of the second group 2416 along both x and y axis. In this embodiment, each conductive patch of the second group 2416 in the checkerboard pattern is coupled through respective voltage variable capacitive elements 2414 to all surrounding conductive patches of the first group 2412. In the embodiment of FIG. 24, the decoupling resistors 2420 form a square lattice in association with a checkerboard pattern formed by the patches. In alternative embodiments, the biased and grounded patches of the first and second groups are arranged in any suitable alternating pattern in both transverse directions, x and v. The alternating patterns may not match in both the x and the y directions and the patterns may not be uniform across the entire AMC.

FIGS. 24 and 25 illustrate conceptually an embodiment of an RAMC realized by integrating varactor diodes into a single layer FSS. This varactor- tuned FSS concept is unique in that bias voltage is not applied or routed through vias from the backplane. Rather, bias voltage is applied to each diode from a coplanar array of RF decoupling resistors which form a square lattice. Resistors lie on the diagonal lines of the array formed by the conductive patches. The resistors connect bias nodes, which are patches unconnected to the vias below them. Every other node in a row or column is a bias voltage node. Ground nodes are patches which are connected to the vias, which in turn are connected to the grounded RF backplane or ground plane. The result is a checkerboard of ground nodes and bias voltage nodes.

Unlike previous designs, no decoupling capacitors are required between bias lines and ground. All surface mounted components are mounted on the same side of the FSS. This saves significant manufacturing costs, which is an important design goal. FIGS. 24 and 25 illustrate an embodiment in which the anodes of each varactor

diode are grounded, and a positive (with respect to ground) bias voltage is

applied to the cathodes. In other words, all of the varactor diodes are biased in

parallel. However, all of the diodes may be reversed so that the cathodes are

grounded and the anodes are biased, but with a negative voltage. Such a

change will have no impact on the RF performance of the AMC. It is even

conceivable that some varactors in a given AMC design have their anodes

grounded, while other varactors in the same AMC have a grounded cathode.

FIG. 26 is a top view and FIG. 27 is a cross sectional view of a second embodiment of a reconfigurable artificial magnetic conductor (RAMC) 2400. This embodiment is a "thinned" version of the embodiment shown in FIGS. 24 and 25. The RAMC 2400 includes a frequency selective surface (FSS) 2402, a spacer layer 2404 penetrated by conducting vias 2408 and a backplane or ground plane 2406. The vias are in electrical contact with the ground plane 2406, which is typically kept at ground potential or other reference voltage. The FSS 2402 includes an array of conductive patches 2410. Each patch

2410 is associated with a via 2408 of the spacer layer. Each patch 2410 of a first group 2412 of patches 2410 is electrically coupled with its associated via so that the patch is maintained at ground or other reference potential. Each patch 2410 of a second group 2416 is not electrically coupled with its associated via but is electrically isolated from the grounded via 2408. The patches 2410 in the illustrated embodiment are arranged in a checkerboard pattern, alternating grounded patches with biased patches. Voltage variable capacitive elements, such as varactor diodes, couple grounded patches of the one group with biased patches of the second group. A mesh of resistors 2420 biases the patches of the second group 2416 with a bias voltage from a bias line 2418.

In the embodiment of FIGS. 24 and 25, each biased patch of the second group in the checkerboard pattern is coupled through respective voltage variable capacitive elements to all surrounding grounding patches. In the embodiment of

FIGS. 26 and 27, biased patches of the second group 2416 in the checkerboard pattern are coupled through respective voltage variable capacitive elements to some surrounding grounded patches. The result is a thinned array of varactors, using fewer diodes than the embodiment of FIGS. 24 and 25, which yields a lower FSS effective sheet capacitance for FSS 2402.

The merit of this thinned array of varactors in the embodiment of FIGS. 26 and 27 is that the capacitance per unit square can be substantially less than the sheet capacitance of a fully populated FSS. This is desirable when tuning to higher frequencies. In this example of FIGS. 26 and 27, every second row and column of diodes 2414 is removed. However, the concept may be extended such that only one of every three or four rows and columns is populated by diodes.

The tuning ratio for resonant frequency of the varactor-tuned AMC 2400 is expected to be approximately a 3:1 bandwidth, assuming the use of hyperabrupt junction GaAs tuning diodes. The resistors 2420 in the coplanar lattice will also contribute some small parasitic capacitance to the FSS unit cell. However, this is quite small for chip resistors, nominally ~ .05 pF per resistor. It is not expected that this parasitic capacitance will be a noticeable factor in defining the tuning bandwidth, for frequencies of 2 GHz and below. Also, the value of the decoupling resistors that create the resistive lattice is not critical. The only current that flows through the resistive lattice is reverse bias leakage current, typically measured in nanoamps. Practical experience with other biasing circuits indicates that 10KΩ to 2.2 MΩ chip resistors may be suitably used.

FIG. 28 and FIG. 29 are a top view and a cross sectional view, respectively, of an additional embodiment of a reconfigurable artificial magnetic conductor (RAMC) 2800. In FIGS. 28 and 29, the vias associated with the bias patches 2416 have been omitted, resulting in a partial forest of vias, where the vias are found only below the ground nodes. None of the bias nodes or patches 2416 has an associated via. This increases the period between vias. Vias are required to achieve a TM mode cutoff, and this may be accomplished using the vias 2408 below the grounded patches 2412 alone. Also, in the illustrated embodiment, the

RAMC 2800 features a larger size of the grounded patches 2412 relative to the bias node patches 2416. This helps to lower the normal effective permittivity of the spacer layer 2404. These two factors combine to lower the TM mode cutoff frequency, hence increasing the surface wave bandgap. The patches are shown to be square or diamond in shape for both bias and ground nodes, but this is not necessarily required. Other shapes and relative sizes for the patches may be substituted to achieve other design goals.

FIG. 30 is a top view of a portion of a reconfigurable AMC 3000 including a tunable frequency selective surface 3002. FIG. 31 is a cross sectional view of the AMC 3000 taken along line A-A in FIG. 30. In this embodiment, a network of resistors 3014 electrically couples patches 3012 forming bias nodes to the bias line 3020. Patches 3010 are ground nodes and are connected through vias 3008 to the ground plane 3006. Capacitive elements 3018, which are in this example embodied as varactor diodes, couple the bias node patches 3012 and the ground node patches 3010. A unit cell 3016 includes a grounded patch 3010, associated capacitive elements 3018, adjacent resistors 3014 and portions of the adjacent bias node patches 3012. The patches 3012 do not have vias and so are not grounded. In the spacer layer 3004, the missing vias below the bias node patches 3012 result in a larger spacing or period between vias 3008. In this embodiment, the grounded patches 3010 are much larger in area than the bias node patches 3012. The combination of a larger period between vias 3008 and a larger surface area of the patches 3010 attached to the vias lowers the TM mode cutoff frequency. A thinned array of capacitive elements is employed by connecting diodes to only some of the ground node patches 3010. As shown in

FIG. 30, one-half of the ground node patches 3010 are not employed to contact capacitive elements. This reduces the total number of diodes required to populate the AMC 3000, thereby reducing cost and weight of the AMC 3000. Further, the effective sheet capacitance is reduced and the maximum tunable frequency is increased in this manner.

FIG. 32 is a top view of a portion of a reconfigurable AMC 3200 including a tunable frequency selective surface 3002. FIG. 33 is a cross sectional view of the AMC 3200 taken along line A-A in FIG. 32. Similar to the AMC 3000 of FIG. 30, the AMC 3200 includes oversized patches 3210 coupled through vias 3208 to the ground plane 3206. Reduced-sized bias node patches 3212 are coupled through a network of bias resistors 3214 to a bias line 3220. Capacitive elements 3218, embodied as varactor diodes, couple the bias node patches 3212 and the ground node patches 3210. A unit cell 3216 includes a grounded patch 3210, associated capacitive elements 3218, adjacent resistors 3214 and portions of the adjacent bias node patches 3212. The patches 3212 do not have vias to the ground plane 3206 and so are not grounded.

In this embodiment, the bias resistors 3214 are arranged in a square mesh, in columns and rows which run between the patches 3210, 3212. As in FIG. 30, no vias are used below the small patches 3212 which form the bias nodes. The combination of a larger spacing or period between vias 3208 and a larger surface area of the patch 3210 associated with the vias lowers the TM mode cutoff frequency, extending the surface wave bandgap.

Also in the illustrated embodiment, the dielectric material of the spacer layer 3604 of the reconfigurable AMC 3200 includes a layer 3222 of FR4 or similar material and a layer 3224 of radiofrequency (RF) grade foam such as

Rohacell polymethacrylimide rigid foam, available from Rohm GmbH, Darmstadt, Germany. Use of RE foam may be preferable for reducing the weight of the AMC 3200. If the foam layer 3224 is used, the vias 3220 may be inserted by hand or other means, rather than using printed circuit board manufacturing techniques.

FIG. 34 is a top view of a portion of a reconfigurable AMC 3400 including a tunable frequency selective surface 3402. FIG. 35 is a cross sectional view of the AMC 3400 taken along line A-A in FIG 34. Similar to the AMCs 3000, 3200 of FIGS. 30 and 32, the AMC 3400 includes oversized patches 3410 coupled through vias 3408 to the ground plane 3406. Patches 3412 do not have vias to the ground plane 3406 and so are not grounded. The reduced-sized bias node patches 3412 are coupled through a network of bias resistors 3414 to a bias line 3420.

Capacitive elements 3418, embodied as varactor diodes, couple the bias node patches 3412 and the ground node patches 3410. A unit cell 3416 includes a grounded patch 3410, associated capacitive elements 3418, adjacent resistors 3414 and portions of the adjacent bias node patches 3412. Again in this embodiment, the bias resistors 3414 are arranged in a square mesh. In this embodiment, the grounded patches 3410 are square with rounded corners. Preferably, the grounded patches cover as much surface area as possible and maximize the effective radius of the patch 3410. In the embodiment of FIG. 34, the effective radius of the patches 3410 is the radius of the circular patch. In the embodiment of FIG. 30, the effective radius of the patches 3010 is a portion of the diagonal of a square patch 3010. These preferred geometries are beneficial to lower the normal permeability of the FSS 3402, which helps to increase the TE mode cutoff frequency.

Again, in the embodiment of FIG. 34, no vias are used below the bias node patches 3412. As described above, the larger patch 3410 surface area and the larger spacing between vias 3408 lowers the TM mode cutoff frequency and extends the surface wave bandgap. The patches 3412 may be made as small as possible while still permitting reliable connection of bias resistors 3414 and the capacitive elements 3418. Also in this embodiment, the frequency selective surface 3402 includes a multilayer dielectric substrate to reduce the weight relative to a thick fiberglass or FR4 board. Also, if the height of the spacer layer 3404 is 0.25 inches (1.0 cm) or greater, FR4 may not be available. Thus, the spacer layer 3404 includes a layer 3422 of FR4 combined with a layer 3424 of foam, as described above.

Further, in the embodiment of FIG. 34, the capacitive elements 3418 are combined as a pair 3426 as varactor diodes contained in a single package 3408.

Such diode pairs 3426 are commercially available with three terminals including a common cathode and two anodes. The common cathode may be soldered or otherwise joined to a bias node 3412 while the two anodes may be joined to adjacent ground node patches 3810. Common anode pairs may also be employed if the polarity of the bias voltage is reversed. Use of such devices may reduce the parts count, manufacturing cost and size and weight of the finished AMC.

FIG. 36 is a cross sectional view of a sixth embodiment of a reconfigurable artificial magnetic conductor (RAMC) 3600. The RAMC 3600 includes a frequency selective surface (FSS) 3602, a dielectric spacer layer 3604, a backplane or ground plane 3606, and conductive vias 3608 extending from the ground plane

3606 through the spacer layer 3604 to form a rodded medium.

The FSS 3602 includes a tunable dielectric film 3614, which may be a ferroelectric material such as Barium Strontium Titanate Oxide (BSTO), a first layer 3610 of conductive patches on one side of the tunable dielectric film 3614 and a second layer 3612 of conductive patches on a second side of the tunable dielectric film. The patches of the second layer 3612 overlap at least in part patches of the first layer 3610. The vias 3608 include first vias 3618 associated with patches of the first layer 3610 and second vias 3616 associated with patches of the second layer 3612. The backplane 3606 includes a stripline bias distribution layer 3620 which conveys bias signals to the first vias 3618 and the second vias

3616. In one embodiment, the backplane 3606 is fabricated using conventional printed circuit board techniques to form and route the stripline conductors interior to the backplane, and vias through the backplane to couple the stripline conductors to the vias 3608 of the spacer layer 3604. A bias voltage source 3622 provides a bias voltage to some stripline conductors, vias 3616 and their associated patches 3610. Ground potential or other reference voltage is provided to other vias 3618 and their associated patches 3612.

The reconfigurable or tuned AMC 3600 is an extension of the varactor- tuned embodiments of FIGS. 24-29 where varactor diodes are replaced by a film of voltage tunable dielectric, which may be a classic ferroelectric (FE) material or a composite FE material containing dopants. This tunable dielectric film separates opposing patches of the first layer 3610 and the second layer 3612 in a capacitive FSS 3602. The permittivity of the tunable dielectric material is highest when no biasing electric field is applied, and then it becomes lower as a DC biasing electric field is applied. Either polarity will work to bias the FE materials. Bias voltage for the FE material (capacitors) is applied to vias 3616 that terminate on one surface of the FSS while opposing patches on the other side of the FSS are grounded through vias 3618. As the bias voltage is increased from zero, the FSS capacitance falls, and the RAMC 3600 tunes to a higher resonant frequency. A maximum decrease of 50% to 75% in tunable dielectric material permittivity is anticipated, depending on the material, which implies an AMC tuning ratio of 1.41:1 to 2:1.

Tunable dielectric materials are characterized by very high relative dielectric constants, typically between 100 and 1000. Furthermore, the desire for relatively low control voltages, less than 100 VDC, implies a thin vertical separation between FSS patches. These factors conspire to raise the FSS sheet capacitance to values higher than what may be desirable in a practical design. A potential solution is to limit the physical extent where the tunable dielectric film and the top level of patches are fabricated, such that they do not necessarily cover the entire surface. FIG. 37 is a top view of another embodiment of a tunable or reconfigurable artificial magnetic conductor (RAMC) 3700. FIG. 38 is a cross sectional view of the RAMC 3700 taken along line A-A in FIG. 37. The RAMC 3700 includes a frequency selective surface (FSS) 3702, a dielectric spacer layer 3704, and a backplane 3706. The spacer layer 3704 is perforated by grounded vias 3718 and biased vias 3716. Each via 3716, 3718 is associated with a patch or metal portion of the FSS 3702. The grounded vias are electrically coupled to a ground plane of the backplane 3706 and are electrically coupled with their associated metal patches of the FSS 3702. The biased vias are electrically coupled to one or more bias signal lines of the back plane 3706 and are electrically coupled with their associated metal portions of the FSS 3702.

The FSS 3702 includes lower FSS metal patches 3712, tunable dielectric film portions 3714, and upper FSS metal portions 3710. In the embodiment of FIGS. 37 and 38, the tunable dielectric thin film 3714 is applied selectively in strips 3724 between some of the lower FSS metal patches 3712. Where the strips 3724 intersect, a biased via 3716 biases its associated patch 3712 to a bias voltage. The upper metal patch 3710 is much smaller than the lower metal patches, and it forms the center electrode to create a series pair of tunable capacitors. The equivalent circuit is shown in FIG. 37. By limiting the upper metal patch 3710 to a small surface area, and designing the ferroelectric capacitors to be series pairs, then the net capacitance of the tunable dielectric capacitors can be made sufficiently small, in the range of 1 to 10 pF. This capacitance range is needed for practical RAMC applications in the UHF and L-band frequency range (300 MHz to 2 GHz).

From the foregoing, it can be see that the present invention provides a reconfigurable artificial magnetic conductor (RAMC) which allows for a wider frequency coverage with a thinner RAMC thickness. The sheet capacitance of the frequency selective surface of the RAMC is controlled, thus controlling its high impedance properties. In one embodiment, varactor diodes are integrated into the frequency selective surface where the bias voltage is applied through a coplanar resistive lattice. In another embodiment, a tunable dielectric film is integrated into a two-layer frequency selective surface, which is biased through a stripline embedded in the backplane. However, a combination of tunable dielectric film and resistive biasing film may be integrated to eliminate the need for a multi-layer RF backplane. The biasing film and tunable dielectric film can be coplanar films, each covering a separate and distinct area of the FSS patches. This can be visualized by replacing the varactor diodes of FIG. 8 above with the tunable dielectric strips 1124 of FIG. 11 above. The present embodiments describe RAMCs whose surface impedance is isotropic, or equal for both transverse polarizations of electric fields. This is possible due to the symmetry of the patches and biasing networks. It is possible to spoil this symmetry, for example by employing rectangular patches in place of square patches. Such asymmetry can cause the AMC resonance to be polarization specific, but the AMC will still exhibit properties of a high impedance surface, and it will still be tunable. However, the surface wave bandgap may be adversely affected, or even disappear.

While a particular embodiment of the present invention has been shown and described, modifications may be made. It is therefore intended in the appended claims to cover such changes and modifications which follow in the true spirit and scope of the invention.

Claims

1. An artificial magnetic conductor (AMC) comprising: a frequency selective surface (FSS) having an effective sheet capacitance which is variable to control resonant frequency of the AMC.

2. The AMC of claim 1 wherein the FSS comprises a single layer of conductive patches disposed on a dielectric layer.

3. The AMC of claim 2 further comprising: voltage variable capacitors between selected conductive patches.

4. The AMC of claim 3 wherein the voltage variable capacitors comprise microelectrical-mechanical system (MEMS) based variable capacitors.

5. The AMC of claim 3 wherein the voltage variable capacitors comprise varactor diodes.

6. The AMC of claim 5 further comprising: ballast resistors between the selected conductive patches.

7. The AMC of claim 5 further comprising: a conductive backplane structure; and a spacer layer separating the FSS and the conductive backplane structure, the spacer layer pierced by conductive vias electrically coupling bias signals between the conductive backplane structure and adjacent conductive patches.

8. The AMC of claim 1 wherein the FSS comprises: a first layer of conductive patches disposed on a first side of a dielectric layer; a second layer of conductive patches disposed on a second side of the dielectric layer, portions of the second layer of conductive patches overlapping portions of the first layer of conductive patches; and radio frequency (RF) switches between selected patches of the first layer of conductive patches.

9. The AMC of claim 8 wherein the RF switches comprise PIN diode switches.

10. The AMC of claim 8 wherein the RF switches comprise microelectrical-mechanical system (MEMS) switches.

11. The AMC of claim 8 further comprising: a conductive backplane structure; and a spacer layer separating the FSS and the conductive backplane structure, the spacer layer pierced by conductive vias electrically coupling bias signals between the conductive backplane structure and adjacent conductive patches.

12. An artificial magnetic conductor (AMC) comprising: a frequency selective surface (FSS); a conductive backplane structure; a spacer layer separating the conductive backplane structure and the FSS, the spacer layer including conductive vias extending between the conductive backplane structure and the FSS; and voltage variable capacitive circuit elements coupled with the FSS and responsive to one or more bias signal lines routed through the conductive backplane structure and the conductive vias.

13. The AMC of claim 12 wherein the FSS comprises a dielectric layer with a single layer of conductive patches disposed on a side of the dielectric layer.

14. The AMC of claim 13 wherein conductive patches of the layer of conductive patches are substantially square.

15. The AMC of claim 13 wherein first predetermined conductive vias are arranged to electrically couple a bias voltage line and respective adjacent conductive patches and second predetermined conductive vias are arranged to electrically couple a ground plane and respective adjacent conductive patches.

16. The AMC of claim 12 further comprising ballast resistors coupled in parallel with the voltage variable capacitive circuit elements.

17. The AMC of claim 12 wherein the conductive backplane structure comprises a stripline circuit with one or more bias control signals routed in between ground planes of the stripline circuit.

18. The AMC of claim 12 wherein the conductive backplane structure comprises a stripline circuit and distributed or lumped RF bypass capacitors inherent in the design of the stripline circuit.

19. The AMC of claim 12 wherein the FSS comprises a dielectric layer with a first layer of conductive patches disposed on one side of the dielectric layer and a second layer of conductive patches disposed on a second side of the dielectric layer to at least partially overlap conductive patches of the first layer of conductive patches.

20. The AMC of claim 19 wherein a first subset of the conductive vias electrically couple a first bias signal line and associated conductive patches according to a first pattern on the one side of the dielectric layer and a second subset of the conductive vias electrically couple a second bias signal line and associated conductive patches according to a second pattern on the one side of the dielectric layer.

21. An artificial magnetic conductor (AMC) comprising: a frequency selective surface (FSS) including a periodic array of conductive patches; a spacer layer including vias extending therethrough in association with predetermined conductive patches of the FSS; and a conducting backplane structure including two or more bias signal lines, the AMC characterized by a unit cell including in a first plane, a pattern of three or more conductive patches, one conductive patch electrically coupled with an associated conductive via, and voltage variable capacitive elements between selected laterally adjacent conductive patches; and a conductive backplane segment extending in a second plane substantially parallel to a plane including the three or more conductive patches and the associated conductive via extending from the one conductive patch to one of the two or more bias signal lines.

22. The artificial magnetic conductor (AMC) of claim 21 wherein the two or more bias signal lines include a ground line and a bias voltage line.

23. The artificial magnetic conductor (AMC) of claim 21 wherein the periodic array comprises a square lattice of four conductive patches.

24. The artificial magnetic conductor (AMC) of claim 21 wherein the voltage variable capacitive elements comprise varactor diodes.

25. The artificial magnetic conductor (AMC) of claim 24 further comprising ballast resistors coupled in parallel with the varactor diodes.

26. An artificial magnetic conductor (AMC) comprising: a frequency selective surface (FSS) including a periodic array of conductive patches; a spacer layer including vias extending therethrough in association with predetermined conductive patches of the FSS; and a conducting backplane structure including two or more bias signal lines, the AMC characterized by a unit cell including in a first plane, a pattern of three or more conductive patches disposed on a first side of a dielectric layer, each conductive patch electrically coupled with an associated conductive via, and radio frequency (RF) switch elements between laterally adjacent conductive patches, each conductive patch overlapping at least in part a spaced conductive patch of a plurality of spaced conductive patches disposed on a second side of the dielectric layer; and in a second plane, a conductive backplane segment extending in a plane substantially parallel to a plane including the three or more conductive patches and the associated conductive vias extending from the each conductive patch to one of the two or more bias signal lines.

27. The AMC of claim 26 wherein the each conductive patch overlaps a spaced conductive patch which is common with horizontally adjacent and vertically adjacent unit cells of the FSS.

28. The artificial magnetic conductor (AMC) of claim 26 wherein the RF switch elements comprise PIN diodes.

29. The artificial magnetic conductor (AMC) of claim 26 wherein the RF switch elements comprise microelectrical-mechanical system (MEMS) switches.

30. A method for reconfiguring an artificial magnetic conductor (AMC) including a frequency selective surface (FSS) having a pattern of conductive patches, a conductive backplane structure and a spacer layer separating the FSS and the conductive backplane structure, the method comprising: applying control bias signals to voltage variable capacitive elements associated with the FSS; and thereby, reconfiguring effective sheet capacitance of the FSS.

31. The method of claim 30 wherein applying bias control signals comprises applying the bias control signals to conductors located in the conductive backplane structure and coupled to selected conductive patches by conductors extending through the spacer layer.

32. The method of claim 30 further comprising: tuning a resonant frequency of the AMC.

33. An artificial magnetic conductor (AMC) comprising: a frequency selective surface (FSS) having a pattern of conductive patches; a conductive backplane structure; and a spacer layer separating the FSS and the conductive backplane structure, the spacer layer including conductive vias associated with some but not all patches of the pattern of conductive patches.

34. The AMC of claim 33 wherein the conductive backplane structure comprises at least one ground plane, the conductive vias being in electrical contact with the at least one ground plane.

35. The AMC of claim 33 wherein the FSS comprises: a first set of conductive patches on one side of an FSS dielectric layer, and a second set of conductive patches on a second side of an FSS dielectric layer.

36. The AMC of claim 35 wherein the spacer layer has conductive vias associated with some or all of only the first set of conductive patches.

37. The AMC of claim 36 wherein the spacer layer has conductive vias associated with some or all of only the second set of conductive patches.

38. The AMC of claim 33 wherein the conductive backplane structure comprises bias signal lines in electrical contact with at least a subset of the conductive vias.

39. The AMC of claim 38 wherein the conductive backplane structure further comprises at least one ground plane, at least a second subset of the conductive vias being in electrical contact with the at least one ground plane.

40. The AMC of claim 33 wherein the FSS comprises: a layer of conductive patches on one side of a dielectric layer.

41. The AMC of claim 33 wherein the FSS comprises: a layer of conductive patches on one side of a tunable dielectric layer.

42. The AMC of claim 33 wherein the FSS comprises: a first layer of conductive patches on one side of a tunable dielectric film; and a second layer of conductive patches on a second side of the tunable dielectric film.

43. The AMC of claim 42 wherein the spacer layer comprises: a first set of conductive vias associated with at least some patches of the first layer of conductive patches; and a second set of conductive vias associated with at least some patches of the second layer of conductive patches.

44. A high impedance surface comprising: a frequency selective surface (FSS) patterned with conductive patches; a conductive ground plane; and a layer separating the FSS and the conductive backplane structure, the layer including a dielectric material pierced by a partial forest of conductive vias.

45. An artificial magnetic conductor (AMC) comprising: a frequency selective surface (FSS) including a single layer of conductive patches, one group of conductive patches being electrically coupled to a reference potential, a second group of conductive patches forming bias nodes; voltage variable capacitive elements coupling patches of the one group of conductive patches with patches of the second group, and decoupling resistors between the patches of the second group.

46. The AMC of claim 45 further comprising: a bias line conveying a bias voltage.

47. The AMC of claim 46 further comprising: decoupling resistors between the bias line and a first row of conductive patches of the second group.

48. The AMC of claim 47 wherein the bias voltage is variable for tuning resonant frequency of the AMC.

49. The AMC of claim 45 further comprising: a ground plane; a spacer layer separating the ground plane and the FSS; and vias through the spacer layer which electrically couple conductive patches of the one group with the ground plane.

50. The AMC of claim 45 wherein the first group of conductive patches and the second group of conductive patches are arranged in an alternating pattern in both transverse directions.

51. The AMC of claim 45 wherein the first group of conductive patches and the second group of conductive patches are arranged in a checkerboard pattern.

52. The AMC of claim 51 wherein each conductive patch of the second group in the checkerboard pattern is coupled through respective voltage variable capacitive elements to all surrounding conductive patches of the first group.

53. The AMC of claim 51 wherein conductive patches of the second group in the checkerboard pattern are coupled through respective voltage variable capacitive elements to some surrounding conductive patches of the first group.

54. The AMC of claim 51 wherein the decoupling resistors form a regular mesh.

55. The AMC of claim 54 wherein the decoupling resistors form a square lattice in association with the checkerboard pattern.

56. The AMC of claim 45 wherein the voltage variable capacitive elements comprise varactor diodes.

57. The AMC of claim 45 wherein the voltage variable capacitive elements comprise voltage variable microelectrical-mechanical system (MEMS) capacitors.

58. The AMC of claim 45 wherein the voltage variable capacitive elements comprise voltage variable thick film capacitors.

59. The AMC of claim 45 wherein the voltage variable capacitive elements comprise voltage variable thin film capacitors.

60. The AMC of claim 45 wherein the voltage variable capacitive elements comprise a bulk tunable dielectric material.

61. The AMC of claim 60 wherein the voltage variable capacitive elements comprise ferroelectric ceramic capacitors.

62. An artificial magnetic conductor (AMC) comprising: a ground plane; a spacer layer disposed adjacent the ground plane; a plurality of vias in electrical contact with the ground plane and extending from a surface of the ground plane in direction of the spacer layer; a frequency selective surface disposed on the spacer layer and including: a periodic pattern of bias node patches alternating with ground node patches, the ground node patches being in electrical contact with respective vias of the plurality of vias; components between selected bias node patches and ground node patches, the components having a capacitance which is variable in response to a bias voltage; and a network of bias resistance elements between adjacent bias node patches.

63. The AMC of claim 62 wherein the bias resistance elements comprise decoupling resistors fabricated using a resistive film.

64. The AMC of claim 62 wherein the bias resistance elements comprise surface mounted chip resistors.

65. The AMC of claim 62 wherein the components comprise varactor diodes.

66. The AMC of claim 62 wherein the components include respective components coupled between a bias node patch and each surrounding ground node patch.

67. The AMC of claim 66 wherein the components comprise varactor diodes.

68. The AMC of claim 62 wherein the components include respective components coupled between alternate ground node patches and each surrounding bias node patch.

69. The AMC of claim 62 wherein the plurality of vias includes a respective via for each bias node patch and each ground node patch, only the each ground node patch being in electrical contact with its respective via.

70. The AMC of claim 62 wherein the plurality of vias omit vias associated with the bias node patches.

71. An artificial magnetic conductor (AMC) comprising: means for forming a backplane for the AMC; a frequency selective surface (FSS) including means for varying effective sheet capacitance of the FSS; and a spacer layer separating the means for forming a back plane and the FSS, the spacer layer including a plurality of vias extending substantially normal to the FSS.

72. The AMC of claim 71 wherein the means for varying capacitance of the FSS comprises: a pattern of conductive patches printed on one side of the FSS, one group of conductive patches forming ground nodes, a second group of conductive patches forming bias nodes; voltage variable capacitive elements responsive to a bias voltage between a respective bias node and a respective ground node; and a bias line for biasing the bias nodes.

73. The AMC of claim 72 wherein the means for forming a backplane comprises a ground plane in electrical contact with vias of the plurality of vias respectively associated with the ground nodes for grounding the ground nodes.

74. The AMC of claim 72 further comprising: a network of resistors disposed between the bias nodes.

75. The AMC of claim 71 wherein the means for varying capacitance comprises: a tunable dielectric thick or thin film; patterns of overlapping conducting patches on respective sides of the tunable dielectric film, each patch being associated with a via, vias associated with patches on a first side being in electrical contact with a bias line of the. means for forming a backplane and vias associated with patches on a second side being in electrical contact with a ground line of the means for forming a backplane.

76. An artificial magnetic conductor (AMC) comprising: a frequency selective surface (FSS) including a tunable dielectric thick or thin film, a first layer of conductive patches on one side of the tunable dielectric film, and a second layer of conductive patches on a second side of the tunable dielecfric film, patches of the second layer overlapping at least in part patches of the first layer; a spacer layer including first vias associated with patches of the first layer and second vias associated with patches of the second layer; and a backplane conveying bias signals to the first vias and the second vias.

77. The AMC of claim 76 further comprising a bias voltage source providing the bias signals to vary permittivity of the tunable dielectric film.

78. An artificial magnetic conductor (AMC) comprising: a frequency selective surface (FSS) including a tunable dielectric film, a first layer of conductive patches on one side of the tunable dielectric film, and a second layer of conductive patches on a second side of the tunable dielectric film, patches of the second layer overlapping at least in part patches of the first layer; a spacer layer including vias associated with patches of the first layer; a backplane conveying bias signals to the first vias; and a resistive biasing network to apply a bias voltage to the tunable dielectric film.