WO2002085035A1

WO2002085035A1 - Solid-state imaging device

Info

Publication number: WO2002085035A1
Application number: PCT/JP2002/003301
Authority: WO
Inventors: Masahiro Juen
Original assignee: Nikon Corporation
Priority date: 2001-04-11
Filing date: 2002-04-02
Publication date: 2002-10-24
Also published as: JPWO2002085035A1

Abstract

A solid-state imaging device comprising pixels, pixels in one line being offset by a 1/2 pixel pitch in a horizontal direction from those in the adjacent line, a color filter array in which first- to third-color color filters in one line are offset by a 3/2 pixel pitch in a horizontal direction from those in the adjacent line and are arranged in each line in the order of the first to third color, a vertical signal transfer elements provided for each set of pixels arranged in zigzag with respect to vertical identical lines, first to third output elements, and vertical signal switching elements that switch two adjacent vertical signal transfer elements to one specific output element and connect them to thereby supply separately a pixel signal for the first-color color filter, a pixel signal for the second-color color filter, and a pixel signal for the third-color color filter to the first to third output elements. Accordingly, a line-for-line reading can provide the fast output of image signals by using independent 3-wire outputs for respective colors while maintaining a high resolution.

Description

Description Solid-state imaging device Technical field

The present invention relates to a solid-state imaging device having a color filter array in which three color filters are arranged. Background art

2. Description of the Related Art Conventionally, a single-chip solid-state imaging device having a color filter array in which three color filters are arranged has performed multi-line output for each color.

FIG. 8 is a diagram schematically showing a typical conventional solid-state imaging device.

In the solid-state imaging device shown in FIG. 8, a plurality of pixels are arranged in a two-dimensional matrix. On these pixels, R (red), G (green), and Β (blue) are associated with each pixel. There is a color fill array in which the three colors are arranged in a stripe pattern. Pixels that are arranged in the same column and are associated with the same color color filter are connected to the same vertical signal line, and each vertical signal line has a color fill color color. Depending on the difference, it is connected to one of the three output lines OUT1, OUT2, OUT3 via a transistor for column selection.

Therefore, the solid-state imaging device shown in Fig. 8 can output three lines for each color of R, G, and B, and can operate at high speed.

FIG. 9 is a diagram showing an outline of the solid-state imaging device disclosed in Japanese Patent Application Laid-Open No. 2000-12819.

In the solid-state imaging device shown in FIG. 9, a plurality of pixels are arranged in a two-dimensional matrix. On these pixels, R (red), G (green), and B (blue) are associated with each pixel. A color filter array in which the three color filters are arranged in a layer is provided. Pixels arranged in two adjacent columns are alternately connected to the same vertical signal line for each row, and each vertical signal line is connected to two output lines OUT 1 through a transistor for column selection. , OUT 2 alternately. So from 0 UT 1 to G A color signal (hereinafter simply referred to as a G signal) can be output, and R and B color signals (hereinafter simply referred to as an RB signal) can be output from OUT 2. That is, in the solid-state imaging device shown in FIG. 9, the G signal and the RB signal can be output independently and simultaneously, so that high-speed operation is possible.

Further, in the solid-state imaging device shown in FIGS. 8 and 9, the same color signal is output from the same output line without being divided into different lines. Therefore, in subsequent signal processing, offset correction and gain correction between different output lines are not required for color signals of the same color, and image quality does not deteriorate due to errors in these corrections. FIG. 10 is a diagram schematically showing a solid-state imaging device disclosed in Japanese Patent Application Laid-Open No. 58-31688.

In the solid-state imaging device shown in FIG. 10, a plurality of pixels are arranged in a row in a state of being offset by 1 Z 2 pixel pitch in a horizontal direction. Also, color fills of three colors, W (white), C (cyan), and Y (yellow), are offset horizontally by a 3/2 pixel pitch for each row, and Is provided with a color filter array arranged in the order of W, C; Further, pixels arranged on the same straight line in the vertical direction and associated with a color filter of the same color are connected to the same vertical signal line. Further, each vertical signal line is alternately connected to two output lines OUT 1 and OUT2 via a transistor for column selection.

According to the technology disclosed in Japanese Patent Publication No. 58-316168, the solid-state imaging device shown in FIG. 10 is used for an in-line race by an in-line race scanning unit (not shown). When driven, two adjacent rows are selected simultaneously via the vertical scanning circuit.

That is, if two lines are output simultaneously for a pair of the first line and the second line and a pair of the third line and the fourth line for an arbitrary field, two lines will be output for the next field. Two-wire output is performed simultaneously for the pair of the third and fourth lines and the pair of the fourth and fifth lines. The two-line output signal is supplied to a signal processing circuit (not shown) at the subsequent stage, where it is subjected to matrix mixing and converted into a luminance signal, an R signal, and a B signal. In other words, according to the technology disclosed in Japanese Patent Application Laid-Open No. 58-31688, the signals from the pixels associated with the same color filter are output by the solid-state imaging device shown in FIG. The output is divided and output to different output lines. By the signal processing, an image signal can be obtained without performing offset correction and gain correction between different output lines.

However, in the solid-state imaging device shown in FIG. 10, two rows are averaged and two-line output is performed, so that the image signal obtained from the two-line output signal has reduced vertical resolution. . In addition, the solid-state imaging device shown in FIG. 10 uses color filters of complementary colors of W, C, and Y. However, in general, solid-state imaging devices using complementary color filters do not have the color filters of the primary colors. It is known that color reproducibility is lower than that of a solid-state imaging device using a filter.

Therefore, by changing the color fill of the complementary color to the color fill of the primary colors of R, G, and B, and by selecting two adjacent rows separately, the color reproducibility and the resolution in the vertical direction are improved. It is possible.

However, in the solid-state imaging device shown in FIG. 10, the color of the color fill was changed as follows, and Y → R

C →

Simply selecting two adjacent rows separately via the vertical scanning circuit would result in the same color signal being output on different lines. Therefore, in the subsequent signal processing circuit, offset correction and gain correction between different output lines are required, and errors due to these corrections become vertical streaks and adversely affect image quality. .

FIG. 11 is a view schematically showing a solid-state imaging device disclosed in Japanese Patent No. 2654081.

In the solid-state imaging device shown in FIG. 11, two adjacent rows are selected at the same time by the same configuration as the solid-state imaging device shown in FIG. 10, but 3-line output is performed for each color. In the signal processing, no error due to offset correction or the like occurs.

However, in the solid-state imaging device shown in FIGS. 10 and 11, the signals from the two rows of offset pixels are simultaneously output, so that the vertical signal line and the horizontal scanning switch have one. Twice the number of pixels per row is required. Therefore, two vertical signal lines must be passed between the offset pixels. Such a vertical signal line wiring is realized by a two-layer wiring or a wiring in which two signal lines are arranged close to each other, but a defect such as a disconnection short-circuit easily occurs.

Also, in the solid-state imaging device shown in Fig. 9, in order to further increase the speed and achieve the same multi-line output signal band while achieving the same multi-line output signal bandwidth, the color filter must be used. Due to the restrictions on the arrangement of the signals, the G signal and the RB signal must be output separately for each of two or more lines.

Therefore, for example, if the G signal is divided into different lines and output at the same time, offset correction and gain correction between different output lines will be required as signal processing at the subsequent stage, which will adversely affect image quality as described above. Problems arise. There is no particular problem when the RB signal is divided into R and B signals and output at the same time.However, when the R and B signals are divided into different output lines and output at the same time, the same problem occurs. Occurs.

In the solid-state imaging device shown in FIG. 8, the number of pixels associated with the green color filter is 1/3 of the total number of pixels arranged in the horizontal direction. Therefore, the horizontal resolution of the solid-state imaging device shown in FIG. 8 is reduced to 2/3 as compared with the solid-state imaging device shown in FIG.

By the way, the solid-state imaging devices shown in FIGS. 10 and 11 do not have a fixed pattern noise suppression circuit. However, in general, as in these solid-state imaging devices, MOS-type or amplification-type solid-state imaging devices are used. The fixed pattern noise suppression circuit mounted on the imaging device requires at least as many temporary storage units as the vertical signal lines (or the horizontal scanning switches). Therefore, when this type of fixed-pattern noise suppression circuit is introduced into the solid-state imaging device shown in Figs. 10 and 11, the temporary storage unit needs to be twice the number of pixels per row, making miniaturization difficult. . Disclosure of the invention

The present invention provides a solid-state imaging device capable of outputting image signals at high speed by performing independent 3-line output for each color while maintaining high resolution by reading out one row at a time. The purpose is to provide a device. Another object of the present invention is to provide a solid-state imaging device capable of efficiently suppressing fixed pattern noise.

The solid-state imaging device according to the present invention includes a plurality of pixels that are arranged in a zigzag manner in the vertical direction by being offset by 1/2 pixel pitch in a horizontal direction for each row, and generate a signal corresponding to incident light; The three color filters of the first, second and third colors are horizontally offset by 3/2 pixel pitch for each row, and for each row, the first color, the second color, A color filter array arranged in the order of the third color, and a signal provided by each of the plurality of pixels arranged in a zigzag manner with respect to the same straight line in the vertical direction. A plurality of vertical signal transfer units for vertically transferring, a first to a third output unit for horizontally transferring a signal vertically transferred by the vertical signal transfer unit and outputting the image signals, and a plurality of the vertical signal transfer units. Two adjacent vertical signal transfers Switching the two vertical signal transfer units to one specific output unit that is determined based on the color of the same color filter associated with each pixel for each unit Supplies the signal generated by the pixel associated with the first color to the first output unit, and outputs the signal generated by the pixel associated with the second color of the color And a vertical signal transfer switching unit that supplies a signal generated by a pixel associated with the color of the third color to the third output unit.

Note that, in the solid-state imaging device of the present invention, one specific output unit connected to two adjacent vertical signal transfer units is as follows.

If the color of the same color corresponding to the pixels connected to the two adjacent vertical signal transfer units is the first color, the specific one output unit is the first output unit. Further, when the color of the same color filter associated with the pixel connected to the two adjacent vertical signal transfer units is the second color, one specific output unit is the second output unit. is there. Further, when the color of the same color corresponding to the pixel connected to the two adjacent vertical signal transfer units is the third color, one specific output unit is the third output unit. is there.

Here, by switching two adjacent vertical signal transfer units to a specific output unit and connecting them, a signal generated by a pixel associated with the first color filter is connected. Signal is supplied to the first output unit, and the signal generated by the pixel associated with the color filter of the second color is supplied to the second output unit, and the color filter of the third color is supplied. An operation in which a signal generated by the attached pixel is supplied to the third output unit will be described. In the solid-state imaging device of the present invention, when the color filter of the first color is associated with the j-th pixel in an arbitrary i-th row, the (j + 1) -th pixel in the i-th row is assigned to the j-th pixel. Two color fill filters are associated with each other, and the (j + 2) -th pixel in the i-th row is associated with a third color force filter. Also, the j-th pixel on the (i + 1) -th row is associated with the third color filter, and the. (J + 1) -th pixel on the (i + 1) -th row is the first color. And the (j + 1) -th pixel in the (i + 1) -th row is associated with the second-color color filter.

Therefore, when the color filter of the first color is associated with the pixel j of the i-th row, the color filter of the first color and the color filter of the third color are transmitted to the j-th vertical signal transfer unit. Pixels that are alternately associated with the filters are connected. Further, the (j + 1) -th S direct signal transfer unit is connected to pixels in which color filters of the second color and color filters of the first color are alternately associated with each other. The pixel in which the third color filter and the second color filter are alternately connected is connected to the (j + 2) -th vertical signal transfer section.

Of the three vertical signal transfer units, the (j + 1) th vertical signal transfer unit is connected to the j′th vertical signal transfer unit via the vertical signal transfer switching unit. Since the connection with the output unit is switched, the first output unit is supplied with a signal generated by the pixel associated with the color filter of the first color. In the (j + 1) th vertical signal transfer unit, the connection with the second output unit is switched between the (j + 1) th vertical signal transfer unit and the second output unit. Is supplied with a signal generated by the pixel associated with the second color.

Similarly, in the (j + 2) th vertical signal transfer unit, the connection with the third output unit is switched between the (j + 3) th vertical signal transfer unit via the vertical signal transfer switching unit. Therefore, a signal generated by the pixel associated with the third color filter is supplied to the third output unit.

Therefore, the first color filter is generated by the associated pixel. The first signal is supplied to the first output unit, and the signal generated by the pixel associated with the second color filter is supplied to the second output unit, and the third color filter is supplied. The signal generated by the attached pixel will be supplied to the third output unit.

In another embodiment of the solid-state imaging device according to the present invention, a signal is generated in accordance with incident light by offsetting by 1/2 pixel pitch in a horizontal direction for each row so as to be zigzag in the vertical direction. And the power of the three colors of the first, second, and third colors are offset horizontally by 3/2 pixel pitch for each row, and for each row, A color fill array arranged in the order of the first color, the second color, and the third color; and provided for each of the plurality of pixels arranged in a zigzag manner with respect to a same vertical line, A plurality of vertical signal transfer units for vertically transferring signals generated by pixels in which two different color filters are alternately associated; and horizontally transferring signals vertically transferred by the vertical signal transfer unit. 1st or 3rd output part that outputs as image signal By switching and connecting the vertical signal transfer unit to two specific output units determined based on the color of the color filter associated with each pixel for each vertical signal transfer unit, The signal generated by the pixel associated with the color filter is supplied to the first output unit, and the signal generated by the pixel associated with the color filter is output to the second output unit. And a vertical signal transfer switching unit that supplies a signal generated by a pixel associated with the color of the third color to the third output unit.

In another embodiment of the solid-state imaging device according to the present invention, two specific output units connected to the vertical signal transfer unit by the vertical signal transfer switching unit are as follows.

For example, when a pixel in which a color fill of the first color and a color fill of the second color are connected to the vertical signal transfer unit, the two specific output units are the first output unit and the specific output unit. The second output unit and the two output units. Further, when a pixel in which the color filter of the second color and the color filter of the third color are connected to the vertical signal transfer unit, the specific two output units are connected to the second output unit. And a third output unit. Further, when a pixel in which the color fill of the third color and the color fill of the first color are connected to the vertical signal transfer unit, the specific two output units are connected to the third output unit. There are two output units, a power unit and a first output unit.

That is, in the vertical signal transfer switching unit, the vertical signal transfer unit connected to the pixel in which the color fill of the first color and the color fill of the second color are associated with each other includes the first output unit and the second output unit. The vertical signal transfer unit, which is connected to the two output units of the output unit and is connected to the pixel associated with the color filter of the second color and the color filter of the third color, is connected to the second output unit. A vertical signal that is switched and connected to the two output units of the third color output unit and the third output unit, and is connected to the pixel in which the third color filter and the first color filter are associated with each other. The transfer unit is switched and connected to two output units, a third output unit and a first output unit.

As a result, the signal generated by the pixel associated with the first color filter is supplied to the first output unit, and the signal generated by the pixel associated with the second color filter is supplied to the first output unit. The signal generated is supplied to the second output unit, and the signal generated by the pixel associated with the color fill of the third color is supplied to the third output unit.

In another aspect of the solid-state imaging device according to the present invention, the vertical signal transfer switching unit may switch connection between the vertical signal transfer unit and the output unit for each row.

According to another aspect of the solid-state imaging device of the present invention, the first to third output units enable signals supplied via the vertical signal transfer switching unit to be horizontally transferred and output at the same timing. May be.

According to another aspect of the solid-state imaging device of the present invention, the pixel includes: a photoelectric conversion unit that generates and accumulates electric charge according to incident light; and an amplification unit that amplifies the electric charge generated and accumulated by the photoelectric conversion unit. And an amplification type pixel having a portion.

In another aspect of the solid-state imaging device according to the present invention, the amplifying unit may be a junction-type field effect transistor.

According to another aspect of the solid-state imaging device of the present invention, the vertical signal transfer switching unit and the second

A sampling circuit for performing correlated double sampling may be provided between the first and third output units.

A buffer circuit may be provided between the first and third output units. According to another aspect of the solid-state imaging device of the present invention, signals individually output from the first to third output units are taken in association with the arrangement of the plurality of pixels, and each signal is lost in each pixel. An interpolation processing unit for interpolating a color signal using a signal associated with a pixel located around the pixel may be provided.

In another embodiment of the solid-state imaging device according to the present invention, a signal corresponding to an image conforming to the arrangement of the plurality of pixels is a square pixel having an offset of 1/2 pixel pitch in a horizontal direction for each row. An array conversion unit for converting a signal corresponding to an image conforming to the array may be provided.

Further objects and features of the present invention are as described in the attached drawings and the following description. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a diagram schematically illustrating the solid-state imaging device according to the first embodiment.

FIG. 2 is a circuit diagram of the solid-state imaging device according to the first embodiment.

FIG. 3 is a diagram showing a spatial frequency response to the solid-state imaging device according to the first embodiment.

FIG. 4 is a diagram illustrating a configuration of an imaging device according to the second embodiment.

FIG. 5 is a diagram illustrating the interpolation processing.

FIG. 6 is a diagram showing an array of data in the memory ignoring the offset.

FIG. 7 is a diagram illustrating an array conversion process.

FIG. 9 is a diagram schematically illustrating a solid-state imaging device disclosed in Japanese Patent Application Laid-Open No. 2000-12819.

FIG. 10 is a diagram schematically showing a solid-state imaging device disclosed in Japanese Patent Application Laid-Open No. 58-31688.

FIG. 11 is a view schematically showing a solid-state imaging device disclosed in Japanese Patent No. 2654081. BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<< Description of First Embodiment >>

The solid-state imaging device illustrated in FIG. 1 is an amplification-type solid-state imaging device, and a plurality of pixels are arranged in a pixel unit 1 in a state where each pixel is offset in a horizontal direction by a 1/2 pixel pitch in each row. . That is, these pixels are arranged in a zigzag manner at a pitch of 1/2 pixel in the vertical direction.

Further, in the solid-state imaging device shown in FIG. 1, the pixels arranged in zigzag in this way are connected to the same vertical signal line 2. Therefore, the pixels arranged in the arbitrary i-th row and the pixels arranged in the (i + 1) -th row are horizontally separated by 1 to 2 pixel pitches. The i-th pixel and the j-th pixel in the (i + 1) -th row are connected to the same vertical signal line 2.

That is, in the solid-state imaging device according to the first embodiment, the arrangement of pixels is similar to that of the solid-state imaging device shown in FIG. 10 (the solid-state imaging device disclosed in Japanese Patent Laid-Open No. 58-31688). The connection relationship with the vertical signal lines is different from the solid-state imaging device shown in FIG.

The solid-state imaging device shown in FIG. 1 has a vertical scanning circuit 3, a vertical signal line switching switch array 4, an output buffer array 5, a horizontal switch array 6, and a horizontal output circuit in addition to the pixel unit 1 and the vertical signal line 2. It comprises lines 7a, 7b, 7c, output amplifiers 8a, 8b, 8c, reset switches 9a, 9b, 9c, and a horizontal scanning circuit 10.

The vertical scanning circuit 3 is connected to each pixel in the pixel unit 1 for each row. The output buffer array 5 is composed of a plurality of clamped buffers 5a, 5b, and 5c (corresponding to a form of a solid-state noise suppression circuit), and each of the clamped buffers 5a, 5b, and 5c. Then, clamp-type CDS (correlated double sampling) described later is performed. The vertical signal lines 2 are connected to the buffers with clamps 5a, 5b, and 5c via the vertical signal line switching switch array 4. The horizontal switch array 6 includes horizontal scan switches 6a, 6b, and 6c provided for each of R, G, and B colors. The horizontal switch array 6 in the output buffer array 5 responds to drive pulses supplied from the horizontal scan circuit 10. The output from each buffer with clamp 5a, 5b, 5c is horizontally scanned for each color and the horizontal output lines 7a, Output to 7b and 7c. The output amplifiers 8a, 8b, 8c output the respective color signals on the horizontal output lines 7a, 7b, 7c to the outside, and the reset switches 9a, 9b, 9c output the horizontal output lines 7a, 9b, 9c. Reset the signals on a, 7b, and 7c according to the predetermined horizontal reset pulse.

Also, in the solid-state imaging device shown in FIG. 1, three color filters of R, G, and B are offset horizontally by a 3/2 pixel pitch for each row, and each row is Has a color filter array arranged in the order of R, G, B.

For example, the j-th pixel in the i-th row (corresponding to the pixel assigned (j, i) in FIG. 1) is a pixel that outputs a signal corresponding to the light transmitted through the R color filter , R signal pixels), the (j + 1) th pixel in the i-th row is a pixel that outputs a signal corresponding to the light transmitted through the G color filter (hereinafter, G signal). The (j + 2) -th pixel in the i-th row is a pixel that outputs a signal corresponding to the light transmitted through the color filter of B (hereinafter, referred to as a B signal pixel). You. Also, the j-th pixel in the (i + 1) -th row becomes a B signal pixel, the (j + 1) -th pixel in the (i + 1) -th row becomes an R signal pixel, and the (i + 1) -th row The (j + 2) th pixel is a G signal pixel.

However, FIG. 2 shows only a portion related to an arbitrary j-th pixel on the i-th row (corresponding to a pixel to which (j, i) is added in FIG. 1) for convenience.

The pixel shown in FIG. 2 is composed of a photodiode 11 that generates and accumulates electric charge according to incident light, and a junction field-effect transistor (JFET) that outputs a signal corresponding to the electric charge from a source by a source follower operation. An amplifying unit 12 comprising a JFET); a transfer unit (P-ch MOS transistor) 13 for transferring the charge from the photodiode 11 to the gate of the amplifying unit 12; and a reset unit (reset unit) for resetting the gate of the amplifying unit 12. PchMOS transistor) 14.

The transfer unit gate line 15 is connected to the gate of the transfer unit 13 and a transfer pulse is supplied. A reset section gate line 16 is connected to the gate of the reset section 14 to supply a reset pulse. A reset bias line 17 for supplying a reset bias voltage is connected to a drain of the reset unit 14. Also, in FIG. 2, signal switching switches 18a and 18b constituting the vertical signal line switching switch array 4 of FIG. 1 are provided, and correspond to the buffered buffer 5a constituting the output buffer array 5 of FIG. A vertical signal line output buffer amplifier 19, a clamp capacitor 20 (corresponding to one form of a time storage unit), and a clamp switch 21 are provided.

Further, in FIG. 2, the horizontal scanning switch 6a, the horizontal output line 7a, the output amplifier 8a, and the horizontal reset switch 9a corresponding to the horizontal scanning switch 22a, the horizontal output line 23, the output amplifier 24, and the horizontal reset switch of FIG. 25 are provided.

Hereinafter, a rough operation of the solid-state imaging device according to the first embodiment will be described with reference to FIG. 1, and thereafter, a detailed operation including a clamp type CDS (correlated double sampling) will be described with reference to FIG. Will be described.

First, a rough operation of the solid-state imaging device will be described. However, in the following, for simplicity of description, in FIG. 1, the R signal pixel to which (j, i) is added is expressed as “R signal pixel (j, i)” and the R signal pixel (j, i) The vertical signal line 2 connected to is denoted as “j-th vertical signal line 2”. The same applies to other pixels and other vertical signal lines 2.

In the solid-state imaging device shown in FIG. 1, the pixels arranged in the row selected by the vertical scanning circuit 3 are driven, and the output from the pixel is supplied to the vertical signal line 2.

For example, when the i-th row is selected by the vertical scanning circuit 3, the output from the R signal pixel (j, i) is supplied to the j-th vertical signal line 2. When the (i + 1) -th row is selected by the vertical scanning circuit 3, the output from the R signal pixel (j + 1, i + 1) is output to the (j + 1) -th vertical signal line 2. Will be supplied.

Therefore, an R color filter is associated with the j′-th vertical signal line 2 and the (j + 1) -th vertical signal line 2 according to the row selected by the vertical scanning circuit 3. The outputs from the pixels that have been supplied are supplied alternately. Similarly, the (j + 1) th vertical signal line 2 and the (j + 2) th vertical signal line 2 alternately supply the output from the pixel to which the G color filter is assigned. The (j + 2) th vertical signal line 2 and the (j + 3) th vertical signal line 2 are alternately supplied with the output from the pixel to which the B color filter is applied. Will be. The vertical signal line switching switch array 4 can supply the output from the pixel associated with the same color filter to each of the buffered buffers 5a, 5b, and 5c in the output buffer array 5. Then, each signal line switching switch is switched. For example, focusing on the buffer with clamp 5 a, when the i-th row is selected by the vertical scanning circuit 3, the j-th vertical signal line 2 is connected to the buffer with clamp 5 a and (i +1) When the row is selected, the (j + 1) th vertical signal line 2 is connected to the buffer with clamp 5a. Therefore, the output of the R signal pixel connected to the jth vertical signal line 2 and the output of the R signal pixel connected to the (j + 1) th vertical signal line 2 are output to the buffer 5a with clamp. And will be supplied sequentially.

Similarly, for the buffer 5b with clamp, the output of the G signal pixel connected to the (j + 1) th vertical signal line 2 and the (j + 2) th vertical signal line 2 The output of the connected G signal pixel is sequentially supplied. Further, for the buffer with clamp 5c, the output of the B signal pixel connected to the (j + 2) th vertical signal line 2 and the output of the (j + 3) th vertical signal line 2 The output of the B signal pixel is sequentially supplied.

The clamped buffers 5a, 5b, and 5c output valid signals (corresponding to the photosensitive signal Vp—dark signal Vd) by the clamp-type CDS (correlated double sampling) described later. You.

Each of the horizontal scanning switches 6a, 6b, 6c in the horizontal switch array 6 is simultaneously turned on in response to a horizontal read pulse supplied from the horizontal scanning circuit 10. Therefore, the valid signals output from the buffers with clamps 5a, 5b, 5c are simultaneously supplied to the horizontal output lines 7a, 7b, 7c for each color.

For example, when the i-th row is selected by the vertical scanning circuit 3, a valid signal for the R signal pixel (j, i) is supplied to the horizontal output line 7a from the buffer with clamp 5a, and the buffer with clamp 5 b outputs a valid signal for the G signal pixel (j + l, i) to the horizontal output line 7b, and the clamped buffer 5c outputs a valid signal for the B signal pixel (j + 2, i). It is supplied to horizontal output line 7c.

The horizontal output lines 7a, 7b, and 7b are set by reset switches 9a, 9b, and 9c. When the signal on 7c is reset and the (i + 1) -th row is selected by the vertical scanning circuit 3, the horizontal output line 7a has a valid signal for the R signal pixel (j + l, i + 1). A valid signal for the G signal pixel (j + 2, i + 1) is supplied to the horizontal output line 7b, and the B signal pixel (j + 3, i + 1) is supplied to the horizontal output line 7c. ) Is supplied.

As a result, an R signal is output from the output amplifier 8a, a G signal is output from the output amplifier 8b, and a B signal is output from the output amplifier 8c.

That is, since the solid-state imaging device according to the first embodiment can perform independent three-line output for each color, it can output image signals corresponding to three color signals at high speed. In the solid-state imaging device according to the first embodiment, a color filter array in which color filters of three colors of;, G, and B are arranged is provided. Even if a color filter array in which color filters of (white) and Μ (magenta) and color filters of Υ (yellow), W (white) and C (cyan) are arranged is provided. Independent three-line output can be performed for each color.

Further, the solid-state imaging device according to the first embodiment is different from the solid-state imaging device disclosed in Japanese Patent Application Laid-Open No. 58-31688, in that each line is formed using a primary color color filter. The charge can be read. Therefore, the color reproducibility and the vertical resolution can be maintained higher than those of the solid-state imaging device disclosed in Japanese Patent Application No. 58-316688.

Further, in the signal processing at the subsequent stage of the solid-state imaging device according to the first embodiment, the matrix mixing required in the solid-state imaging device disclosed in Japanese Patent Laid-Open No. 58-31688 is unnecessary. Yes, offset correction and gain correction between the three output lines can be performed in the same way as normal RGB signal correction. Therefore, errors due to these corrections do not adversely affect the image quality.

Hereinafter, with reference to FIG. 2, a detailed operation of the solid-state imaging device according to the first embodiment will be described focusing on a clamp type CDS (correlated double sampling).

First, when the i-th row is in the non-selected state, in the pixel shown in FIG. 2, the photodiode 11 generates and accumulates electric charges according to incident light. In addition, a low-level transfer pulse indicating off via the transfer unit gate line 15 is applied to the gate of the transfer unit 13. Is supplied, and the photodiode 11 is separated from the amplifier 12. Further, a reset pulse of ON level indicating ON is supplied to the gate of the reset unit 14 via the reset unit gate line 16, and the gate of the amplifier unit 12 is reset by the reset bias line 17. Fixed at the bias voltage. That is, the amplifier unit 12 holds the non-selected state, and there is no signal output from the pixel to the vertical signal line 2.

Next, when the i-th row is selected and the signal switching switch 18a is turned on and the signal switching switch 18b is turned off, the charge readout from the photodiode .11 is performed as follows. It is done.

First, the reset pulse supplied to the gate of the reset section 14 via the reset section gate line 16 is changed from low level (indicating ON) to high level (indicating OFF), and the reset section 14 is reset. When turned off, the gate of the amplifier section 12 is biased to the read voltage through the power coupling capacitance with the reset gate line 16. Therefore, the dark signal Vd is output to the vertical signal line 2. The 喑 signal Vd is a signal that includes noise when the amplifying unit 12 is reset, solid pattern noise, and the like.

At this time, the horizontal clamp switch 21 is on, the horizontal switch 22 side of the clamp capacitor 20 is fixed to the reference voltage Vref, and the dark signal Vd is accumulated in the clamp capacitor 20. .

Next, when the horizontal clamp switch 21 is turned off, the horizontal switch 22 side of the clamp capacitor 20 is in a floating state. At this time, when the transfer pulse supplied to the gate of the transfer section 12 via the transfer section gate line 15 changes from a high level (indicating ON) to a single level (indicating OFF), the photo The charge stored in the diode 11 is transferred to the gate of the amplifier 12. Therefore, a photosensitive signal V p (corresponding to a signal obtained by superimposing the 喑 signal V d on an effective signal) corresponding to such charges is output to the vertical signal line output buffer 19, and the clamp capacitance 20 is output. Receives the exposure signal VP. At this time, the above-mentioned signal Vd is already held in the clamp capacitor 20.

Therefore, a valid signal in which the dark signal Vd is removed from the photosensitive signal VP is output from the horizontal scanning switch 22 of the clamp capacitor 20. That is, This means that clamp-type CDS (correlated double sampling) has been realized via the clamp capacitor 20.

In this state, when the horizontal scan switch 22 is turned on after the horizontal reset switch 25 is turned on and off and the horizontal output line 23 is reset, a valid signal is output from the output amplifier 24. Will be done.

As described above, according to the solid-state imaging device of the first embodiment, noise when resetting the amplification unit 12 and solid-state power noise are removed by the clamp-type CDS (correlated double sampling). The obtained image signal can be obtained.

In addition, in the solid-state imaging device according to the first embodiment, when the clamp type CDS (correlated double sampling) is performed, the clamp capacitors 20 functioning as a temporary storage unit can be provided by the number of pixels per row. good. Therefore, the fixed pattern noise can be suppressed while the circuit scale is suppressed, and the solid-state imaging device shown in FIG. 10 (the solid-state imaging device disclosed in Japanese Patent Laid-Open No. 58-31688) and Miniaturization, which has been difficult with the solid-state imaging device shown in FIG. 11 (the solid-state imaging device disclosed in Japanese Patent No. 2654081), can be easily realized.

Further, the solid-state imaging device according to the first embodiment is an amplification-type solid-state imaging device including an amplification unit 12 composed of a JFET. Such an amplification unit 12 connects the vertical signal line 2 to a low impedance. , Voltage fluctuations of the vertical signal line 2 due to noise generated when the switching switches 18a and 18b are switched can be suppressed. Further, in the solid-state imaging device according to the first embodiment, since the vertical signal line output buffer amplifier 19 is provided between the signal switching switches 18 a and 18 b and the clamp capacitance 20, the clamp capacitance 20 Therefore, the effect of noise generated when the signal switching switches 18a and 18b are switched can be reduced.

In the first embodiment, the solid-state imaging device including the amplifying unit 12 composed of the JFET has been described as an example. However, the present invention is not limited to the solid-state imaging device having such a configuration, and a MOS transistor may be used. Also, the present invention can be applied to a solid-state imaging device provided with an amplifying unit including a bipolar transistor.

In the first embodiment, an embedded photodiode may be used as the photodiode 11 in order to reduce the occurrence of a dark signal and the like. Here, the resolution of an image obtained by an imaging device (for example, an electronic camera or the like) having the solid-state imaging device of the first embodiment will be examined.

FIG. 3 is a diagram illustrating a spatial frequency response to the solid-state imaging device according to the first embodiment.

In FIG. 3, f s V is a spatial frequency determined by a vertical sampling pitch, and f sh is a spatial frequency determined by a horizontal pixel pitch of each row. However, in FIG. 3, the basic pitch is the same in the horizontal and vertical directions, and the phase is ignored. For simplicity, only the first quadrant is shown.

The 図 (circle) marks in the figure indicate the positions at which modulated carriers occur in achromatic colors. In the first embodiment, since a plurality of pixels are arranged in a state of being offset by 1/2 pixel pitch in the horizontal direction for each row, the carrier in the horizontal 0 degree direction is (2 f sh, 0) The closest carrier occurs at (0, f sv), and the next closest carrier occurs at (fsh, 1/2 · fsv). As a result, the achromatic signal reproduction range (two-dimensional Nyquist range) in the state of white balance is the area A and B in the figure.

The mouth (square) in the figure is the position where carriers of each color of R, G, B are generated. The closest carrier occurs at (1/3 · fsh, 1/2 · fsv), the next closest carrier occurs at (SZS 'fsh, 0), and an image with resolution near these two carriers. Causes color moiré. The gamut of the chromatic signal without moiré (two-dimensional Nyquist range of the color signal) is the area A in the figure.

Usually, in an image pickup device having a single-plate solid-state image pickup device, an OLPF (Optical Low Pass Filter) is arranged in front of the solid-state image pickup device to suppress color moiré. The 0 L PF to be disposed before the solid-state imaging device according to the first embodiment can be configured by combining a birefringent plate having a notch at the position of the C line and the D line in the figure.

In the imaging by the imaging device in which the 0 LPF having such a configuration is arranged in front of the solid-state imaging device of the first embodiment, the luminance signal close to achromatic can reproduce the regions A and B almost as theoretically. . Such a region is a two-dimensional Nyquist range in a solid-state imaging device having a square pixel array having the same basic pixel pitch and the same number of pixels, that is, (1/2 · f It is almost equivalent to the area enclosed by the (sh, y) line and the (x, 1/2 · fsv) line. That is, the solid-state imaging device according to the first embodiment is a single-chip solid-state imaging device, but is comparable to a black-and-white solid-state imaging device having a square pixel array having the same number of pixels when capturing an object that is close to achromatic. High resolution can be realized.

By the way, since each pixel of the single-chip solid-state imaging device is associated with only one color filter of the three colors R, G, and B, color signals of the other two colors are lost. I have. Therefore, in an imaging device having a single-plate solid-state imaging device, an interpolation process for interpolating two color signals missing in each pixel is performed. However, an image signal obtained by the solid-state imaging device according to the first embodiment is subjected to interpolation processing performed by an existing imaging device (an imaging device having a single-plate solid-state imaging device having a square pixel array). It cannot be applied as is.

Therefore, in a second embodiment, an imaging device that performs interpolation processing on an image signal output from the solid-state imaging device of the first embodiment and records the image signal will be described.

<< Description of Second Embodiment >>

In FIG. 4, a solid-state imaging device 41 is the solid-state imaging device of the first embodiment. The imaging device shown in FIG. 4 includes, in addition to the solid-state imaging device 41, a timing generator circuit 42, analog front-end circuits 43a, 43b, 43c, and AD conversion circuits 44a, 44b, 44. c, a pixel interpolation circuit 45, a memory 46, a square pixel array conversion circuit 47, and a recording device 48. In addition, it is assumed that an imaging optical system (not shown) and the above-described 0 LPF are provided in front of the solid-state imaging device 41.

The evening imaging generator circuit 42 includes a drive pulse 49 for driving the solid-state imaging device 41 and a control pulse for controlling other circuits in the imaging device in accordance with a sequence control signal supplied from a sequence control unit (not shown). Generates control signal 50.

The analog front-end circuits 43a, 43b, and 43c perform DC reproduction (clamping) and sensitivity adjustment (gain) for the R, G, and B color signals supplied as image signals from the solid-state imaging device 41. ), And perform processing such as offset adjustment.

The color signal of each color subjected to such processing is subjected to AD conversion by AD conversion circuits 44a, 44b, and 44c, and is supplied to a pixel interpolation circuit 45. The pixel interpolation circuit 45 performs an interpolation process described later on the color signals of the respective colors supplied in this manner, and supplies the color signals to the square pixel array conversion circuit 47.

The square pixel array conversion circuit 47 performs an array conversion process described later on the color signals of each color supplied from the pixel interpolation circuit 45 and supplies the color signals to the recording device 48.

The recording device 48 records the color signal of each color supplied from the square pixel array conversion circuit 47 on a predetermined recording medium, but in some cases, such as gamma conversion, color space conversion, sub-sampling, image compression, etc. Signal processing may be performed.

Hereinafter, the interpolation processing performed by the pixel interpolation circuit 45 will be described, and then the array conversion processing performed by the square pixel array conversion circuit 47 will be described.

The pixel interpolation circuit 45 associates data corresponding to the color signals of each color digitized by the AD conversion circuits 44 a, 44 b, and 44 c with the arrangement of pixels in the solid-state imaging device 41. Store in memory 46. Then, a color signal missing in each pixel is interpolated based on a predetermined interpolation formula.

For example, when interpolating an R signal to a G signal pixel, an interpolation formula for averaging the R signals obtained from adjacent R signal pixels with a weight corresponding to the reciprocal of the distance between the pixels may be applied. .

FIG. 5 is a diagram illustrating the interpolation processing performed in this manner.

In Fig. 5, when the R signal is interpolated into the G signal pixel, three R signal pixels adjacent to the G signal pixel (an R signal pixel adjacent to the left direction and an R signal pixel adjacent to the right diagonal upward direction) This indicates that the R signal obtained from the R signal pixel adjacent in the diagonally lower right direction is referred to. When a B signal is interpolated to a G signal pixel, three B signal pixels adjacent to the G signal pixel (a B signal pixel adjacent to the right direction, a B signal pixel adjacent to the diagonally upper left direction, and a left B signal pixel This indicates that the B signal obtained from the B signal pixel that is close to the diagonally downward direction is referred to. Further, in the case of the interpolation for the B signal pixel and the R signal pixel, the color signal obtained from the neighboring pixel is similarly referred to.

In other words, when interpolating two color signals that are missing in an arbitrary pixel, the pixel to be interpolated is a pixel that is close to the left, a pixel that is close to the upper right, and a pixel that is closer to the lower right. Interpolate the first color signal with reference to the color signal obtained from the pixel Then, with reference to the color signals obtained from the pixels that are close to the right, the pixels that are close to the upper left, and the pixels that are close to the lower left, the second What is necessary is to interpolate the color signal.

By the way, since the pixels in the solid-state imaging device 41 are offset by a half pixel pitch for each row, the color signal of each color supplied from the AD conversion circuits 44a, 44b, and 44c is provided. In order to store the data corresponding to in the memory 46 in a manner that is faithfully associated with the actual pixel arrangement, a pseudo empty data must be inserted at a position where no pixel exists. Therefore, twice as much space is required as storing only valid data ο

Therefore, in the actual interpolation processing, it is preferable to ignore the offset of the 1/2 pixel pitch in the solid-state imaging device 41 and store the offset as a square pixel array.

FIG. 6 is a diagram showing an array of data in the memory 46 ignoring the offset. FIG. 6 shows a case where the even rows are offset rightward by a 1/2 pixel pitch. Further, a position corresponding to the actual pixel arrangement in the solid-state imaging device 41 is referred to as “real space position”, and the pixel arrangement ignoring the offset is referred to as “memory arrangement”.

However, in the in-memory array where the offset is ignored, it is necessary to switch the interpolation method between the interpolation for the pixels arranged in the even rows and the interpolation for the pixels arranged in the odd rows.

For example, for the G signal pixels arranged in even rows, the R signal is interpolated by referring to the data of the R signal pixels arranged in the left, diagonally upward, and diagonally right directions. The B signal is interpolated with reference to the data of the B signal pixels arranged in the up, down, and up directions. On the other hand, for the G signal pixels arranged in odd rows, the R signal is interpolated by referring to the data of the R signal pixels arranged leftward, upward, and downward, O Interpolates the B signal with reference to the data of the B signal pixels arranged diagonally down left o

By the way, the color signal of each color in the state where the interpolation processing is performed in this manner is an array of pixels in the solid-state imaging device 41 (an array in which each pixel is offset by 1Z2 pixel pitch for each row). This corresponds to an image conforming to. Therefore, for example, the data of the G signal at the time when it is supplied to the square pixel array conversion circuit 47 is arranged at a position shifted by one pixel pitch and two pixel pitches for each row as shown by “G” in FIG. Will be. However, in FIG. 7, the position of each pixel in the square pixel array is indicated by □ (square), and the case where the even-numbered row is offset rightward by 1 Z 2 pixel pitch is shown. The same position is used for the R and B signals.

The square pixel array conversion circuit 47 performs an array conversion process of converting such color signals of each color into a signal corresponding to an image conforming to the square pixel array.

The square pixel array conversion circuit 47 realizes, for example, an array conversion process for the G signal by interpolating the G signal at a position indicated by “g” in FIG. Note that such interpolation can be performed by averaging the data of the G signal adjacent to the upper, lower, left, and right directions in even rows, as in the interpolation method 1 in FIG. As shown in 2, this can be done by averaging the data of the G signals that are adjacent in two directions, left and right.

In addition, the square pixel array conversion circuit 47 performs array conversion processing on the R signal and the B signal in the same manner as the G signal. Then, the color signals of the respective colors for which the array conversion processing has been completed are supplied to the recording device 48.

As described above, in the imaging device of the second embodiment, the solid-state imaging device in which the arrangement of each pixel is offset by 1 pixel pitch for each row (corresponding to the solid-state imaging device of the first embodiment) ) Can be reliably interpolated for the image signal output from.

Further, in the imaging device according to the second embodiment, an image signal on which interpolation processing has been performed can be converted into an image signal conforming to a square pixel array. Therefore, various types of signal processing conventionally performed can be easily applied to the image signal obtained by the imaging device according to the second embodiment.

In addition, in the imaging device according to the second embodiment, a smoother image can be obtained by applying an interpolation process that quadruples the number of pixels. Industrial applicability

In the solid-state imaging device of the present invention, different zigzag arrangements are provided in the vertical direction. A vertical signal transfer unit is provided for each pixel in which the color fills are alternately associated, and the vertical signal transfer switching unit generates the pixels by the pixels in which the color fills are associated. A signal can be output from the first output unit, and a signal generated by a pixel associated with the color filter of the second color can be output from the second output unit. A signal generated by the pixel associated with the filter can be output from the third output unit.

In other words, a plurality of pixels are arranged in a state where each pixel is offset in the horizontal direction by a 1/2 pixel pitch, and a first color, a second color, and a third color are filled in a row. In a solid-state imaging device having a color filter array that is offset in the horizontal direction by a 3/2 pixel pitch every time, and for each row, a first color, a second color, and a third color are arranged in this order. However, independent 3-wire output for each color can be realized. Also, the number of vertical signal lines may be the same as the number of pixels per row, and there is no need to pass two vertical signal lines between pixels, so that an unnecessary increase in the number of vertical signal lines can be suppressed.

In particular, when the connection between the vertical signal transfer unit and the output unit is switched for each row by the vertical signal transfer switching unit, the resolution in the vertical direction can be reliably maintained high. Also, when the signals supplied via the vertical signal transfer switching unit are horizontally transferred and output at the same timing by the first to third output units, the image signal can be output reliably and at high speed. it can.

Furthermore, when the solid-state imaging device of the present invention is an amplification-type solid-state imaging device having amplification pixels, the vertical signal transfer unit can be driven with a low impedance voltage, so that the vertical signal transfer unit is switched to the output unit. Voltage fluctuations in the vertical signal transfer unit due to noise generated when connecting to the terminal can be suppressed. When a sampling circuit for performing correlated double sampling is provided between the vertical signal transfer switching unit and the first to third output units, noise or noise generated when the amplification unit is reset by correlated double sampling is provided. Therefore, the effects of solid pattern noise and the like can be reduced. Further, when a buffer circuit is provided between the vertical signal transfer switching section and the first to third output sections, the influence of noise generated when the vertical signal transfer section is switched and connected to the output section is reduced. It can be reduced. Therefore, a highly accurate image signal can be obtained.

Further, the signals individually output from the first to third output units are output to the plurality of pixels. In the case where an interpolation processing unit is provided that interpolates the two color signals missing in each pixel by using the signals associated with the pixels located around the pixel, the interpolation processing unit interpolates the signals of the two colors missing in each pixel. The missing two-color signals are interpolated using the signals associated with the pixels located in the vicinity, and the three-color signals can be associated with all the pixels. Furthermore, a signal corresponding to an image conforming to an array of a plurality of pixels is converted into a signal corresponding to an image conforming to a square pixel array in which offsets are not performed at a half pixel pitch in the horizontal direction for each row. When an array conversion unit for conversion is provided, it is possible to obtain an image signal that can be handled in the same manner as a pixel signal obtained by a single-chip solid-state imaging device having a square pixel array.

Claims

The scope of the claims

1. A plurality of pixels that are arranged in a zigzag manner in the vertical direction by being offset by 1/2 pixel pitch in the horizontal direction for each row, and generate a signal corresponding to incident light;

The first color, the second color, and the third color of the three colors are offset horizontally by three pixels by two pixel pitches for each row, and the first color and the second color for each row. A color-filled array arranged in the order of color, third color,

A plurality of vertical signal transfer units provided for each pixel arranged in a zigzag manner with respect to the same straight line in the vertical direction among the plurality of pixels, and for vertically transferring a signal generated by the pixel;

First to third output units for horizontally transferring a signal vertically transferred by the vertical signal transfer unit and outputting the image signal as an image signal;

For each of two adjacent vertical signal transfer units among the plurality of vertical signal transfer units, a specific one determined based on what color the color fill of the same color associated with each pixel is. By switching and connecting the two vertical signal transfer units to the output unit, a signal generated by the pixel associated with the color fill of the first color is supplied to the first output unit, A signal generated by the pixel associated with the color filter of the second color is supplied to the second output unit, and a signal generated by the pixel associated with the color filter of the third color is supplied to the second output unit. Vertical signal transfer switching unit to supply to the output unit

A solid-state imaging device comprising:

2. A plurality of pixels that are arranged in a zigzag manner in the vertical direction by offsetting by one pixel pitch in the horizontal direction for each row and generate a signal corresponding to the incident light;

Color fills of the first, second, and third colors are offset horizontally by 32 pixel pitches for each row, and the first and second colors are set for each row. A color filter array arranged in the order of the third color,

Pixels arranged in zigzag with respect to the same vertical line among the plurality of pixels A plurality of vertical signal transfer units that are provided for each pixel and vertically transfer signals generated by pixels in which two different color filters are alternately associated;

By switching and connecting the vertical signal transfer unit to two specific output units determined based on the color of the color corresponding to each pixel for each vertical signal transfer unit, A signal generated by a pixel associated with a color of one color is supplied to a first output unit, and a signal generated by a pixel associated with a color of a second color is supplied to a second output unit. A vertical signal conversion switching unit for supplying a signal generated by a pixel associated with the color of the third color to the third output unit.

A solid-state imaging device comprising:

3. The solid-state imaging device according to claim 1 or 2, wherein the vertical signal transfer switching unit includes:

Switch connection between vertical signal transfer unit and output unit for each row

A solid-state imaging device characterized by the above-mentioned.

4. In the solid-state imaging device according to any one of claims 1 to 3,

The first to third output units are:

The signals supplied via the vertical signal transfer switching section are horizontally transferred and output at the same timing.

A solid-state imaging device characterized by the above-mentioned.

5. In the solid-state imaging device according to any one of claims 1 to 4,

The pixel is

A solid-state imaging device, comprising: an amplifying pixel having a photoelectric conversion unit that generates and accumulates electric charge corresponding to incident light, and an amplification unit that amplifies the electric charge generated and accumulated by the photoelectric conversion unit. .

6. The solid-state imaging device according to claim 5, The amplification unit,

It is a junction type field effect transistor

A solid-state imaging device characterized by the above-mentioned.

7. The solid-state imaging device according to claim 5, wherein the sampling circuit performs correlated double sampling between the vertical signal transfer switching unit and the first to third output units.

A solid-state imaging device comprising:

8. In the solid-state imaging device according to any one of claims 1 to 7,

A solid-state imaging device comprising a buffer circuit between the vertical signal transfer switching unit and the first to third output units.

9. In the solid-state imaging device according to any one of claims 1 to 8,

The signals individually output from the first to third output units are fetched in association with the array of the plurality of pixels, and the two-color signals missing in each pixel are input to the pixels located around the pixel. An interpolation processing unit that performs interpolation using the associated signal

A solid-state imaging device comprising:

10. The solid-state imaging device according to any one of claims 1 to 9, wherein:

A signal corresponding to an image conforming to the arrangement of the plurality of pixels is converted into a signal corresponding to an image conforming to a square pixel arrangement in which offset is not performed at a 1/2 pixel pitch in the horizontal direction for each row. Array conversion unit

A solid-state imaging device comprising: