WO2002077654A1 - Procede permettant de detecter la dose de porteurs dans une plaquette en semi-conducteur - Google Patents

Procede permettant de detecter la dose de porteurs dans une plaquette en semi-conducteur Download PDF

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Publication number
WO2002077654A1
WO2002077654A1 PCT/US2002/008418 US0208418W WO02077654A1 WO 2002077654 A1 WO2002077654 A1 WO 2002077654A1 US 0208418 W US0208418 W US 0208418W WO 02077654 A1 WO02077654 A1 WO 02077654A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor wafer
test volume
determining
set forth
probe tip
Prior art date
Application number
PCT/US2002/008418
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English (en)
Inventor
William H. Howland
Robert J. Hillard
Original Assignee
Solid State Measurements, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Solid State Measurements, Inc. filed Critical Solid State Measurements, Inc.
Priority to US10/472,342 priority Critical patent/US20040108869A1/en
Priority to JP2002575653A priority patent/JP2004526319A/ja
Priority to EP02721475A priority patent/EP1377842A4/fr
Publication of WO2002077654A1 publication Critical patent/WO2002077654A1/fr

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302—Contactless testing
    • G01R31/312—Contactless testing by capacitive methods
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2648—Characterising semiconductor materials
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2831—Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means

Definitions

  • the present invention relates to measuring electrical properties of a product semiconductor wafer. Description of Related Art
  • V T threshold voltage
  • V ⁇ is most sensitive to carrier density profile in the channel region of a MOS transistor. Ion implantation into the channel region is used to produce the channel profile since it allows precise adjustment of V T .
  • the gate equivalent oxide thickness has decreased to as low as 15 angstroms. Hence, a higher channel doping level is required in order to maintain V T at an appropriate level and to control off-state leakage and to improve gate control of the channel charge. This makes tight control of V ⁇ more critical and, hence, more difficult.
  • V T monitor wafers are used to measure V T whereupon the measured value of V T can be utilized to adjust the ion implant of the channel regions of a product wafer.
  • the measuring means In order to measure V ⁇ on product wafers, the measuring means must be non-contaminating, non-damaging, fast, and capable of measuring V T in product wafer scribe lines or test volumes.
  • a probe having an elastically deformable, electrically conductive tip.
  • the probe tip is caused to contact a dielectric layer overlaying at least a portion of one of the scribe lines of the semiconductor wafer thereby forming a metal-oxide-semiconductor (MOS) structure.
  • MOS metal-oxide-semiconductor
  • the probe tip has a contact area that is received within said scribe line when the probe tip contacts the dielectric layer.
  • a capacitance-voltage (CV), current-voltage (IV), conductance- voltage (GV) or capacitance-time (Ct) type electrical stimulus is applied to the MOS structure.
  • a response of the MOS structure to the electrical stimulus is measured and from the response at least one property of the dielectric layer, the semiconductor wafer and/or the interface therebetween is determined.
  • the probe contacts the dielectric layer with a force whereby the probe tip elastically deforms within its elastic limits.
  • the semiconducting material comprising the semiconductor wafer can include an ion implanted dopant received in a test volume underlying the dielectric layer contacted by the probe tip.
  • the step of applying the stimulus includes the steps of superimposing an AC voltage on a DC voltage and sweeping the DC voltage between a first, starting voltage and a second, ending voltage.
  • the step of measuring the response includes the step of acquiring capacitance values during the sweep of the DC voltage.
  • the determining step includes the step of determining a dopant concentration in at least one layer of the test volume as a function of the acquired capacitance values and the voltage at which each capacitance value is acquired.
  • a dopant implant dose can be determined in the test volume as a function of the dopant concentration in a plurality of layers of the test volume. The plurality of layers extend from adjacent the surface of the test volume in a direction into the test volume away from the surface.
  • the method can further include determining from the acquired capacitance values a minimum capacitance value (C mm ) of the test volume.
  • C mm minimum capacitance value
  • the value for C m ⁇ n occurs when the test volume is depleted of majority carriers and a net recombination of majority carriers and minority carriers in or adjacent the test volume is at equilibrium. From the value for Cmm . a maximum space-charge depth of the test volume is determined. The maximum space-charge depth is a distance from the surface of the test volume where the depleted majority carriers reside when the test volume is at equilibrium. An average doping concentration in the test volume can then be determined from the maximum space-charge depth. A threshold voltage value V T can also be determined from the acquired capacitance values. [0011] Comparisons of average doping concentrations of a reference semiconductor wafer and one or more semiconductor wafers under test can be utilized to determine if an ion implant process for the semiconductor wafers under test is varying outside of an acceptable tolerance.
  • a method of determining one or more properties of a semiconductor wafer that includes providing a semiconductor wafer having a pattern of integrated circuits formed thereon and scribe lines separating the integrating circuits from one another.
  • a probe is provided having an elastically deformable, electrically conductive tip. The probe tip is caused to contact at least a portion of one of the scribe lines of the semiconductor wafer. The probe tip has a contact area that is received within the scribe line.
  • An electrical stimulus is applied between the probe tip and the semiconductor wafer and the response of the semiconductor wafer to the electrical stimulus is measured. From the response, at least one property of the semiconductor wafer is determined.
  • the semiconducting material comprising the semiconductor wafer can include an ion implanted dopant received in a test volume underlying the contact between the probe tip and the semiconductor wafer.
  • the determining step includes the step of determining a dopant concentration in at least one layer of the test volume as a function of the acquired capacitance values.
  • Fig. 1 is a cross sectional side view of a conductive probe contacting a scribe line of a patterned semiconductor wafer having an overlaying dielectric layer and a test volume formed in the scribe line;
  • FIG. 2 is an isolated perspective view of a portion of a patterned semiconductor wafer with probe tips contacting scribe lines having a dielectric layer overlaying test volumes formed in the scribe lines:
  • Fig. 3a is a capacitance versus voltage plot of a test volume and dielectric layer acquired utilizing the conductive probe shown in Fig. 1 ;
  • Fig. 3b is a plot derived from the capacitance versus voltage plot shown in Fig. 3a;
  • Fig. 3c is a plot of implant dopant concentration of the test volume determined from the plot shown in Fig. 3b;
  • Fig. 4 is a capacitance versus voltage plot for a forward and reverse voltage sweep of a test volume and dielectric layer acquired utilizing the conductive probe shown in Fig. 1 ;
  • FIG. 5 is an isolated perspective view of a portion of a patterned semiconductor with probe tips contacting scribe lines having a dielectric layer overlaying the bulk semiconducting material forming the semiconductor wafer;
  • Fig. 6 is an isolated perspective view of a portion of a patterned semiconductor with probe tips contacting the bulk semiconducting material forming the semiconductor wafer in scribe lines where test volumes are formed;
  • Fig. 7 is an isolated perspective view of a portion of a patterned semiconductor with probe tips contacting the bulk semiconducting material forming the semiconductor wafer in scribe lines.
  • an apparatus 2 for measuring an implant dose or an implant concentration of a semiconductor wafer 8 having an overlaying dielectric layer 4 includes a vacuum chuck 10 which holds a back surface 12 of semiconductor wafer 8 by means of vacuum.
  • chuck 10 is moveable vertically up and down as shown by arrow 14 in Fig. 1.
  • Apparatus 2 also includes a probe 20 having a shaft 22 with a conductive tip 24 at one end thereof. Probe 20 is also moveable vertically up and down as shown by arrow 14.
  • a means for applying electrical stimulus 32 and a measurement means 34 are connected in parallel between conductive tip 24 and chuck 10.
  • Chuck 10 is typically connected to a reference ground. However, this is not to be construed as limiting the invention since chuck 10 can alternatively be connected to an AC or DC reference bias.
  • Conductive tip 24 is formed from an elastically deformable material such as a smooth, highly polished metal, e.g., tantalum, a conductive elastomer or a conductive polymer.
  • Conductive tip 24 preferably has a hemispherical shape having a radius of curvature between 10 micrometers and 100 centimeters. However, this is not to be construed as limiting the invention.
  • semiconductor wafer 8 is a product semiconductor wafer
  • semiconductor wafer 8 includes a pattern of integrated circuits 40 separated by scribe lines 42 in a manner known in the art.
  • one or more select volumes of each integrated circuit 40 are ion implanted with a suitable dopant which creates a potential difference between each of these volumes and the bulk semiconducting material surrounding each of these implanted volumes.
  • test volumes 44 of semiconductor wafer 8 are also ion implanted.
  • Each test volume 44 is formed in one of the scribe lines 42 between two integrated circuits 40 or at the intersection of two transverse scribe lines 42.
  • dielectric layer 4 is formed over the top surface of each test volume 44. Dielectric layer 4 can be simultaneously formed over test volumes 44 and integrated circuits 40 or can be formed over test volumes 44 and integrated circuits 40 at different times.
  • Fig. 2 the outline of conductive tip 24 of probe 20 is shown received on the surface of dielectric layer 4 overlaying each test volume 44.
  • the mechanical contact area between conductive tip 24 of probe 20 and dielectric layer 4 overlaying each test volume 44 can be determined by the well-known Hertzian formula related to elastic contacts between spherical and flat bodies.
  • dopant ions implanted into semiconductor wafer 8 come to rest at different depths from top surface 6 of semiconductor wafer 8 based upon, among other things, the kinetic energy of each ion striking semiconductor wafer 8 and the crystal structure where each ion impacts semiconductor wafer 8.
  • the ion concentration, i.e., ions/cm 3 of each layer of semiconductor wafer 8 from top surface 6 will vary.
  • implant dose i.e., ions/cm 2
  • ion implanted test volumes 44 formed in scribe lines 42 or at the intersection of transverse scribe lines 42 in semiconductor wafer 8.
  • conductive tip 24 of probe 20 is brought into contact with dielectric layer 4 overlaying each ion implanted test volume 44. While a single probe 20 can be utilized to sequentially determine the implant dose of each test volume 44 of semiconductor wafer 8, multiple probes 20 coupled to a common test fixture (not shown) can be utilized to acquire from multiple test volumes 44 data from which the implant dose of each test volume can be determined. The acquisition of data and the determination of implant dose from one test volume 44 will now be described with reference to Figs.
  • contact forming means 30 causes conductive tip 24 to contact dielectric layer 4 overlaying ion implanted test volume 44 of semiconductor wafer 8 thereby forming a MOS test structure. More specifically, the combination of conductive tip 24, dielectric layer 4 and semiconductor wafer 8 forms the MOS test structure.
  • means for applying electrical stimulus 32 applies a suitable capacitance-voltage (CV), current-voltage (IV), conductance-voltage (GV) or capacitance-time (Ct) type electrical stimulus to this MOS test structure.
  • CV capacitance-voltage
  • IV current-voltage
  • GV conductance-voltage
  • Ct capacitance-time
  • Means for applying electrical stimulus 32 applies to the MOS test structure a CV type electrical stimulus comprising an AC voltage superimposed on a DC voltage which is swept from a first, starting voltage 50 to a second, ending voltage 52.
  • capacitance values of the MOS test structure are acquired.
  • An exemplary plot of acquired capacitance values versus voltage is shown in Fig. 3a.
  • the inverse of the acquired capacitance values squared, i.e., 1/C versus voltage is determined.
  • a plot of 1/C 2 versus voltage is shown in Fig. 3b.
  • the following equation 1 is utilized to determine the implant concentration N w for values of 1/C 2 between starting voltage 50 and ending voltage 52. EQ 1: -d(l/c 2 dV qe s N w A
  • FIG. 3c A plot of N w versus distance W is shown in Fig. 3c.
  • the implant concentration does not have a determinable value for a distance 60 from top surface 6 of semiconductor wafer 8.
  • the dopant concentration increases with increasing distance W from top surface 6 of semiconductor wafer 8 until it reaches a peak value 62. Thereafter, with further increasing distance W from top surface 6, the dopant concentration decreases until it reaches a steady state value N sub at a distance L from top surface 6.
  • the value of N sub is indicative of residual ions trapped in semiconductor wafer 8 during growing of the ingot from which semiconductor wafer 8 was extracted.
  • the position of peak value 62 of N w versus W can be adjusted toward or away from top surface 6 of semiconductor wafer 8 by adjusting the depth to which the dopant ions are implanted into semiconductor wafer 8. For example, dopant ions implanted closer to top surface 6 will cause peak value 62 to shift toward the N w axis in Fig. 3c while dopant ions implanted further away from top surface 6 will cause peak value 62 to shift away from the N w axis in Fig. 3c.
  • equations 1 and 2 to determine N w versus W the location and magnitude of peak value 62 of N w can be accurately determined and, thereby, controlled.
  • the dopant implant dose, also referred to as the partial implant dose PID, of each test volume can be determined from the following equation 3:
  • N sub residual dopant concentration in the semiconducting material forming semiconductor wafer 8
  • PID dopant implant dose
  • the determination of dopant implant dose can be compared to a theoretical dopant implant dose for test volume 44 to determine if the ion implant of dopants in semiconductor wafer 8 is occurring within an acceptable tolerance.
  • C m j n for a test volume 44 is determined by applying a CV type stimulus to conductive tip 24. This CV type stimulus includes superimposing an AC signal on a DC signal which is swept from a first, starting voltage 70 to a second, ending voltage 72.
  • the sweep of the DC voltage to ending voltage 72 occurs in a manner whereupon test volume 44 is driven into deep depletion 74.
  • the means for applying electrical stimulus 32 causes the DC voltage to dwell at ending voltage 72. Since test volume 44 has been driven into deep depletion 74, the measured capacitance increases even though the means for applying electrical stimulus 32 maintains ending voltage 72 applied to conductive tip 24.
  • the capacitance of test volume 44 continues increasing until it reaches a steady state value 76. This steady state value 76 occurs when test volume 44 is depleted of majority carriers and the net recombination of majority carriers and minority carriers in or adjacent test volume 44 is at equilibrium. Thereafter, the means for applying electrical stimulus 32 performs a reverse voltage sweep from ending voltage 72 toward starting voltage 70.
  • measurement means 34 monitors the capacitance of test volume 44 and determines when the capacitance of the reverse voltage sweep initially equals the capacitance of the forward voltage sweep. This capacitance is designated as Cmm and the voltage corresponding to C mm is designated as the threshold voltage V T .
  • the value of V T can be determined empirically from the CV type stimulus or it can be determined in a manner known in the art from values determined for C m ⁇ n and N sur f, discussed hereafter.
  • the maximum space charge distance (W M ) from top surface 6 at Cmm can be determined.
  • T ox thickness of dielectric layer 4
  • W M maximum space charge distance from top surface 6 at C ra ;
  • A contact area of conductive tip 24.
  • N surf average doping concentration
  • the value of N surf determined for a reference semiconductor wafer can be compared to the value of N surf for each of one or more product semiconductor wafers under test to determine if the difference in values exceeds a predetermined difference indicative of the ion implant process varying outside of the acceptable tolerance.
  • conductive tip 24 of probe 20 can contact dielectric layer 4 overlaying semiconductor wafer 8 in a scribe line 42 thereof.
  • the portion of semiconductor wafer 8 below the contact of conductive tip 24 and dielectric layer 4 does not include an ion implant.
  • the combination of conductive tip 24, dielectric layer 4 and semiconductor wafer 8 forms a MOS test structure to which the means for applying electrical stimulus 32 can apply one or more of a suitable CV type, current-voltage (IV) type, conductance-voltage (GV) and/or capacitance-time (Ct) or lifetime measurement type electrical stimulus.
  • Measurement means 34 can then measure the response of the MOS test structure to the stimulus and determine therefrom one or more properties of dielectric layer 4, semiconductor wafer 8, and/or the interface therebetween in a manner known in the art.
  • the measured response can be utilized to determine a value for the residual dopant concentration (N SUb ) in the semiconducting material forming semiconductor wafer 8.
  • Conductive tip 24 of probe 20 can also contact a dielectric layer overlaying the bulk semiconducting material or an ion implanted test volume 44 of an unpatterned semiconductor wafer, i.e., a semiconductor wafer having no integrated circuits 40 or scribe lines 42 formed thereon, to form a MOS test structure to which CV type, IV type, GV type or Ct type electrical stimulus can be applied.
  • the response of this MOS test structure to the stimulus can be measured and one or more properties of the dielectric layer, the semiconductor wafer, and/or the interface therebetween can be determined from the measured response in a manner known in the art.
  • a scribe line 42 of semiconductor wafer 8 has no overlaying dielectric layer 4
  • conductive tip 24 of probe 20 can contact the semiconducting material in this scribe line 42 thereby forming a Schottky test structure.
  • the portion of semiconductor wafer 8 forming this Schottky test structure can either be the bulk semiconducting material forming semiconductor wafer 8 or can be a test volume 44 ion implanted with a suitable dopant.
  • Means for applying electrical stimulus 32 can apply a suitable electrical stimulus, e.g., a CV type electrical stimulus, to this Schottky test structure and measurement means 34 can measure the response of the Schottky test structure to the stimulus and determine therefrom one or more properties of semiconductor wafer 8 in a manner known in the art.
  • conductive tip 24 of probe 20 can also contact the bulk semiconducting material or an ion implanted test volume 44 of an unpatterned semiconductor wafer, i.e., a semiconductor wafer having no dielectric layer 4, integrated circuits 40 or scribe lines 42 formed thereon, to form a Schottky test structure to which a suitable electrical stimulus, e.g., a CV type electrical stimulus, can be applied.
  • the response of this Schottky test structure to the stimulus can be measured and one or more properties of semiconductor wafer 8 can be determined from the measured response in a manner known in the art.
  • the present invention provides a method for determining dopant concentration and dopant dose in scribe lines of a product semiconductor wafer.
  • the present invention also provides a method for determining whether an ion implant process for a product semiconductor wafer is varying outside of an acceptable tolerance.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

La présente invention concerne un produit de plaquette (8) en semi-conducteur pourvu de circuits intégrés (40) séparés par des lignes de découpe (42). Une sonde (20) dotée d'une extrémité électroconductrice et élastiquement déformable est mise en contact avec une des lignes de découpe (42), constituant ainsi une structure d'essai. Un stimulus électrique (32) adéquat est appliqué à la structure d'essai et une réponse de la structure d'essai au stimulus électrique est mesurée. Au moins une propriété du produit de plaquette (8) en semi-conducteur est déterminée en fonction de la réponse mesurée.
PCT/US2002/008418 2001-03-23 2002-03-19 Procede permettant de detecter la dose de porteurs dans une plaquette en semi-conducteur WO2002077654A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US10/472,342 US20040108869A1 (en) 2002-03-19 2002-03-19 Method of detecting carrier dose of a semiconductor wafer
JP2002575653A JP2004526319A (ja) 2001-03-23 2002-03-19 半導体ウェハにおけるキャリアドーズ量の検出方法
EP02721475A EP1377842A4 (fr) 2001-03-23 2002-03-19 Procede permettant de detecter la dose de porteurs dans une plaquette en semi-conducteur

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US27854801P 2001-03-23 2001-03-23
US60/278,548 2001-03-23

Publications (1)

Publication Number Publication Date
WO2002077654A1 true WO2002077654A1 (fr) 2002-10-03

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EP (1) EP1377842A4 (fr)
JP (1) JP2004526319A (fr)
WO (1) WO2002077654A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1413892A2 (fr) * 2002-10-22 2004-04-28 Solid State Measurements, Inc. Procédé et appareil de mesure de la durée de vie de porteurs de charge dans une galette sémiconductrice
EP1450171A2 (fr) * 2003-02-10 2004-08-25 Solid State Measurements, Inc. Dispositif et méthode d'inspection de plaquettes
US6879176B1 (en) * 2003-11-04 2005-04-12 Solid State Measurements, Inc. Conductance-voltage (GV) based method for determining leakage current in dielectrics
EP1710594A1 (fr) * 2005-04-05 2006-10-11 Solid State Measurements, Inc. Procédé de mesure de wafers à semi-conducteurs à l'aide d'une sonde améliorée à l'oxyde

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US3849872A (en) * 1972-10-24 1974-11-26 Ibm Contacting integrated circuit chip terminal through the wafer kerf
US4103228A (en) * 1977-05-16 1978-07-25 Rca Corp. Method for determining whether holes in dielectric layers are opened
US4282483A (en) * 1979-05-15 1981-08-04 Tencor Instruments Probe for determining p or n-type conductivity of semiconductor material
US5767691A (en) * 1993-12-22 1998-06-16 International Business Machines Corporation Probe-oxide-semiconductor method and apparatus for measuring oxide charge on a semiconductor wafer

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US5047711A (en) * 1989-08-23 1991-09-10 Silicon Connections Corporation Wafer-level burn-in testing of integrated circuits
US5023561A (en) * 1990-05-04 1991-06-11 Solid State Measurements, Inc. Apparatus and method for non-invasive measurement of electrical properties of a dielectric layer in a semiconductor wafer

Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
US3849872A (en) * 1972-10-24 1974-11-26 Ibm Contacting integrated circuit chip terminal through the wafer kerf
US4103228A (en) * 1977-05-16 1978-07-25 Rca Corp. Method for determining whether holes in dielectric layers are opened
US4282483A (en) * 1979-05-15 1981-08-04 Tencor Instruments Probe for determining p or n-type conductivity of semiconductor material
US5767691A (en) * 1993-12-22 1998-06-16 International Business Machines Corporation Probe-oxide-semiconductor method and apparatus for measuring oxide charge on a semiconductor wafer

Non-Patent Citations (1)

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Title
See also references of EP1377842A4 *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1413892A2 (fr) * 2002-10-22 2004-04-28 Solid State Measurements, Inc. Procédé et appareil de mesure de la durée de vie de porteurs de charge dans une galette sémiconductrice
JP2004146831A (ja) * 2002-10-22 2004-05-20 Solid State Measurements Inc 半導体ウェハの荷電キャリア寿命測定方法及び測定装置
EP1413892A3 (fr) * 2002-10-22 2005-01-12 Solid State Measurements, Inc. Procédé et appareil de mesure de la durée de vie de porteurs de charge dans une galette sémiconductrice
EP1450171A2 (fr) * 2003-02-10 2004-08-25 Solid State Measurements, Inc. Dispositif et méthode d'inspection de plaquettes
EP1450171A3 (fr) * 2003-02-10 2005-09-21 Solid State Measurements, Inc. Dispositif et méthode d'inspection de plaquettes
US6879176B1 (en) * 2003-11-04 2005-04-12 Solid State Measurements, Inc. Conductance-voltage (GV) based method for determining leakage current in dielectrics
EP1710594A1 (fr) * 2005-04-05 2006-10-11 Solid State Measurements, Inc. Procédé de mesure de wafers à semi-conducteurs à l'aide d'une sonde améliorée à l'oxyde

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Publication number Publication date
EP1377842A4 (fr) 2005-08-17
JP2004526319A (ja) 2004-08-26
EP1377842A1 (fr) 2004-01-07

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