WO2002076135A1

WO2002076135A1 - Cell search method, circuit therefor and mobile station in w-cdma communication system

Info

Publication number: WO2002076135A1
Application number: PCT/JP2001/002092
Authority: WO
Inventors: Changming Zhou
Original assignee: Yozan Inc.
Priority date: 2001-03-16
Filing date: 2001-03-16
Publication date: 2002-09-26

Abstract

A cell search method and a circuit therefor in CDMA cellular mobile communication system. A mobile station has a base station database (204) in which geographical information about the cells of a base station is stored, and a mobile station position measuring/receiving unit (209) for measuring the position of the mobile station on the basis of GPS signals, and identifies from the position of the mobile station the base station and the associated scramble code. At the same time, a matched filter (301) detects the slot synchronization of a received signal from the spread code of a first synchronized (searched) channel.

Description

Specification

Cell search method and circuit for W-C DMA communication system and mobile station

The present invention relates to a W-C DMA cellular mobile communication system, and more particularly, to speeding up cell search in a mobile station capable of detecting its current position. Background art

In recent years, the wideband Castle Code Division Multiplexing (W-CDMA) communication system, which has attracted attention in the field of mobile communications, uses arithmetic processing for initial synchronization and base station identification in initial cell search. It takes a lot of time for initial cell search. Therefore, the first synchronization (search) channel common to all base stations is used to identify the beginning of the slot at which the spreading code is received. In addition, a three-stage cell search method has been proposed in which scramble codes for specifying base stations are divided into groups, a second synchronization (search) channel for specifying groups is provided, and the initial cell search is speeded up.

The three-stage cell search method consists of three stages: (1) slot synchronization, (2) frame synchronization and scramble code identification, and (3) scramble code identification.

For details of the three-stage cell search method, see “Analysis of Cell Search Characteristics in W—CDMA Cellular System”, Transactions of the Institute of Electronics, Information and Communication Engineers, Vol. J83-B, No9, ppl24. It is described in the first half of 5-1 2 5 7. However, the three-stage cell search method requires a large amount of processing for cell search and consumes a large amount of power.

Accordingly, the present invention has been devised to solve such a conventional problem. A cell search process capable of speeding up a cell search process and reducing the power consumption of a mobile station by utilizing the position information of the mobile station. Method, cell search circuit and And mobile stations. Disclosure of the invention

The mobile station detects the current position of its own station. It also has a position detection and reception means for receiving. It also has a base station database that stores base station information such as the service setting area (cell) of each base station. The current position of the own station is compared with the base station database to identify the cell (base station) where the own station is located.

In addition, a scramble code corresponding to the specified cell (base station) is generated, and after the slot synchronization, a correlation operation is performed between the code of the same scramble code having a different phase and a common pilot channel (CPICH). Then, the correlation output is integrated over a certain period of time, the signal power of the correlation output is calculated, and the phase having the maximum correlation signal power is defined as the frame timing. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a flowchart showing the cell search method of the present invention. FIG. 2 is a block diagram showing a mobile station according to the present invention.

FIG. 3 is a block diagram showing the cell search circuit in FIG. FIG. 4 is a block diagram showing the matched filter in FIG. FIG. 5 is a block diagram showing the sliding correlator unit in FIG.

FIG. 6 is a block diagram showing one sliding correlator in FIG.

FIG. 7 is a block diagram showing another embodiment of the cell search circuit in FIG.

FIG. 8 is a flowchart showing a conventional three-stage cell search method. FIG. 9 is a conceptual diagram showing a transmission signal frame configuration in a conventional three-stage cell search method. BEST MODE FOR CARRYING OUT THE INVENTION

The present invention will be described in more detail with reference to the accompanying drawings.

FIG. 8 is a flowchart showing a conventional three-stage cell search method, which comprises the following three-stage processing.

Phase 1 (receives the first sync channel)

The matched filter despreads the signal of the first synchronization channel (P-SCH: PrimarySyn ccnroniZa tio nCh a nne el), and searches for a peak with the maximum time average of the correlation value. As shown in FIG. 9, a P-SCH signal is transmitted from the base station in units of, for example, one slot (10 symbols), and establishes synchronization with this slot, that is, a P-SCH reception position. The timing of all channels transmitted from one base station is synchronized with the timing of P-SCH. The P-SCH reception position obtained here corresponds to the slot timing of all channels transmitted from the base station transmitting the received P-SCH.

Second stage (S—SCH or S—SCH and P—SCI-I simultaneous reception)

Based on the slot synchronization in the first stage, the sliding correlator detects the frame timing of the channel transmitted by the base station. With this, the scramble code group is specified, and the number of scramble codes is narrowed down to a predetermined number (for example, 8 types).

When narrowing down, for each slot timing, a plurality of spreading codes indicating a scramble code group are sequentially applied to detect correlation with a second synchronization channel:> —CH (secondary synchronization channel). . At this time, a scramble code group is specified by a combination of a plurality of spreading codes that maximize the power sum of the correlation values, and the timing of this correlation is set to the frame synchronization timing. Third stage (Common pilot channel CPIC I-I received)

Based on the scrambling code group and frame timing obtained in the second step, the sliding correlator calculates the correlation with the common pilot channel CPICH to which the candidate scrambling codes are sequentially applied, and calculates the correlation power. Narrow down to the largest scramble code. Here, the common pilot channel CPICH is composed of a double code consisting of a scramble code and a channelization code. .

As described above, time averaging processing is required at each stage, and the detection accuracy is better as the averaging time is longer, but the processing time is longer. Therefore, the detection accuracy and the processing speed are in a trade-off relationship, and realization of high-speed and high-accuracy detection has been desired.

FIG. 1 is a flowchart showing a cell search method according to the present invention. Step S101: At the time of slot timing detection, a plurality (jmax) of slot timing candidates are detected and stored, and these candidates are sequentially applied to frame timing detection. The rank of the candidate applied to the frame timing is set to “;!”, And this is sequentially incremented. In step S101, the slot timing order j to be adopted is initialized to "1".

Step S102: The mobile station receives P-SCII (first synchronization channel), despreads it with a matched filter, detects slot timing candidates, and saves them (slot). Sync).

Step S103: Among the slot timing candidates in step S102, the j-th correlation power candidate is adopted for frame timing detection. Step S104: In parallel with steps S102 and S103, the mobile station detects the position of its own station based on a GPS (GlobalPositioininngSystem) signal or the like.

Step S105: The mobile station stores the geographical information of the cell of each base station (including the center position, radius, coverage, etc. of the cell) in a database (hereinafter referred to as "base station"). This is called the local office database. After step S104, the position of the own station is compared with the base station database.

Step S106: In steps S104 and S105, the mobile station specifies a base station to receive a signal (scramble code specification). As a result, the scramble code to be applied to the frame timing detection is specified.

Step S107: The mobile station uses the scrambling code specified in step S106, and at the slot timing selected in step S103, the common pilot channel CPICH or sliding pilot correlator. Performs a correlation operation with another control channel. As a result, frame timing is detected (frame synchronization). Step S108: In the mobile station, if the slot timing selected in step 107 and the scramble code correspond, frame synchronization succeeds, but if not, the mobile station loses. Lose. In step S108, it is determined whether or not the frame synchronization has succeeded. If the frame synchronization has succeeded, the process ends.

Step S109: In the mobile station, when the frame synchronization has failed, it is determined whether or not all slot timing candidates have been applied to frame timing detection.

Step S110: If the mobile station has already applied all slot timing candidates in step S109, the mobile station performs error processing such as displaying an error message, and ends the processing.

Step S111: The mobile station adds "1" to "j" if all slot timing candidates have not been applied in step S109, and then proceeds to step S103. Return to

As described above, the mobile station directly detects its own position using a GPS signal or the like, and immediately specifies the base station and the scramble code from the base station database. Is also significantly simpler and faster. Furthermore, in parallel with specifying the scramble code, W

As a result, slot timing candidates are extracted, thereby increasing the overall processing speed.

FIG. 2 is a block diagram showing a mobile station according to the present invention.

The mobile station includes a transmitting unit 201 for transmitting a signal to the base station, a receiving unit 202 for receiving a signal from the base station, an antenna 220, and a transmitting unit 201 and a receiving unit 2 A transmission / reception control section 203 for controlling the control section 02 is provided. The mobile station has a base station database 204 in which geographical information of cells of each base station is stored. The base station database 204 is a database update control section 205. Will be updated as appropriate.

The receiving section 202 receives the update data UD of the base station database 204, and transfers this update data UD to the database update control section 205 through the transmission / reception control section 203. The database update control unit 205 writes the update data UD to the base station database 204 to update the database. The database update control unit 205 is further provided with an external I / F 206 so that database update information UD can be obtained from a personal computer or other device.

That is, the database update control unit 205 can acquire the update data UD as a W-CDMA reception signal or as data supplied from another device. Providing a plurality of update data acquisition forms in this way increases the flexibility of updating the database.

The mobile station has a local station position detection / reception unit 209 connected to the GPS antenna 207, and detects the position of the mobile station based on the GPS (GlobalPositioinngSystem) signal GS. The own station position detection / receiver 209 is further provided with an external I / F 208, which is connected to an independent GPS receiver (not shown) via the external IZF 208. obtain.

That is, the local station position detection / reception unit 209 receives the GPS signal GS directly from the GPS antenna 207 to detect the position of the local station, or based on the position detection information GI of the independent GPS receiver. Detect your own location You. By providing a plurality of forms of position detection in this way, the degree of freedom in position detection is increased.

The base station database 204 stores scramble code information corresponding to each base station, and the cell (base station) identification unit 210 uses the base station database based on its own station position detection information GI. With reference to 204, the information SCI (scramble code number, etc.) of the scramble code of the corresponding base station is obtained. The cell (base station) identification unit 210 inputs the scramble code information SCI to the cell search unit 211 provided in the reception unit 202.

FIG. 3 is a block diagram showing details of the cell search unit 211.

The cell search section 211 is a matched filter 310 to which a received signal S in (complex component signal including an in-phase component and a quadrature component) of a W-CDMA baseband is input and a sliding correlator. And a scramble code generation unit 303 to which the information SCI of the scramble code is input from the cell (base station) identification unit 210.

The matched filter 301 detects the slot synchronization of the received signal by the spread code of the first synchronization (search) channel P-SCH. The output S01 of the matched filter 301 is input to the power calculation circuit 304, and the signal power of the correlation output of each chip (sample) is calculated. The output SQ 2 of the power calculation circuit 304 is input to the addition circuit 305, and the output S 03 of the addition circuit 305 is input to the memory 306. The output S04 of the memory 306 is fed back to the addition circuit 305, and is added to the output S02 of the power calculation circuit 304. That is, in the memory 303, the output S02 of the power calculation circuit 304 is cyclically integrated for each chip (sample) of each slot at the slot cycle and stored. The memory 306 generates a correlation signal power integrated value or an average value S05 thereof for a predetermined period, and inputs the integrated value to the slot timing detection unit 307.

The slot timing detection section 307 detects the time integration of the correlation signal power or the peak of the average value, and the timing of the peak is used to determine the slot. Detects lot synchronization. As a result, a plurality of candidates for the slot timing are extracted, and these candidate Tj are input to the sliding correlator section 302 in order from the one with the largest signal power average, and the frame timing is set. To detect.

Each slot timing may include a signal from a different base station, and may not correspond to the base station specified by the cell (base station) specifying unit 210. Therefore, the slot timing is specified based on the success or failure of the frame timing detection.

The scramble code generator 303 generates a scramble code based on the information of the scramble code input from the cell (base station) identifier 210. Assuming that one frame of the received signal is composed of 11 slots (FIG. 9), the scramble code generator generates scrambling records S sc1, S sc2, and S sc at each of the n slots. ..., output S scn. Ssc1, Ssc2, ..., Sscn indicate the first to n-th phase scramble codes. The sliding correlator section 302 has n sliding correlators corresponding to these phases, and performs a correlation operation using these sliding correlators.

The output S ssc1, S ssc2, ..., S sscn of each of the sliding correlators of the first to eleventh phases is an adder circuit 308, 308, ..., 308, respectively. n, and the outputs S 06 1 to S 06 η of the adders 308 1 to 300 η are input to the memories 310 to 309 η, respectively. Memory 309 :! 3 309 η output S 071 〜S 0 7 n is fed back to the adder circuit 3 08:! 3 308 n and added to the output S ssc 1 1S ssc 11 of each sliding collector . That is, the integrated values (integrated values) obtained by sequentially adding the outputs Sssc1 to Ssscn of the sliding correlators are stored in the memories 309 1 to 903 n. The output S s s c 1, of each of the sliding correlators in the first to n-th phases,

S ssc 2 and S sscn are complex component signals having an in-phase component and a quadrature component, respectively, and the adders 3 08 1, 3 0 2, ..., 3 0 8 n performs an addition operation for each of the in-phase component and the quadrature component. Similarly memory 3 09 :! 33091 are input for the in-phase component and the quadrature component, respectively.

The memories 309 1 to 309 η generate integral values or average values of the in-phase component and the quadrature component of the correlation signal for a predetermined period, and use this as a power operation circuit 3101, 3102,. .., 3 1 0 Enter in η. Each of the power calculation circuits 3101 to 310η inputs the integrated value or average value S081 to S0811 of the correlation value to the frame timing detection unit 311. The frame timing detection unit 311 calculates the peak value of the power of the integrated value or the average value of the correlation values, and detects the frame timing. If the frame timing detection succeeds, the frame timing is used. If the frame timing detection does not succeed, the other slot timings are sequentially applied and the frame timing detection is repeated.

The success or failure of the frame synchronization is fed back from the frame timing detection unit 311 to the slot timing detection unit 307.

As described above, since the scramble code is set directly from the position information, the processing load is light and the power consumption is small.

In addition, since the scrambling code setting and the slot timing candidate Yuzu are executed independently and in parallel, the processing speed is high.

FIG. 4 is a block diagram showing a matched filter 31. The matched filter MF executes “fast correlation of a hierarchical correlation sequence (Fastcorre 1 ationoihierarchical corre 1 ationsequence)”. Filters MF1 and MF2 are connected in series. The matched filter MF 1 has m multipliers M 11 to M 1 m and a delay circuit D 11 1 to D 1, m which sequentially delays the input signal S in and inputs the delayed signal to the multipliers M 12 to M 1 ni. -1 and an adder ADD1 for summing the outputs of the multipliers M11 to M1m.

On the other hand, the matched filter MF 2 has m multipliers M 21 to M 2 m, The output of the matched filter MF 1 is sequentially delayed, and the sum of the outputs of the delay circuits D 21 to D 2, m−1 that are input to the multiplication circuits M 22 to M 2 m and the outputs of the multiplication circuits M 21 to M 2 m And an adder circuit AD D 2.

Since the matched filter circuit performs a high-speed product-sum operation on large-capacity data, the circuit scale is generally large and a large amount of power is consumed. This is a fatal problem for mobile communication terminals. To solve this problem, T Doc S M G 2 UMT S L 1 4 2 7/98: E T S I S T C was held in Stockholm, Sweden, from October 14 to 16, 1998.

At the meeting of SMG2 UMT SL ayer 1 Expert Group, Siemens announced `` AN ewcorre 1 ationsequence for the Primary Synchronisation Code with goodcorrelatio npropertiesandlowde ctorcomp 1 exity J (Fastcorrelationofhlera rchicalcorrelationsequence) ”. This suggests the possibility of downsizing the matched filter circuit.

For example, a sequence X, with a period m, and a sequence X ₂ with a period m are set, and X! The X ₂ is one period changes for one value of, generating a by connexion spreading code to both the product X i XX _2. At this time, the correlation operation is expressed as in Equation (1), and Equation (1) can be replaced with the product of two correlation operations as shown in Equations (2) and (3). In Equations (1) to (3), S psc (t) is the correlation output at time t, S in (i + t) is the input signal up to time t expressed as a discrete signal, and P s (t ') Is the partial correlation at time t '. Note although the period m of X ,, X ₂ and same or may be different period. div m) Equation (1)

χ ( ^ζχ " ^{ι + ί} ) formula (2)

Ps (t ') = ^ X ₂ (j) xSin (j + t') Equation (3)

ο

.., Pm in FIG. 4 correspond to the sequence X1, and C1, C2,..., Cm correspond to the sequence X2.

In the present embodiment, the hierarchical configuration has been described as an example. However, a matched filter having any other configuration can be used.

FIG. 5 is a block diagram showing sliding correlator section 302, in which n sliding correlators SC:! To SCn are connected in parallel with respect to received signal Sin. . In each of the sliding correlators SC1 to SCn, the scramble codes SSC (t), SSC (t + Δt)..., SSC (t + A correlation operation between (n-1) Δt) and the received signal S in is performed. Scramble code S S C (t), S S C ('t + t),

S S C (t + (n — 1) Δ t) is obtained by sequentially giving the same scramble code a phase difference of Δ t.

Note that, when the base station uses a spreading code (channelization code) different from the scrambling code at the same time, the scrambling code generated by the generating circuit 303 has a phase 1 It is necessary to combine the spread code with the spreading code for each phase _n and set the result in the sliding correlator section 302. Figure 6 shows one sliding correlator SC1 as a representative. The received signal is composed of an in-phase component (I component: described as S in I.) and a quadrature component (Q component: described as S in Q.). The sliding correlator SC1 performs each of these components. Perform correlation calculation.

The sliding correlator SC 1 has a multiplication circuit MI 1 and a multiplication circuit MI 2 for the I component (S i 11 I) of the input signal. The multiplication with the I component SCI is sequentially performed, and the multiplication circuit MI 2 sequentially performs the multiplication of the time-series received signal S in I and the Q component SCQ of the scramble code.

Further, the sliding correlator SC 1 has a multiplication circuit MQ 1 and a multiplication circuit MQ 2 for the Q component (S in Q) of the input signal, and the multiplication circuit MQ 1 scrambles the time-series received signal S in Q Multiplication with the Q component SCQ of the code is sequentially performed, and the multiplication circuit MQ2 sequentially performs multiplication of the time-series received signal S in Q and the I component SCI of the scramble code. The output of the multiplication circuit M I1 and the output of the multiplication circuit M Q1 are added by an addition circuit A DDI to calculate a correlation operation result S s s c c I The outputs of the multiplication circuit M Q2 and the multiplication circuit M I2 are subtracted by a subtraction circuit ADDQ to calculate a correlation operation result S s s c 1 Q.

In the case where the transmitting side of the base station uses a spreading code composed of a scrambling code and a channelization code, the scrambling code generation unit 303 of FIG. 6 includes the channelization code. The generation circuit is also included. The spreading code applied to the sliding correlator SC1 is obtained by calculating an exclusive OR of the scramble code and the channelization code for each bit.

In FIG. 5, the same effect can be obtained by providing a force S indicating the configuration of n sliding correlators and a configuration in which n or less sliding correlators are provided and the correlation operation is performed serially. it can.

FIG. 7 is a block diagram showing another embodiment of the cell search circuit in FIG. In the embodiment of FIG. 3, the sliding correlator section 302 The outputs S ssc1 to S sscn are integrated for each of the in-phase component and the quadrature component, and finally, the signal power is calculated by the power calculation circuits 3101 to 310n. The output power of the correlator section 302 is calculated and then integrated.

Power operation circuits 3101 to 310η are connected to the sliding correlator section 302, and signal powers S091 to S09n of outputs Ssscl to Ssscn are calculated, respectively. These signal powers are input to the adders 308 1 to 308 n, respectively, and their outputs S 101 to S 101 n are input to the memories 309 to 309 n, respectively. The outputs of the memories 309 1 to 309 n are input to the frame timing detection unit 331 and are fed-packed to the adders 308 1 to 308 n. Memory 309 1 to 309 n has a power operation circuit 310 :! The integrated value obtained by sequentially adding the power outputs of up to 310 η is stored.

According to this embodiment, the same effect as that of the embodiment of FIG. 3 can be obtained. Industrial applicability

Using the position information of the mobile station, it is possible to speed up the cell search process and reduce the power consumption of the mobile station.

Claims

The scope of the claims

1. In a CDMA cellular mobile communication system, a mobile station has a base station database storing base station information such as its location detection / reception means and the service setting area of the base station. By comparing the location information with the base station database, the cell (base station) where the own station is located is identified, the scrambling code corresponding to the cell (base station) is identified,

At the same time, a slot timing candidate is detected by detecting the correlation with the first synchronization channel using a matched filter,

Further, the cell timing is detected by performing a correlation operation with a common pilot channel having a different phase of the above-mentioned scramble record for each slot in one frame. Search method.

2. When frame timing detection using one slot timing candidate is unsuccessful, the other candidates are applied sequentially, and frame timing detection is repeated until frame timing detection is successful. The cell search method according to claim 1, which is characterized in that:

3. The cell search method according to claim 2, wherein the slot timing is applied to the frame timing detection in ascending order of the correlation filter power of the matched filter.

4. A mobile station is provided with a position detection circuit capable of detecting the current position of the mobile station, and a base station database storing base station information such as a service setting area of each base station is provided.

A cell identification circuit that compares the current position of the own station with the base station database is provided.

A slot synchronization circuit for detecting slot timing candidates including a matched filter circuit for detecting a correlation with the first synchronization channel;

Furthermore, corresponding to each slot in one frame, And a scramble code generation circuit that generates codes of different phases of the scramble code corresponding to the cell (base station) where the own station is located, and the correlation between these scramble codes and the common pilot channel. A cell search circuit comprising: a frame synchronization circuit that detects and determines a phase having a maximum correlation signal power and detects a frame timing.

5. The mobile station downloads the base station database containing the latest base station information via the currently available wireless communication system or wired communication system, and updates the current base station database. 5. The cell search circuit according to claim 4, wherein the cell search circuit is new.

6. The cell search circuit according to claim 4, wherein the mobile station includes position receiving means for receiving the current position of the own station by wire or wireless communication from outside.

7. The cell search circuit according to claim 4, wherein the mobile station includes position detecting means for detecting a current position of the mobile station based on a GPS signal received by a GPS antenna.

8. A cell specifying unit that specifies a scrambling code of a base station with which the mobile station communicates based on information of a cell including the mobile station,

A slot timing detection unit that extracts a plurality of slot timing candidates from a correlation operation result between the received signal and the spreading code of the first synchronization channel;

A frame timing is detected based on a correlation operation result between the received signal at the timing of the slot timing candidate and the scramble code, and when the frame timing is unsuccessful, another slot timing candidate is sequentially applied. And a frame timing detector for identifying one slot timing,

Mobile station with.

9. Position detection of own station by receiving GPS (Global Positioning System) signal to identify the position of own station. A base station database holding information on scrambling codes of base stations corresponding to cells including the position of the own station;

Further comprising

9. The mobile station according to claim 8, wherein the cell specifying unit specifies a scramble code by referring to the base station database based on information on the position detected by the local station position detecting / receiving unit. Bureau.

10. The mobile station according to claim 8, wherein the correlation operation between the received signal and the spread code of the first synchronization channel is performed by a matched filter.

11. A scramble code generation circuit that generates the scramble code specified by the cell specification unit at a timing synchronized with each slot in the frame,

A sliding correlator unit having a number of sliding correlators corresponding to the number of slots corresponding to these scrambling codes, and a corresponding scrambling code applied to each sliding correlator;

Further comprising

9. The mobile station according to claim 8, wherein the frame timing detection unit performs frame timing detection based on an output of the sliding correlator unit.

12. The mobile station according to claim 8, wherein the frame timing detection section outputs a signal indicating success or failure of the frame timing detection to the slot timing detection section.

13. A circuit for calculating the time integral of the power of the correlation operation result between the received signal and the spread code of the first synchronization channel is further provided, and the slot timing detecting section detects the slot timing based on the time integral of the power. 9. The mobile station according to claim 8, wherein candidates are extracted.

14. Calculate the time integral of the power of the correlation operation result between the received signal and the scramble code at the timing of the slot timing candidate 9. The mobile station according to claim 8, wherein a circuit for performing the operation is provided, and the frame timing detection unit detects the frame timing based on a time integration of power.