WO2002075340A3 - Dispositif de maintien d'un circuit electronique dans un etat predetermine - Google Patents

Dispositif de maintien d'un circuit electronique dans un etat predetermine Download PDF

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Publication number
WO2002075340A3
WO2002075340A3 PCT/FR2002/000962 FR0200962W WO02075340A3 WO 2002075340 A3 WO2002075340 A3 WO 2002075340A3 FR 0200962 W FR0200962 W FR 0200962W WO 02075340 A3 WO02075340 A3 WO 02075340A3
Authority
WO
WIPO (PCT)
Prior art keywords
electronic circuit
determined state
energising
holding
input terminal
Prior art date
Application number
PCT/FR2002/000962
Other languages
English (en)
Other versions
WO2002075340A2 (fr
Inventor
Philippe Perdu
Romain Desplats
Original Assignee
Centre Nat Etd Spatiales
Philippe Perdu
Romain Desplats
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Centre Nat Etd Spatiales, Philippe Perdu, Romain Desplats filed Critical Centre Nat Etd Spatiales
Priority to DE60236432T priority Critical patent/DE60236432D1/de
Priority to AT02722351T priority patent/ATE468540T1/de
Priority to EP02722351A priority patent/EP1393088B1/fr
Publication of WO2002075340A2 publication Critical patent/WO2002075340A2/fr
Publication of WO2002075340A3 publication Critical patent/WO2002075340A3/fr

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2836—Fault-finding or characterising
    • G01R31/2844—Fault-finding or characterising using test interfaces, e.g. adapters, test boxes, switches, PIN drivers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31905—Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture

Abstract

L'invention concerne un dispositif (16) électronique de maintien d'un circuit électronique (10) dans un état prédéterminé, le circuit (10) ayant été préala-blement amené dans ledit état prédéterminé par une source d'excitation extérieure (14) propre ô appliquer des signaux d'entrée à chaque borne d'entrée (12) dudit circuit électronique (10). Il comporte :- des moyens (30) de recueil du signal d'entrée appliqué, par ladite source d'excitation extérieure (14), ô chaque borne d'entrée (12) du circuit électronique dans ledit état prédéterminé ;- des moyens autonomes (34, 38, 40) d'excitation permanente du circuit électronique (10) adaptés pour le maintien, après suppression de ladite source d'excitation extérieure (14), à chaque borne d'entrée (12) du circuit électronique, du signal d'entrée recueilli ; et- des moyens (28) de pilotage des moyens autonomes (34, 38, 40) d'excitation permanente en fonction des signaux d'entrée recueillis.
PCT/FR2002/000962 2001-03-21 2002-03-19 Dispositif de maintien d'un circuit electronique dans un etat predetermine WO2002075340A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE60236432T DE60236432D1 (de) 2001-03-21 2002-03-19 Vorrichtung zur erhaltung einer elektronischen schaltung in einem vorgegebenen zustand
AT02722351T ATE468540T1 (de) 2001-03-21 2002-03-19 Vorrichtung zur erhaltung einer elektronischen schaltung in einem vorgegebenen zustand
EP02722351A EP1393088B1 (fr) 2001-03-21 2002-03-19 Dispositif de maintien d'un circuit electronique dans un etat predetermine

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR01/03845 2001-03-21
FR0103845A FR2822546B1 (fr) 2001-03-21 2001-03-21 Dispositif de maintien d'un circuit electronique dans un etat predetermine

Publications (2)

Publication Number Publication Date
WO2002075340A2 WO2002075340A2 (fr) 2002-09-26
WO2002075340A3 true WO2002075340A3 (fr) 2003-01-03

Family

ID=8861406

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR2002/000962 WO2002075340A2 (fr) 2001-03-21 2002-03-19 Dispositif de maintien d'un circuit electronique dans un etat predetermine

Country Status (5)

Country Link
EP (1) EP1393088B1 (fr)
AT (1) ATE468540T1 (fr)
DE (1) DE60236432D1 (fr)
FR (1) FR2822546B1 (fr)
WO (1) WO2002075340A2 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4300207A (en) * 1979-09-25 1981-11-10 Grumman Aerospace Corporation Multiple matrix switching system
US4354268A (en) * 1980-04-03 1982-10-12 Santek, Inc. Intelligent test head for automatic test system
US5146161A (en) * 1991-04-05 1992-09-08 Vlsi Technology, Inc. Integrated circuit test system
US5898703A (en) * 1997-06-05 1999-04-27 Mitsubishi Denki Kabushiki Kaisha Device and method for testing integrated circuit including bi-directional test pin for receiving control data and outputting observation data

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5461649A (en) * 1994-05-09 1995-10-24 Apple Computer Inc. Method and apparatus for maintaining a state of a state machine during unstable clock conditions without clock delay

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4300207A (en) * 1979-09-25 1981-11-10 Grumman Aerospace Corporation Multiple matrix switching system
US4354268A (en) * 1980-04-03 1982-10-12 Santek, Inc. Intelligent test head for automatic test system
US5146161A (en) * 1991-04-05 1992-09-08 Vlsi Technology, Inc. Integrated circuit test system
US5898703A (en) * 1997-06-05 1999-04-27 Mitsubishi Denki Kabushiki Kaisha Device and method for testing integrated circuit including bi-directional test pin for receiving control data and outputting observation data

Also Published As

Publication number Publication date
FR2822546B1 (fr) 2003-06-27
FR2822546A1 (fr) 2002-09-27
DE60236432D1 (de) 2010-07-01
WO2002075340A2 (fr) 2002-09-26
EP1393088A2 (fr) 2004-03-03
ATE468540T1 (de) 2010-06-15
EP1393088B1 (fr) 2010-05-19

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