WO2002074025A2 - Multilayer printed circuit board - Google Patents

Multilayer printed circuit board Download PDF

Info

Publication number
WO2002074025A2
WO2002074025A2 PCT/DE2002/000754 DE0200754W WO02074025A2 WO 2002074025 A2 WO2002074025 A2 WO 2002074025A2 DE 0200754 W DE0200754 W DE 0200754W WO 02074025 A2 WO02074025 A2 WO 02074025A2
Authority
WO
WIPO (PCT)
Prior art keywords
circuit board
printed circuit
edge region
ohmic resistance
recesses
Prior art date
Application number
PCT/DE2002/000754
Other languages
German (de)
French (fr)
Other versions
WO2002074025A3 (en
Inventor
Christian Dirks
Original Assignee
Ilfa Industrieelektronik Und Leiterplattenfertigung Aller Art Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ilfa Industrieelektronik Und Leiterplattenfertigung Aller Art Gmbh filed Critical Ilfa Industrieelektronik Und Leiterplattenfertigung Aller Art Gmbh
Priority to DE10291003T priority Critical patent/DE10291003D2/en
Priority to AU2002308354A priority patent/AU2002308354A1/en
Publication of WO2002074025A2 publication Critical patent/WO2002074025A2/en
Publication of WO2002074025A3 publication Critical patent/WO2002074025A3/en

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0234Resistors or by disposing resistive or lossy substances in or near power planes
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/16Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/167Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed resistors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092Dispersed materials, e.g. conductive pastes or inks
    • H05K1/095Dispersed materials, e.g. conductive pastes or inks for polymer thick films, i.e. having a permanent organic polymeric binder
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/032Materials
    • H05K2201/0323Carbon
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/0929Conductive planes
    • H05K2201/093Layout of power planes, ground planes or power supply conductors, e.g. having special clearance holes therein
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/0969Apertured conductors

Definitions

  • the invention relates to a multilayer printed circuit board according to the preamble of claim 1.
  • Printed circuit boards which contain flat power supply systems. They consist of continuous metallic conductor surfaces, which can contain holes and smaller recesses, or of metallic conductor tracks. Copper is used as the material for the conductor surfaces or conductor tracks. At least one of these surfaces or tracks carries supply voltage, at least another one of these layers carries ground potential. In addition, ground areas are used in multilayer printed circuit boards which only serve as reference ground for conductor tracks, but do not directly lead to ground potential.
  • Interference power can spread on these surfaces or tracks and radiate into adjacent components or radiate into the environment. Although it is known to switch capacitors between connections for sources of interference power and reference potential, the interference power does not disappear as a result, but is merely reflected. So interference power cannot be destroyed by diverting it to ground. From EP 1 005 259 A2 it is known to divide at least one electrically conductive surface into a plurality of segments which are separated from one another by narrow gaps. The gaps are filled with an electrically conductive material, the specific ohmic resistance of which is considerably higher than that of the metallic material. The surface then has an average total resistance which is higher than the ohmic resistance of an equally large one-part surface made of the same metallic material. As a result, the current heat losses in the absorptive area are significantly higher than in a conventional copper area, as a result of which the propagation and / or radiation of high-frequency interference power is reduced.
  • the invention has for its object to improve a multilayer printed circuit board in such a way that the propagation and / or radiation of interference power without impairing the arrangement of active electronic components and is reduced without increasing the ripple of the conductor surface carrying supply potential.
  • the invention is based on the following consideration.
  • an electric field and a magnetic field essentially only exist between two conductor surfaces, and therefore an alternating electromagnetic field, taking into account the field expansion occurring at surface boundaries, can only radiate electromagnetic energy in the edge region of two conductor surfaces.
  • the edge regions of the conductor surfaces act more or less as an antenna which emits electromagnetic energy and / or as an open line, the electromagnetic Energy reflected.
  • the electromagnetic energy reaching the edges of the printed circuit board is gie absorbed significantly before it finally reaches the edge of the circuit board and the remaining portion is emitted and / or reflected.
  • the inner area of the conductor area which is separate from the edge area, forms an essentially continuous area, if one disregards the necessary bores for electrically connected or electrically insulated connections of the populated active and passive components. Similar to conventional printed circuit boards, there are no restrictions regarding the arrangement of the electronic components and the increase in the ripple of the supply potential.
  • the ohmic resistance preferably increases in relation to a unit area in the edge region toward the edge.
  • the entire edge region from the transition to the inner region to the outer edge acts as effective absorption distance.
  • the absorption effect is adapted as the impedances increasing towards the edge area.
  • a steady increase in the ohmic resistance also avoids impact points which lead to a reduction in the locally distributed absorption effect and thus to increased radiation or reflection of electromagnetic energy.
  • the edge area is fissured by gaps or recesses.
  • the gaps or recesses are filled with an electrically conductive material, the specific ohmic resistance of which is considerably higher than that of the metallic material.
  • the electrically conductive material filling the gaps or recesses is preferably carbon mass. As a result, the gaps or recesses are completely filled with resistance material, so that an overall electrically conductive surface is created again. Through the use of carbon mass, the resistance material gaps can adapt to any shape.
  • the electrically conductive material filling the gaps or recesses can be applied using thick film technology or alternatively by screen printing.
  • the surface with the higher average total ohmic resistance in the edge region of the printed circuit board is arranged between continuous conductor surfaces in relation to a surface unit.
  • the absorptive edge areas of the conductor surface can then largely absorb interference power that is introduced into this surface system by irregular current consumption by integrated circuits, as a result of which the radiation from the surface system is significantly reduced.
  • cross currents are drawn in the final stage of the integrated circuit when the potential of the output changes from a logic state to the their logical state changes.
  • the maximum of the cross current occurs when the edge of the change of state has its greatest steepness.
  • the duration of such a cross current spike can be between 1 and 100 ns.
  • the radiation of an electrical field due to potential differences in the conductor area at high current peaks is shielded in the middle area of the conductor area by the sandwich-like structure. In the edge areas, the increasing ohmic resistance ensures extensive absorption of the alternating electromagnetic field resulting from the magnetic field and the electrical field.
  • the insulating layers between the surface with the higher average total ohmic resistance in the edge region of the printed circuit board based on a surface unit and the continuous conductor surfaces are dimensioned such that the distance between the absorbent conductor surface and the respective continuous conductor surface is between 10 and 200 ⁇ m, preferably 50 ⁇ m is.
  • Attainable attenuation of the radiation is approximately in the range of 10 dB.
  • Fig. 2 is a view of an exposed planes of the circuit board in a first embodiment of the conductor surface
  • Fig. 3 is a view of the same level of the circuit board in a second embodiment of the conductor surface.
  • the printed circuit board 10 shown in FIG. 1 comprises, by way of example, three conductor surfaces 12, 22 and 24 made of copper, of which the middle conductor surface 12 leads to supply potential and the two adjacent conductor surfaces 22, 24 reference potential for supplying energy to integrated circuits.
  • the conductor surfaces 12, 22 and 24 are separated from one another by thin insulating layers 20.
  • insulating layers 26 which carry conductor tracks 28 for signal lines.
  • the two reference potential-conducting conductor surfaces 22, 24 extend over the entire surface to the edge of the circuit board 10, wherein only holes for contacting or insulated implementation of the connections of components are left out.
  • the middle conductor surface 12, which carries supply potential, is likewise designed over the entire area in the inner region 30, with the exception of the bores for contacting or insulated connection of components.
  • a peripheral edge region 14 is, however, designed differently, as the view of the conductor surface 12 in FIGS. 2 and 3 shows.
  • the conductor surface 12 forms gaps 16 which widen in a wedge shape towards the edge of the printed circuit board 10.
  • the edge region 14 of the conductor surface 12 is fissured by recesses 18.
  • the gaps 16 or recesses 18 are filled with carbon mass, an electrically conductive material, the specific ohmic resistance of which is significantly higher than that of the metallic material copper.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

The invention relates to a multilayer printed circuit board (10) comprising at least one conductive surface (12), which contains metallic material and which guides a supply potential or reference potential. The conductive surface (12) comprises, in the edge area (14) of the printed circuit board (10), an average ohmic total resistance with regard to a surface unit that is considerably higher than the ohmic resistance of the same surface (12) in a region (30) of the printed circuit board (10), said region being located further in, with regard to said surface unit.

Description

Mehrschichtige Leiterplatte Multi-layer circuit board

Die Erfindung betrifft eine mehrschichtige Leiterplatte nach dem Oberbegriff des Anspruchs 1.The invention relates to a multilayer printed circuit board according to the preamble of claim 1.

Es sind Leiterplatten bekannt, die flächige Stromversorgungssysteme enthalten. Sie bestehen aus durchgehenden metallischen Leiterflächen, die Löcher und kleinere Aussparungen enthalten können oder aus metallischen Leiterbahnen. Als Materialien für die Leiterflächen oder Leiterbahnen dient Kupfer. Wenigstens eine dieser Flächen oder Bahnen führt VersorgungsSpannung, wenigstens eine andere dieser Lagen führt Massepotential. Außerdem werden in mehrlagigen Leiterplatten Masseflächen verwendet, die lediglich als Bezugsmasse für Leiterbahnen dienen, aber nicht direkt Massepotential führen.Printed circuit boards are known which contain flat power supply systems. They consist of continuous metallic conductor surfaces, which can contain holes and smaller recesses, or of metallic conductor tracks. Copper is used as the material for the conductor surfaces or conductor tracks. At least one of these surfaces or tracks carries supply voltage, at least another one of these layers carries ground potential. In addition, ground areas are used in multilayer printed circuit boards which only serve as reference ground for conductor tracks, but do not directly lead to ground potential.

Störleistung kann sich auf diesen Flächen oder Bahnen ausbreiten und in angrenzende Bauelemente einstrahlen oder in die Umgebung abstrahlen. Es ist zwar bekannt, zwischen Anschlüssen für Quellen der Störleistung und Bezugspotential Kondensatoren zu schalten, die Störleistung verschwindet aber dadurch in keinem Fall, sondern wird lediglich reflektiert. Man kann Störleistung also nicht dadurch vernichten, dass man sie zur Masse ableitet. Aus der EP 1 005 259 A2 ist bekannt, wenigstens eine elektrisch leitende Fläche in eine Vielzahl Segmente zu unterteilen, die durch schmale Spalte voneinander getrennt sind. Die Spalte sind mit einem elektrisch leitenden Material gefüllt, dessen spezifischer ohmscher Widerstand wesentlich höher als der des metallischen Materials ist. Die Fläche weist dann einen mittleren Gesamtwiderstand auf, der höher ist als der ohmsche Widerstand einer gleich großen einteiligen Fläche aus demselben metallischen Material. Hierdurch werden die Stromwärmeverluste in der absorptiven Fläche wesentlich höher, als in einer konventionellen Kupferfläche, wodurch die Ausbreitung und/oder Abstrahlung von hochfrequenter Störleistung verringert wird.Interference power can spread on these surfaces or tracks and radiate into adjacent components or radiate into the environment. Although it is known to switch capacitors between connections for sources of interference power and reference potential, the interference power does not disappear as a result, but is merely reflected. So interference power cannot be destroyed by diverting it to ground. From EP 1 005 259 A2 it is known to divide at least one electrically conductive surface into a plurality of segments which are separated from one another by narrow gaps. The gaps are filled with an electrically conductive material, the specific ohmic resistance of which is considerably higher than that of the metallic material. The surface then has an average total resistance which is higher than the ohmic resistance of an equally large one-part surface made of the same metallic material. As a result, the current heat losses in the absorptive area are significantly higher than in a conventional copper area, as a result of which the propagation and / or radiation of high-frequency interference power is reduced.

Die bekannte Anordnung von Segmenten beeinträchtigt allerdings beim Entwurf elektronischer Schaltungen die schaltungs- technisch optimierte, Platz sparende Anordnung aktiver elektronischer Bauelemente, den die zur Energieversorgung dienenden Anschlüsse sollten möglichst auf ein Segment der Versorgungspotential führenden Leiterfläche treffen, und hierbei auch nicht in den Randbereich des Segments sondern möglichst in Zentrum. Außerdem besteht besonders bei hoher Stromaufnahme und steilen Schaltflanken die Gefahr, dass die Welligkeit der Versorgungspotential führenden Leiterfläche auf benachbarte elektronische Bauelemente überspricht .The known arrangement of segments, however, affects the circuit-optimized, space-saving arrangement of active electronic components in the design of electronic circuits, since the connections serving for energy supply should meet a segment of the supply potential-conducting surface as far as possible, and also not in the edge region of the segment but rather in the center. In addition, especially with high current consumption and steep switching edges, there is a risk that the ripple of the conductor surface carrying supply potential will cross over to neighboring electronic components.

Der Erfindung liegt die Aufgabe zugrunde, eine mehrschichtige Leiterplatte dahingehend zu verbessern, dass die Ausbreitung und/oder Abstrahlung von Störleistung ohne Beeinträchtigung der Anordnerbarkeit aktiver elektronischer Bauelemente und ohne Erhöhung der Welligkeit der Versorgungspotential führenden Leiterfläche verringert wird.The invention has for its object to improve a multilayer printed circuit board in such a way that the propagation and / or radiation of interference power without impairing the arrangement of active electronic components and is reduced without increasing the ripple of the conductor surface carrying supply potential.

Diese Aufgabe wird bei einer Leiterplatte mit den Merkmalen des Anspruchs 1 gelöst .This object is achieved in a printed circuit board with the features of claim 1.

Weiterbildungen und vorteilhafte Ausgestaltungen ergeben sich aus den Unteransprüchen und der weiteren Beschreibung.Further developments and advantageous refinements result from the subclaims and the further description.

Die Erfindung beruht auf folgender Überlegung. Bei mehrschichtigen Leiterplatten existieren ein elektrisches Feld und ein magnetisches Feld gemeinsam im wesentlichen nur zwischen zwei Leiterflächen und daher kann ein elektromagnetisches Wechselfeld unter Berücksichtigung der an Flächengrenzen auftretenden Feldaufweitung nur elektromagnetische Energie im Randbereich von zwei Leiterflächen abstrahlen.The invention is based on the following consideration. In the case of multilayer printed circuit boards, an electric field and a magnetic field essentially only exist between two conductor surfaces, and therefore an alternating electromagnetic field, taking into account the field expansion occurring at surface boundaries, can only radiate electromagnetic energy in the edge region of two conductor surfaces.

In Abhängigkeit von der durch die mechanischen Abmessungen der Leiterflächen und des dazwischen liegenden Dielektrikums gebildeten Leitungsresonanz in Bezug auf die Wellenlänge der erzeugten elektromagnetischen Energie wirken die Randbereiche der Leiterflächen mehr oder weniger als Antenne, die elektromagnetische Energie abstrahlt und/oder als offene Leitung, die elektromagnetische Energie reflektiert.Depending on the line resonance formed by the mechanical dimensions of the conductor surfaces and the dielectric in between, in relation to the wavelength of the electromagnetic energy generated, the edge regions of the conductor surfaces act more or less as an antenna which emits electromagnetic energy and / or as an open line, the electromagnetic Energy reflected.

Durch den im Randbereich der Leiterplatte wirksamen erheblich höheren mittleren ohmschen Gesamtwiderstand im Vergleich zu einem weiter innen liegenden Bereich der Leiterplatte, jeweils bezogen auf dieselbe Flächeneinheit, wird die zu den Rändern der Leiterplatte gelangende elektromagnetische Ener- gie wesentlich absorbiert, ehe sie schließlich an den Rand der Leiterplatte gelangt und der verbleibende Anteil abgestrahlt und/oder reflektiert wird.Due to the considerably higher average total ohmic resistance in the edge area of the printed circuit board compared to a further inner area of the printed circuit board, in each case based on the same area unit, the electromagnetic energy reaching the edges of the printed circuit board is gie absorbed significantly before it finally reaches the edge of the circuit board and the remaining portion is emitted and / or reflected.

Dagegen bildet der vom Randbereich gesonderte innen liegende Bereich der Leiterfläche eine im wesentlichen durchgehende Fläche, wenn man einmal von den notwendigen Bohrungen für e- lektrisch verbundene oder elektrisch isolierte Anschlüsse der bestückten aktiven und passiven Bauelemente absieht. Ähnlich konventioneller Leiterplatten sind hier keine Einschränkungen hinsichtlich der Anordnerbarkeit der elektronischen Bauelemente und der Erhöhung der Welligkeit des Versorgungspotentials vorhanden.In contrast, the inner area of the conductor area, which is separate from the edge area, forms an essentially continuous area, if one disregards the necessary bores for electrically connected or electrically insulated connections of the populated active and passive components. Similar to conventional printed circuit boards, there are no restrictions regarding the arrangement of the electronic components and the increase in the ripple of the supply potential.

Gegenüber Flächen mit unterbrochener, karbonisierter Struktur entstehen außerdem Vorteile dadurch, dass Gleichstromanteile in der Stromaufnahme der integrierten Schaltung nicht zu unzulässigen Spannungsabfällen führen. Außerdem kommt es bei der Erfindung nicht zu zusätzlichen Impedanzkopplungen bei Signalleitungen, die über unterbrochene Flächen mit Karbonabsorbern geführt werden.Compared to surfaces with an interrupted, carbonized structure, there are also advantages in that DC components in the current consumption of the integrated circuit do not lead to impermissible voltage drops. In addition, the invention does not result in additional impedance couplings for signal lines that are routed over interrupted areas with carbon absorbers.

Vorzugsweise steigt der ohmsche Widerstand bezogen auf eine Flächeneinheit im Randbereich zum Rand hin an.The ohmic resistance preferably increases in relation to a unit area in the edge region toward the edge.

Da die in den Leiterflächen fließenden hochfrequenten Querströme zum Rand der Leiterplatte hin zu höheren Impedanzen transformiert werden, wirkt so der gesamte Randbereich vom Übergang zu innen liegenden Bereich bis zum äußeren Rand als wirksame Absorptionsstrecke. Die Absorptionswirkung ist als der zu Randbereich steigenden Impedanzen angepasst.Since the high-frequency cross currents flowing in the conductor surfaces are transformed to higher impedances towards the edge of the circuit board, the entire edge region from the transition to the inner region to the outer edge acts as effective absorption distance. The absorption effect is adapted as the impedances increasing towards the edge area.

Durch einen stetigen Anstieg des ohmschen Widerstandes werden zudem Stoßstellen vermieden, die zu einer Verminderung der örtlich verteilten Absorptionswirkung führen und damit zu einer erhöhten Abstrahlung oder Reflexion elektromagnetischer Energie führen können.A steady increase in the ohmic resistance also avoids impact points which lead to a reduction in the locally distributed absorption effect and thus to increased radiation or reflection of electromagnetic energy.

Bei einer praktischen Ausgestaltung ist der Randbereich durch Spalte oder Aussparungen zerklüftet. Die Spalte oder Aussparungen sind mit einem elektrisch leitenden Material ausgefüllt, dessen spezifischer ohmscher Widerstand wesentlich höher als der des metallischen Materials ist.In a practical embodiment, the edge area is fissured by gaps or recesses. The gaps or recesses are filled with an electrically conductive material, the specific ohmic resistance of which is considerably higher than that of the metallic material.

Diese Ausgestaltung führt durch die Kombination von Materialien unterschiedlichen spezifischen ohmschen Widerstandes zu einer Fläche mit einem höheren resultierenden Widerstand als dem des metallischen Materials. Zwar ist der erhaltene Widerstand nicht homogen verteilt, die Inhomogenität ist aber im Bezug auf die Wellenlänge der hochfrequenten Störenergie vernachlässigbar. Dafür ist aber eine technisch einfache Realisierung mit bei Leiterplatten üblichen Fertigungsverfahren möglich und gewährleistet reproduzierbare elektrische Eigenschaften.This configuration leads through the combination of materials of different specific ohmic resistance to a surface with a higher resulting resistance than that of the metallic material. Although the resistance obtained is not distributed homogeneously, the inhomogeneity is negligible in relation to the wavelength of the high-frequency interference energy. For this purpose, however, a technically simple implementation is possible using the production processes customary for printed circuit boards and guarantees reproducible electrical properties.

Vorzugsweise ist das die Spalte oder Aussparungen ausfüllende elektrisch leitende Material Karbonmasse . Hierdurch werden die Spalte oder Aussparungen vollständig mit Widerstandsmaterial aufgefüllt, so dass wieder eine elektrisch leitende Gesamtfläche entsteht. Durch die Verwendung von Karbonmasse kann sich das Widerstandsmaterial Zwischenräumen einer beliebigen Form anpassen.The electrically conductive material filling the gaps or recesses is preferably carbon mass. As a result, the gaps or recesses are completely filled with resistance material, so that an overall electrically conductive surface is created again. Through the use of carbon mass, the resistance material gaps can adapt to any shape.

Das die Spalte oder Aussparungen ausfüllende elektrisch leitende Material kann in Dickfilmtechnik oder alternativ durch Siebdruck aufgebracht sein.The electrically conductive material filling the gaps or recesses can be applied using thick film technology or alternatively by screen printing.

Diese Techniken sind bei der Herstellung von Leiterplatten geläufig, wodurch auch bei der erfindungsgemäßen Realisierung optimale Ergebnisse sichergestellt werden.These techniques are common in the production of printed circuit boards, which also ensures optimal results in the implementation according to the invention.

Bei einem flächigen Energieversorgungssystem ist die Fläche mit dem im Randbereich der Leiterplatte höheren mittleren ohmschen Gesamtwiderstand bezogen auf eine Flächeneinheit zwischen durchgehenden Leiterflächen angeordnet.In the case of a flat energy supply system, the surface with the higher average total ohmic resistance in the edge region of the printed circuit board is arranged between continuous conductor surfaces in relation to a surface unit.

Die absorptiven Randbereiche der Leiterfläche können dann Störleistung, die durch unregelmäßige Stromaufnahme von integrierten Schaltungen in dieses Flächensystem eingebracht wird, weitgehend absorbieren, wodurch die Abstrahlung aus dem Flächensystem deutlich vermindert wird.The absorptive edge areas of the conductor surface can then largely absorb interference power that is introduced into this surface system by irregular current consumption by integrated circuits, as a result of which the radiation from the surface system is significantly reduced.

Diese Maßnahme ist besonders bei der Anwendung von CMOS- integrierten Schaltungen wirksam, bei denen Störleistung durch Querströme verursacht wird. Derartige Querströme werden in der Endstufe der integrierten Schaltung gezogen, wenn das Potential des Ausgangs von einem logischen Zustand in den an- deren logischen Zustand wechselt. Das Maximum des Querstroms tritt auf, wenn die Flanke des Zustandswechsels ihre größte Steilheit aufweist. Die Dauer eines solchen Querstrom-Piks kann zwischen 1 und 100 ns liegen.This measure is particularly effective when using CMOS integrated circuits in which interference power is caused by cross currents. Such cross currents are drawn in the final stage of the integrated circuit when the potential of the output changes from a logic state to the their logical state changes. The maximum of the cross current occurs when the edge of the change of state has its greatest steepness. The duration of such a cross current spike can be between 1 and 100 ns.

Die Abstrahlung eines elektrischen Feldes durch Potentialdifferenzen in der Leiterfläche bei hohen Stromspitzen wird im mittleren Bereich der Leiterfläche durch den sandwichartigen Aufbau abgeschirmt . In den Randbereichen sorgt der zunehmende ohmsche Widerstand für eine weitgehende Absorption des aus dem magnetischen Feld und dem elektrischen Feld resultierenden elektromagnetischen Wechselfeldes.The radiation of an electrical field due to potential differences in the conductor area at high current peaks is shielded in the middle area of the conductor area by the sandwich-like structure. In the edge areas, the increasing ohmic resistance ensures extensive absorption of the alternating electromagnetic field resulting from the magnetic field and the electrical field.

Vorzugsweise sind die Isolierschichten zwischen der Fläche mit dem im Randbereich der Leiterplatte höheren mittleren ohmschen Gesamtwiderstand bezogen auf eine Flächeneinheit und den durchgehenden Leiterflächen so bemessen ist, dass der Abstand zwischen der absorbierenden Leiterfläche und der jeweiligen durchgehenden Leiterfläche zwischen 10 und 200 μm, vorzugsweise 50 μm beträgt.The insulating layers between the surface with the higher average total ohmic resistance in the edge region of the printed circuit board based on a surface unit and the continuous conductor surfaces are dimensioned such that the distance between the absorbent conductor surface and the respective continuous conductor surface is between 10 and 200 μm, preferably 50 μm is.

Das Leitersystem erhält dadurch einen außerordentlich niedrigen Wellenwiderstand, wodurch im Zusammenhang mit den Verlusten im Leitungssystem Strukturresonanzeffekte vermieden werden. Ferner führt die Dämpfung im Leitungssystem zur Verminderung von Überschwingern auf den Signalpulsen. Dagegen wird die Flankengeschwindigkeit kaum beeinflusst. Dies ist besonders bei Anwendung schneller Logik interessant, weil EMV- Maßnahmen normalerweise eine deutliche Verlangsamung der Flanken bewirken. Die mit den erfindungsgemäßen Maßnahmen er- reichbare Dämpfung der Abstrahlung liegt etwa im Bereich von 10 dB.This gives the conductor system an extremely low characteristic impedance, which means that structural resonance effects are avoided in connection with the losses in the line system. Furthermore, the attenuation in the line system leads to a reduction in overshoots on the signal pulses. In contrast, the edge speed is hardly influenced. This is particularly interesting when using fast logic, because EMC measures usually cause the edges to slow down significantly. The measures taken with the measures according to the invention Attainable attenuation of the radiation is approximately in the range of 10 dB.

Nachfolgend werden ein Ausführungsbeispiele der Erfindung anhand der Zeichnung erläutert .An exemplary embodiment of the invention is explained below with reference to the drawing.

In der Zeichnung zeigen:The drawing shows:

Fig. 1 einen Querschnitt durch eine mehrschichtige Leiterplatte,1 shows a cross section through a multilayer printed circuit board,

Fig. 2 eine Ansicht einer freigelegten Ebenen der Leiterplatte in einer ersten Ausgestaltung der Leiterfläche undFig. 2 is a view of an exposed planes of the circuit board in a first embodiment of the conductor surface and

Fig. 3 eine Ansicht derselben Ebene der Leiterplatte in einer zweiten Ausgestaltung der Leiterfläche.Fig. 3 is a view of the same level of the circuit board in a second embodiment of the conductor surface.

Die in Fig. 1 dargestellte Leiterplatte 10 umfasst beispielhaft drei Leiterflächen 12, 22 und 24 aus Kupfer, von denen die mittlere Leiterfläche 12 Versorgungspotential und die beiden benachbarten Leiterflächen 22, 24 Bezugspotential zur Energieversorgung integrierter Schaltkreise führen. Die Leiterflächen 12, 22 und 24 sind durch dünne Isolierschichten 20 voneinander getrennt. Außer diesen Leiterflächen sind noch weitere durch Isolierschichten 26 voneinander getrennte Flächen vorhanden, die Leiterbahnen 28 für Signalleitungen tragen.The printed circuit board 10 shown in FIG. 1 comprises, by way of example, three conductor surfaces 12, 22 and 24 made of copper, of which the middle conductor surface 12 leads to supply potential and the two adjacent conductor surfaces 22, 24 reference potential for supplying energy to integrated circuits. The conductor surfaces 12, 22 and 24 are separated from one another by thin insulating layers 20. In addition to these conductor surfaces, there are further surfaces separated from one another by insulating layers 26, which carry conductor tracks 28 for signal lines.

Die beiden Bezugspotential führenden Leiterflächen 22, 24 erstrecken sich vollflächig bis an den Rand der Leiterplatte 10, wobei lediglich Bohrungen zur Kontaktierung oder isolierten Durchführung der Anschlüsse von Bauelementen ausgespart sind. Die mittlere, Versorgungspotential führende Leiterfläche 12 ist im innen liegenden Bereich 30 ebenfalls vollflächig ausgeführt, unter Aussparung der Bohrungen zur Kontaktierung oder isolierten Durchführung der Anschlüsse von Bauelementen.The two reference potential-conducting conductor surfaces 22, 24 extend over the entire surface to the edge of the circuit board 10, wherein only holes for contacting or insulated implementation of the connections of components are left out. The middle conductor surface 12, which carries supply potential, is likewise designed over the entire area in the inner region 30, with the exception of the bores for contacting or insulated connection of components.

Ein umlaufender Randbereich 14 ist jedoch anders gestaltet, wie die Ansicht der Leiterfläche 12 in den Figuren 2 und 3 zeigt. In Fig. 2 bildet die Leiterfläche 12 Spalte 16, die sich keilförmig zum Rand der Leiterplatte 10 erweitern. Bei der in Fig. 3 dargestellten Alternative ist der Randbereich 14 der Leiterfläche 12 durch Aussparungen 18 zerklüftet. Bei beiden Ausführungen sind die Spalte 16 oder Aussparungen 18 mit Karbonmasse ausgefüllt, einem elektrisch leitenden Material, dessen spezifischer ohmscher Widerstand wesentlich höher als der des metallischen Materials Kupfer ist.A peripheral edge region 14 is, however, designed differently, as the view of the conductor surface 12 in FIGS. 2 and 3 shows. In FIG. 2, the conductor surface 12 forms gaps 16 which widen in a wedge shape towards the edge of the printed circuit board 10. In the alternative shown in FIG. 3, the edge region 14 of the conductor surface 12 is fissured by recesses 18. In both versions, the gaps 16 or recesses 18 are filled with carbon mass, an electrically conductive material, the specific ohmic resistance of which is significantly higher than that of the metallic material copper.

Stromimpulse durch Querströme, die die integrierten Schaltungen bei Wechsel des Ausgangspotentials ziehen, regen elektromagnetische Stoßwellen an den Leiterflächen 12 an. Der Strom, der die elektromagnetische Stoßwelle begleitet, wird im Randbereich 14 von dem gut leitenden Kupfer in die schlecht leitende Karbonmasse verdrängt. Dabei wird die elektromagnetische Energie in Wärme umgesetzt und so die Abstrahlung in die Umgebung gedämpft . Current pulses through cross currents, which pull the integrated circuits when the output potential changes, excite electromagnetic shock waves on the conductor surfaces 12. The current which accompanies the electromagnetic shock wave is displaced in the edge region 14 by the copper, which conducts well, into the poorly conductive carbon mass. The electromagnetic energy is converted into heat and the radiation into the environment is dampened.

Claims

P a t e n t a n s p r ü c h e Patent claims 1. Mehrschichtige Leiterplatte (10) mit wenigstens einer Versorgungspotential oder Bezugspotential führenden Leiterfläche (12) , die metallisches Material umfasst, dadurch gekennzeichnet, dass die Leiterfläche (12) im Randbereich (14) der Leiterplatte (10) einen mittleren ohmschen Gesamtwiderstand bezogen auf eine Flächeneinheit aufweist, der erheblich höher ist als der ohmsche Widerstand derselben Fläche (12) in einem weiter innen liegenden Bereich (30) der Leiterplatte (10), bezogen auf dieselbe Flächeneinheit.1. multilayer printed circuit board (10) with at least one supply potential or reference potential-conducting conductor surface (12) comprising metallic material, characterized in that the conductor surface (12) in the edge region (14) of the circuit board (10) has an average total ohmic resistance in relation to a Has area unit, which is considerably higher than the ohmic resistance of the same area (12) in a further inner area (30) of the printed circuit board (10), based on the same area unit. 2. Mehrschichtige Leiterplatte (10) nach Anspruch 1, dadurch gekennzeichnet, dass der ohmsche Widerstand bezogen auf eine Flächeneinheit im Randbereich (14) zum Rand hin ansteigt .2. Multi-layer printed circuit board (10) according to claim 1, characterized in that the ohmic resistance relative to a unit area in the edge region (14) increases towards the edge. 3. Mehrschichtige Leiterplatte (10) nach Anspruch 2, dadurch gekennzeichnet, dass der ohmsche Widerstand bezogen auf eine Flächeneinheit im Randbereich (14) zum Rand hin stetig ansteigt.3. Multi-layer circuit board (10) according to claim 2, characterized in that the ohmic resistance based on a surface unit in the edge region (14) increases steadily towards the edge. 4. Leiterplatte nach einem der Ansprüche 1 bis 3 , dadurch gekennzeichnet, dass der Randbereich (14) durch Spalte (16) oder Aussparungen (18) zerklüftet ist und dass die Spalte (16) oder Aussparungen (18) mit einem elektrisch leitenden Material ausgefüllt sind, dessen spezifischer ohmscher Widerstand wesentlich höher als der des metallischen Materials ist.4. Printed circuit board according to one of claims 1 to 3, characterized in that the edge region (14) is fissured by gaps (16) or recesses (18) and that the gaps (16) or recesses (18) with an electrically conductive Material are filled, the specific ohmic resistance is significantly higher than that of the metallic material. 5. Leiterplatte nach Anspruch 4, dadurch gekennzeichnet, dass das die Spalte (16) oder Aussparungen (18) ausfüllende elektrisch leitende Material Karbonmasse ist .5. Printed circuit board according to claim 4, characterized in that the gap (16) or recesses (18) filling electrically conductive material is carbon mass. 6. Leiterplatte nach Anspruch 4 oder 5, dadurch gekennzeichnet, dass das die Spalte (16) oder Aussparungen (18) ausfüllende elektrisch leitende Material in Dickfilmtechnik aufgebracht ist .6. Printed circuit board according to claim 4 or 5, characterized in that the gap (16) or recesses (18) filling electrically conductive material is applied in thick film technology. 7. Leiterplatte nach Anspruch 4 oder 5, dadurch gekennzeichnet, dass das die Spalte (16) oder Aussparungen (18) ausfüllende elektrisch leitende Material durch Siebdruck aufgebracht ist .7. Printed circuit board according to claim 4 or 5, characterized in that the gap (16) or recesses (18) filling electrically conductive material is applied by screen printing. 8. Leiterplatte nach einem der Ansprüche 1 bis 7, dadurch gekennzeichnet, dass die Fläche (12) mit dem im Randbereich (14) der Leiterplatte (10) höheren mittleren ohmschen Gesamt- widerstand bezogen auf eine Flächeneinheit zwischen durchgehenden Leiterflächen (22, 24) angeordnet ist.8. Printed circuit board according to one of claims 1 to 7, characterized in that the surface (12) with the higher average ohmic resistance in the edge region (14) of the printed circuit board (10) based on a unit area between continuous conductor surfaces (22, 24) is arranged. 9. Leiterplatte nach Anspruch 8, dadurch gekennzeichnet, dass die Isolierschichten zwischen der Fläche (12) mit dem im Randbereich (14) der Leiterplatte (10) höheren mittleren ohmschen Gesamtwiderstand bezogen auf eine Flächeneinheit und den durchgehenden Leiterflächen (22, 24) so bemessen ist, dass der Abstand zwischen der Fläche (12) und der jeweiligen durchgehenden Leiterfläche (22, 24) zwischen 10 und 200 μm, vorzugsweise 50 μm beträgt. 9. Printed circuit board according to claim 8, characterized in that the insulating layers between the surface (12) with the higher mean ohmic total resistance in the edge region (14) of the printed circuit board (10) based on a unit area and the continuous conductor surfaces (22, 24) so dimensioned is that the distance between the surface (12) and the respective continuous conductor surface (22, 24) between 10 and 200 microns, preferably 50 microns.
PCT/DE2002/000754 2001-03-08 2002-02-28 Multilayer printed circuit board WO2002074025A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE10291003T DE10291003D2 (en) 2001-03-08 2002-02-28 Multi-layer circuit board
AU2002308354A AU2002308354A1 (en) 2001-03-08 2002-02-28 Multilayer printed circuit board

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10111333 2001-03-08
DE10111333.1 2001-03-08

Publications (2)

Publication Number Publication Date
WO2002074025A2 true WO2002074025A2 (en) 2002-09-19
WO2002074025A3 WO2002074025A3 (en) 2002-12-05

Family

ID=7676840

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2002/000754 WO2002074025A2 (en) 2001-03-08 2002-02-28 Multilayer printed circuit board

Country Status (3)

Country Link
AU (1) AU2002308354A1 (en)
DE (1) DE10291003D2 (en)
WO (1) WO2002074025A2 (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10336290A1 (en) * 2003-08-07 2005-03-17 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Circuit board for highest clocking frequencies, which includes a supply layer, also has damping structure attenuating waves more strongly at edges than in center
US8252937B2 (en) 2007-09-14 2012-08-28 Janssen Pharmaceuticals, Inc. 1,3-disubstituted 4-(aryl-X-phenyl)-1H-pyridin-2-ones
US8299101B2 (en) 2007-03-07 2012-10-30 Janssen Pharmaceuticals, Inc. 1,4-disubstituted 3-cyano-pyridone derivatives and their use as positive mGluR2-receptor modulators
US8399493B2 (en) 2004-09-17 2013-03-19 Janssen Pharmaceuticals, Inc. Pyridinone derivatives and their use as positive allosteric modulators of mGluR2-receptors
US9708315B2 (en) 2013-09-06 2017-07-18 Janssen Pharmaceutica Nv 1,2,4-triazolo[4,3-a]pyridine compounds and their use as positive allosteric modulators of MGLUR2 receptors
US9737533B2 (en) 2009-05-12 2017-08-22 Janssen Pharmaceuticals. Inc. 1,2,4-triazolo [4,3-A] pyridine derivatives and their use for the treatment of prevention of neurological and psychiatric disorders
US10106542B2 (en) 2013-06-04 2018-10-23 Janssen Pharmaceutica Nv Substituted 6,7-dihydropyrazolo[1,5-a]pyrazines as negative allosteric modulators of mGluR2 receptors
US10537573B2 (en) 2014-01-21 2020-01-21 Janssen Pharmaceutica Nv Combinations comprising positive allosteric modulators or orthosteric agonists of metabotropic glutamatergic receptor subtype 2 and their use
US11071729B2 (en) 2007-09-14 2021-07-27 Addex Pharmaceuticals S.A. 1′,3′-disubstituted-4-phenyl-3,4,5,6-tetrahydro-2H,1′H-[1,4′]bipyridinyl-2′-ones
US11369606B2 (en) 2014-01-21 2022-06-28 Janssen Pharmaceutica Nv Combinations comprising positive allosteric modulators or orthosteric agonists of metabotropic glutamatergic receptor subtype 2 and their use

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI417095B (en) 2006-03-15 2013-12-01 Janssen Pharmaceuticals Inc 1,4-disubstituted 3-cyano-pyridone derivatives and their use as positive allosteric modulators of mglur2-receptors
TW200845978A (en) 2007-03-07 2008-12-01 Janssen Pharmaceutica Nv 3-cyano-4-(4-tetrahydropyran-phenyl)-pyridin-2-one derivatives
CA2735764C (en) 2008-09-02 2016-06-14 Ortho-Mcneil-Janssen Pharmaceuticals, Inc. 3-azabicyclo[3.1.0]hexyl derivatives as modulators of metabotropic glutamate receptors
WO2010060589A1 (en) 2008-11-28 2010-06-03 Ortho-Mcneil-Janssen Pharmaceuticals, Inc. Indole and benzoxazine derivatives as modulators of metabotropic glutamate receptors
EA020671B1 (en) 2009-05-12 2014-12-30 Янссен Фармасьютикалз, Инк. 1,2,4-TRIAZOLO[4,3-a]PYRIDINE DERIVATIVES AND THEIR USE AS POSITIVE ALLOSTERIC MODULATORS OF mGluR2 RECEPTORS
MY153913A (en) 2009-05-12 2015-04-15 Janssen Pharmaceuticals Inc 7-aryl-1,2,4-triazolo[4,3-a]pyridine derivatives and their use as positive allosteric modulators of mglur2 receptors
ES2552879T3 (en) 2010-11-08 2015-12-02 Janssen Pharmaceuticals, Inc. 1,2,4-Triazolo [4,3-a] pyridine derivatives and their use as positive allosteric modulators of mGluR2 receptors
EP2643320B1 (en) 2010-11-08 2015-03-04 Janssen Pharmaceuticals, Inc. 1,2,4-TRIAZOLO[4,3-a]PYRIDINE DERIVATIVES AND THEIR USE AS POSITIVE ALLOSTERIC MODULATORS OF MGLUR2 RECEPTORS
US9271967B2 (en) 2010-11-08 2016-03-01 Janssen Pharmaceuticals, Inc. 1,2,4-triazolo[4,3-a]pyridine derivatives and their use as positive allosteric modulators of mGluR2 receptors

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5898576A (en) * 1996-11-12 1999-04-27 Bay Networks Inc. Printed circuit board including a terminated power plane and method of manufacturing the same
JP2867985B2 (en) * 1996-12-20 1999-03-10 日本電気株式会社 Printed circuit board
DE19854271A1 (en) * 1998-11-25 2000-05-31 Ilfa Industrieelektronik Und L Circuit board
DE60131485T2 (en) * 2000-02-29 2008-10-09 Kyocera Corp. circuit board

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10336290A1 (en) * 2003-08-07 2005-03-17 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Circuit board for highest clocking frequencies, which includes a supply layer, also has damping structure attenuating waves more strongly at edges than in center
US8399493B2 (en) 2004-09-17 2013-03-19 Janssen Pharmaceuticals, Inc. Pyridinone derivatives and their use as positive allosteric modulators of mGluR2-receptors
US8299101B2 (en) 2007-03-07 2012-10-30 Janssen Pharmaceuticals, Inc. 1,4-disubstituted 3-cyano-pyridone derivatives and their use as positive mGluR2-receptor modulators
US9067891B2 (en) 2007-03-07 2015-06-30 Janssen Pharmaceuticals, Inc. 1,4-disubstituted 3-cyano-pyridone derivatives and their use as positive allosteric modulators of mGluR2-receptors
US8252937B2 (en) 2007-09-14 2012-08-28 Janssen Pharmaceuticals, Inc. 1,3-disubstituted 4-(aryl-X-phenyl)-1H-pyridin-2-ones
US11071729B2 (en) 2007-09-14 2021-07-27 Addex Pharmaceuticals S.A. 1′,3′-disubstituted-4-phenyl-3,4,5,6-tetrahydro-2H,1′H-[1,4′]bipyridinyl-2′-ones
US9737533B2 (en) 2009-05-12 2017-08-22 Janssen Pharmaceuticals. Inc. 1,2,4-triazolo [4,3-A] pyridine derivatives and their use for the treatment of prevention of neurological and psychiatric disorders
US10071095B2 (en) 2009-05-12 2018-09-11 Janssen Pharmaceuticals, Inc. 1,2,4-triazolo [4,3-A] pyridine derivatives and their use for the treatment of neurological and psychiatric disorders
US10106542B2 (en) 2013-06-04 2018-10-23 Janssen Pharmaceutica Nv Substituted 6,7-dihydropyrazolo[1,5-a]pyrazines as negative allosteric modulators of mGluR2 receptors
US10584129B2 (en) 2013-06-04 2020-03-10 Janssen Pharmaceuticals Nv Substituted 6,7-dihydropyrazolo[1,5-a]pyrazines as negative allosteric modulators of mGluR2 receptors
US9708315B2 (en) 2013-09-06 2017-07-18 Janssen Pharmaceutica Nv 1,2,4-triazolo[4,3-a]pyridine compounds and their use as positive allosteric modulators of MGLUR2 receptors
US10537573B2 (en) 2014-01-21 2020-01-21 Janssen Pharmaceutica Nv Combinations comprising positive allosteric modulators or orthosteric agonists of metabotropic glutamatergic receptor subtype 2 and their use
US11103506B2 (en) 2014-01-21 2021-08-31 Janssen Pharmaceutica Nv Combinations comprising positive allosteric modulators or orthosteric agonists of metabotropic glutamatergic receptor subtype 2 and their use
US11369606B2 (en) 2014-01-21 2022-06-28 Janssen Pharmaceutica Nv Combinations comprising positive allosteric modulators or orthosteric agonists of metabotropic glutamatergic receptor subtype 2 and their use
US12048696B2 (en) 2014-01-21 2024-07-30 Janssen Pharmaceutica Nv Combinations comprising positive allosteric modulators or orthosteric agonists of metabotropic glutamatergic receptor subtype 2 and their use

Also Published As

Publication number Publication date
AU2002308354A1 (en) 2002-09-24
DE10291003D2 (en) 2004-04-15
WO2002074025A3 (en) 2002-12-05

Similar Documents

Publication Publication Date Title
WO2002074025A2 (en) Multilayer printed circuit board
DE10019839B4 (en) Multilayer capacitor, use of the multilayer capacitor, circuit arrangement and wiring substrate therewith
DE19911731C2 (en) Printed circuit board
DE69637165T2 (en) Multilayer printed circuit board and its use as a contact grid package
DE10027870B4 (en) Laminated capacitor and mounting arrangement
DE69016441T2 (en) MULTI-LAYER BOARD, WHICH HIGH-FREQUENCY INTERFERENCES SUPPRESSED BY HIGH-FREQUENCY SIGNALS.
DE10019838B4 (en) Multi-layer capacitor, wiring substrate therewith and use of such a multi-layer capacitor
DE69623425T2 (en) Structure of a choke coil
DE69325953T2 (en) Power semiconductor module
DE69033784T2 (en) Printed circuit board
EP0459179B1 (en) IC-housing made of three coated dielectric plates
DE10019229A1 (en) Multilayer capacitor for use in high frequency circuits
DE60131485T2 (en) circuit board
EP2609796B1 (en) Multi-level circuit board for high-frequency applications
EP0757515B1 (en) Control circuit for vehicle
EP0376100B1 (en) Method and lead frame for mounting a semiconductor
EP0801884B1 (en) Module mounting rack for an electronic control unit with signal-processing components and rapid-operation digital components
EP1217659B1 (en) Power Semiconductor Modul with an High Withstanding against Voltage
DE3937183A1 (en) METHOD FOR EMISSION RADIATION DAMPING ON CIRCUIT BOARDS
DE60130717T2 (en) Circuit board with contact surfaces for connection to an electronic component mounted thereon
DE69016471T2 (en) Printed circuit board, suitable for avoiding electromagnetic interference.
WO2003049185A2 (en) Semiconductor component circuit with a reduced oscillation tendency
DE9214898U1 (en) Control unit
DE10103472A1 (en) Semiconductor module for electronic power regulator has carrier with conductive layers on either side of insulating layer incorporating further conductive layer
DE19516918A1 (en) Control device, in particular for controlling functions of a motor vehicle

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
AK Designated states

Kind code of ref document: A3

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
REF Corresponds to

Ref document number: 10291003

Country of ref document: DE

Date of ref document: 20040415

Kind code of ref document: P

WWE Wipo information: entry into national phase

Ref document number: 10291003

Country of ref document: DE

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Ref document number: JP