WO2002065699A2 - Method and device for ensuring a regulated data transfer on a two-wire bus - Google Patents
Method and device for ensuring a regulated data transfer on a two-wire bus Download PDFInfo
- Publication number
- WO2002065699A2 WO2002065699A2 PCT/EP2002/001204 EP0201204W WO02065699A2 WO 2002065699 A2 WO2002065699 A2 WO 2002065699A2 EP 0201204 W EP0201204 W EP 0201204W WO 02065699 A2 WO02065699 A2 WO 02065699A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- bus
- address
- station
- stl
- stations
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/407—Bus networks with decentralised control
- H04L12/413—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection (CSMA-CD)
- H04L12/4135—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection (CSMA-CD) using bit-wise arbitration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4286—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a handshaking protocol, e.g. RS232C link
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/407—Bus networks with decentralised control
- H04L12/413—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection (CSMA-CD)
Definitions
- the invention relates to a method and device for ensuring a regulated data transfer on a two-wire bus according to the preamble of claim 1 and claim 8.
- Bus systems are used in particular in so-called building management.
- each station has an individual address. If a station wants to send data to another station, it first sends its address, whereupon the addressed station becomes active, while all other stations remain passive. If the receiving station has understood the signal perfectly, it sends a receipt, which concludes the data transmission. The bus is then free again for the next transmission.
- the present invention is therefore based on the object of specifying a method by means of which the controlled data transfer on a two-wire bus can be ensured with simple means.
- a start pulse is given to the bus by a central bus supply device
- evaluation electronics compare the sent address and the signal picked up by the bus bit by bit and, in the event of an inequality, stops the transmission of the own address
- the present invention is based on the idea of having the stations connected to the bus, which have to transmit a message, send their address simultaneously and synchronously on the bus.
- each sending station compares the signal picked up by the bus, which is a superposition of the addresses of all active stations, bit by bit with its own address. If a station detects that its address signal differs from the signal picked up by the bus, it immediately stops sending its own address. To this This ensures that only the station with the highest or lowest address remains active at the end. This is the top priority station. This then sends its data on the bus.
- all stations connected to the bus continue to listen, so that each station knows which stations are currently exchanging a message.
- Another advantage is that the data can be sent to the bus with the aid of a simple switch, preferably in the form of a transistor in an open collector circuit.
- the address and possibly the further data are sent by means of a first shift register which, according to a further development, converts the address stored in parallel in an address memory into serial information.
- the signals picked up by the bus are read bit-by-bit into a second shift register which, according to an advantageous embodiment, acts as a serial-parallel converter and converts the data read bit-by-bit into a parallel signal.
- the voltage level on the bus is lowered for a defined period of time in order to generate the start pulse. This is done by the central bus supply device.
- the receiving station advantageously sends a receipt at the end, which ensures that the sending station is switched from the active to the inactive state.
- Another object of the present invention is to specify a bus system with the aid of which the method for ensuring the regulated data transfers can be carried out on the two-wire bus.
- a significant advantage is the simple construction, in particular the fact that only a simple switch, preferably in the form of a transistor in an open-collector circuit, is sufficient to send addresses and data to the bus.
- the evaluation electronics which compare the signals picked up by the bus with their own address, are also particularly simple. It consists of a synchronous detector that determines the clock frequency of the station clock from the signals picked up by the bus, a first and a second AND gate and an RS flip-flop.
- the first AND gate has the task of comparing the signals and, in the event of an inequality, driving the RS flip-flop, which emits a defined stop signal at its output, with the aid of which the reading of the station address from the shift register is stopped immediately.
- Each station is preferably equipped with a voltage regulator, which generates the operating voltage of the station from the voltage on the bus.
- a diode advantageously decouples the station's voltage regulator from the bus, so that the short-circuiting of the bus required for signal transmission does not interfere with the station's voltage supply.
- the central supply device is equipped with a controlled switch, with the aid of which the voltage potential on the bus can be controlled.
- 1 is a two-wire bus system with two stations shown as a block diagram
- Fig. 2 shows an exemplary data telegram
- FIG. 3 shows the address areas for data telegrams according to FIG. 2 for three stations.
- Fig. 1 shows a two-wire bus BUS, which is fed by a central supply device NG.
- the line connected to the minus potential can be grounded.
- a controlled switch SS is assigned to the line connected to the plus potential, by means of which the level of the plus potential can be changed.
- the voltage potential can either be raised or lowered.
- Fig. 1 only two stations Stl, St2 are shown.
- Each station Stl, St2 is provided with its own voltage supply fed by the bus BUS, consisting of a capacitor C, a voltage regulator VR and a diode D, which voltage regulator VR decoupled from the bus BUS.
- the voltage regulator VR generates the operating voltage Vb.
- each station is equipped with a microprocessor ⁇ P.
- the address signal stored in the first shift register SRI is read out bit-by-bit clock-controlled by all stations that have something to say.
- the signals reach a short-circuit switch S via a non-link NOT. All short-circuit switches S are connected between the two bus wires.
- the switch S is actuated and the bus BUS is short-circuited, which corresponds to a logical "0". If the first shift register SRI sends a "1", the switch S remains open. The bus BUS is not short-circuited, which corresponds to a logical "1".
- each station Stl, St2 contains evaluation electronics. This initially consists of a synchronous detector SyncD, which uses the recorded signals to generate the clock frequency tf of the station clock dock generated. This ensures that all stations connected to the bus use the same clock frequency tf.
- the evaluation electronics also contain a first AND gate AND1.
- the station address read by the first shift register SRI and the signal picked up by the bus BUS are fed to the latter. As long as the transmitted address signal and the signal picked up by the bus BUS are identical, the first AND gate AND1 does not emit an output signal.
- the station clock generated by the synchronous detector SyncD is supplied with the frequency tf to the clock inputs cl of the two shift registers SRI, SR2.
- a second AND gate AND2 is connected upstream of the clock input of the first shift register SRI.
- the system clock and the stop signal from the output of the RS flip-flop FF are fed to the latter.
- the station cycle can pass the second AND gate AND2 unhindered.
- the second AND gate AND2 is blocked, so that the first shift register SRI interrupts the reading of the station address.
- this is the station with the lowest address and the highest priority.
- FIG. 2 shows an example of a data telegram as it can be used for data traffic via the two-wire bus BUS.
- the active station transmits, for example, a type signal Tx, after a further defined pause a receiver address EAx and after a further defined pause its data packet DATAx. If the receiver station has understood everything correctly, it sends a receiver acknowledgment signal EQx. This signal switches the sending station from the active to the inactive state. After a further pause P2, the process described can start again.
- the central supply device NG gives the start pulse P1 to the bus BUS at the time ts. After a defined period of time, all three stations Stl, St2, St3 simultaneously start sending their address bit by bit and clock-controlled to the bus BUS. This process takes as long as the addresses are identical.
- the station Stl sent a logical "1", the stations St2 and St3 a logical "0". Their short-circuit switches S have short-circuited the bus BUS, so that the station ST1 receives a "0". Because of this deviation, the first station Stl stops sending its address SAl. However, the receiving process continues.
- the second station St2 also noticed a deviation in the addresses. At this point in time, it therefore stops sending its address SA2, but continues to receive the bus signals.
- station St3 Because of the lower address and the higher priority associated with it, station St3 has prevailed. It accomplishes that Transfer of their address SA3, which is completed at the time te. This is followed by the transmission of the further data packets explained with reference to FIG. 2.
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2002250892A AU2002250892A1 (en) | 2001-02-14 | 2002-02-06 | Method and device for ensuring a regulated data transfer on a two-wire bus |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10106846.8 | 2001-02-14 | ||
DE2001106846 DE10106846A1 (en) | 2001-02-14 | 2001-02-14 | Method and device for ensuring a regulated data transfer on a two-wire bus |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2002065699A2 true WO2002065699A2 (en) | 2002-08-22 |
WO2002065699A3 WO2002065699A3 (en) | 2002-11-14 |
Family
ID=7674015
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2002/001204 WO2002065699A2 (en) | 2001-02-14 | 2002-02-06 | Method and device for ensuring a regulated data transfer on a two-wire bus |
Country Status (3)
Country | Link |
---|---|
AU (1) | AU2002250892A1 (en) |
DE (1) | DE10106846A1 (en) |
WO (1) | WO2002065699A2 (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4745596A (en) * | 1985-07-16 | 1988-05-17 | Honda Giken Kogyo Kabushiki Kaisha | Multiplex communication system |
US4887262A (en) * | 1987-03-30 | 1989-12-12 | U.S. Philips Corporation | Single-channel bus system for multi-master use with bit cell synchronization, and master station comprising a bit cell synchronization element suitable for this purpose |
EP0756402A1 (en) * | 1995-07-25 | 1997-01-29 | Cho, Jin-young | Distributed serial arbitration system |
EP0940950A2 (en) * | 1998-03-06 | 1999-09-08 | STMicroelectronics GmbH | Node interface in a data network |
-
2001
- 2001-02-14 DE DE2001106846 patent/DE10106846A1/en not_active Withdrawn
-
2002
- 2002-02-06 AU AU2002250892A patent/AU2002250892A1/en not_active Abandoned
- 2002-02-06 WO PCT/EP2002/001204 patent/WO2002065699A2/en not_active Application Discontinuation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4745596A (en) * | 1985-07-16 | 1988-05-17 | Honda Giken Kogyo Kabushiki Kaisha | Multiplex communication system |
US4887262A (en) * | 1987-03-30 | 1989-12-12 | U.S. Philips Corporation | Single-channel bus system for multi-master use with bit cell synchronization, and master station comprising a bit cell synchronization element suitable for this purpose |
EP0756402A1 (en) * | 1995-07-25 | 1997-01-29 | Cho, Jin-young | Distributed serial arbitration system |
EP0940950A2 (en) * | 1998-03-06 | 1999-09-08 | STMicroelectronics GmbH | Node interface in a data network |
Non-Patent Citations (1)
Title |
---|
ETSCHBERGER KONRAD: "CAN Controller-Area-Network Grundlagen, Protokolle, Bausteine, Anwendungen" 1994 , CRL HANSER VERLAG M]NCHEN WIEN , GERMANY XP002210677 Seite 37, Absatz 2 -Seite 43, Absatz 2 * |
Also Published As
Publication number | Publication date |
---|---|
DE10106846A1 (en) | 2002-09-05 |
WO2002065699A3 (en) | 2002-11-14 |
AU2002250892A1 (en) | 2002-08-28 |
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