WO2002058158A3 - Field effect transistor with redued gate delay and method of fabricating the same - Google Patents

Field effect transistor with redued gate delay and method of fabricating the same Download PDF

Info

Publication number
WO2002058158A3
WO2002058158A3 PCT/US2001/049970 US0149970W WO02058158A3 WO 2002058158 A3 WO2002058158 A3 WO 2002058158A3 US 0149970 W US0149970 W US 0149970W WO 02058158 A3 WO02058158 A3 WO 02058158A3
Authority
WO
WIPO (PCT)
Prior art keywords
gate electrode
field effect
effect transistor
redued
fabricating
Prior art date
Application number
PCT/US2001/049970
Other languages
French (fr)
Other versions
WO2002058158A2 (en
Inventor
Manfred Horstmann
Rolf Stephan
Karsten Wieczorek
Stephan Kruegel
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE10056873A external-priority patent/DE10056873B4/en
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority to AU2002246796A priority Critical patent/AU2002246796A1/en
Publication of WO2002058158A2 publication Critical patent/WO2002058158A2/en
Publication of WO2002058158A3 publication Critical patent/WO2002058158A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Ceramic Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A transistor formed on a substrate 201 comprises a gate electrode 207 having a lateral extension at the foot of the gate electrode that is less than the average lateral extension of the gate electrode 207. The increased cross-section of the gate electrode 207 compared to the rectangular cross-sectional shape of a prior art device provides for a significantly reduced gate resistance while the effective gate length, i.e., the lateral extension of the gate electrode at its foot, may be scaled down to a size of 100 nm and beyond. Moreover, a method for forming the field effect transistor described above is disclosed.
PCT/US2001/049970 2000-11-16 2001-10-23 Field effect transistor with redued gate delay and method of fabricating the same WO2002058158A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002246796A AU2002246796A1 (en) 2000-11-16 2001-10-23 Field effect transistor with redued gate delay and method of fabricating the same

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE10056873.4 2000-11-16
DE10056873A DE10056873B4 (en) 2000-11-16 2000-11-16 Method for producing a gate electrode of a field effect transistor with reduced gate resistance
US09/847,622 2001-05-02
US09/847,622 US6798028B2 (en) 2000-11-16 2001-05-02 Field effect transistor with reduced gate delay and method of fabricating the same

Publications (2)

Publication Number Publication Date
WO2002058158A2 WO2002058158A2 (en) 2002-07-25
WO2002058158A3 true WO2002058158A3 (en) 2003-01-23

Family

ID=26007681

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/049970 WO2002058158A2 (en) 2000-11-16 2001-10-23 Field effect transistor with redued gate delay and method of fabricating the same

Country Status (2)

Country Link
AU (1) AU2002246796A1 (en)
WO (1) WO2002058158A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101142820B1 (en) 2004-06-15 2012-05-08 어플라이드 스핀트로닉스, 인크. A novel capping structure for enhancing dR/R of the MTJ device

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015048532A1 (en) 2013-09-26 2015-04-02 Synopsys, Inc. Parameter extraction of dft
US20160162625A1 (en) 2013-09-26 2016-06-09 Synopsys, Inc. Mapping Intermediate Material Properties To Target Properties To Screen Materials
US10402520B2 (en) 2013-09-26 2019-09-03 Synopsys, Inc. First principles design automation tool
WO2015048400A1 (en) * 2013-09-26 2015-04-02 Synopsys, Inc. Estimation of effective channel length for finfets and nano-wires
US10489212B2 (en) 2013-09-26 2019-11-26 Synopsys, Inc. Adaptive parallelization for multi-scale simulation
US10516725B2 (en) 2013-09-26 2019-12-24 Synopsys, Inc. Characterizing target material properties based on properties of similar materials
US10734097B2 (en) 2015-10-30 2020-08-04 Synopsys, Inc. Atomic structure optimization
US10078735B2 (en) 2015-10-30 2018-09-18 Synopsys, Inc. Atomic structure optimization

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997023902A2 (en) * 1995-12-21 1997-07-03 Siemens Aktiengesellschaft Process for producing an mos transistor
US5998273A (en) * 1999-01-25 1999-12-07 International Business Machines Corporation Fabrication of semiconductor device having shallow junctions
US5998285A (en) * 1998-07-30 1999-12-07 Winbond Electronics Corp. Self-aligned T-shaped process for deep submicron Si MOSFET's fabrication
US6046105A (en) * 1997-04-30 2000-04-04 Texas Instruments Incorporated Preferential lateral silicidation of gate with low source and drain silicon consumption

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997023902A2 (en) * 1995-12-21 1997-07-03 Siemens Aktiengesellschaft Process for producing an mos transistor
US6046105A (en) * 1997-04-30 2000-04-04 Texas Instruments Incorporated Preferential lateral silicidation of gate with low source and drain silicon consumption
US5998285A (en) * 1998-07-30 1999-12-07 Winbond Electronics Corp. Self-aligned T-shaped process for deep submicron Si MOSFET's fabrication
US5998273A (en) * 1999-01-25 1999-12-07 International Business Machines Corporation Fabrication of semiconductor device having shallow junctions

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101142820B1 (en) 2004-06-15 2012-05-08 어플라이드 스핀트로닉스, 인크. A novel capping structure for enhancing dR/R of the MTJ device

Also Published As

Publication number Publication date
WO2002058158A2 (en) 2002-07-25
AU2002246796A1 (en) 2002-07-30

Similar Documents

Publication Publication Date Title
KR100327347B1 (en) Metal oxide semiconductor field effect transistor having reduced resistance between source and drain and fabricating method thereof
WO2004038808A3 (en) Double and triple gate mosfet devices and methods for making same
TW200501424A (en) Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication the same
WO2003103032A3 (en) A method for making a semiconductor device having a high-k gate dielectric
TW200501411A (en) Structure and method for forming the gate electrode in a multiple-gate transistor
WO2003081687A3 (en) Self-aligned nanotube field effect transistor and method of fabricating same
EP1227514A3 (en) Method for forming a gate dielectric with high-K and low-K regions
SG108291A1 (en) Method for forming variable-k gate dielectric
WO2004038770A3 (en) Integrated circuit arrangement comprising a capacitor, and production method
EP1071125A3 (en) Process for producing transistors having independently adjustable parameters
KR100374649B1 (en) Structure of semiconductor device and manufacturing method thereof
WO2005057615A3 (en) Closed cell trench metal-oxide-semiconductor field effect transistor
WO2004093197A3 (en) Method for forming structures in finfet devices
TW200507099A (en) Process for forming dual metal gate structures
WO2002097889A3 (en) Semiconductor device and a method therefor
GB2366911B (en) Semiconductor device having desired gate profile and method of fabricating the same
EP1387399A3 (en) Gate dielectric and method
WO2007120283A3 (en) Transistor with immersed contacts and methods of forming thereof
SG86432A1 (en) A method to form a high k dielectric gate insulator layer, a metal gate structure, and self-aligned channel regions, post source/drain formation
WO2002078091A3 (en) Field effect transistor structure and method of manufacture
WO2006104562A3 (en) Method of forming a semiconductor device having asymmetric dielectric regions and structure thereof
WO2003021685A1 (en) Semiconductor device and production method thereof
WO2000034984A3 (en) Transistor with notched gate
WO2004012270A3 (en) Field effect transistor and method of manufacturing same
WO2002058158A3 (en) Field effect transistor with redued gate delay and method of fabricating the same

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
AK Designated states

Kind code of ref document: A3

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP