WO2002054840A1 - Method for producing electroconductive structures - Google Patents

Method for producing electroconductive structures Download PDF

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Publication number
WO2002054840A1
WO2002054840A1 PCT/CH2002/000001 CH0200001W WO02054840A1 WO 2002054840 A1 WO2002054840 A1 WO 2002054840A1 CH 0200001 W CH0200001 W CH 0200001W WO 02054840 A1 WO02054840 A1 WO 02054840A1
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WO
WIPO (PCT)
Prior art keywords
substrate
surface
structures
copper
characterized
Prior art date
Application number
PCT/CH2002/000001
Other languages
German (de)
French (fr)
Inventor
Philippe Steiert
Silke Walz
Original Assignee
Elmicron Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to CHPCT/CH01/00004 priority Critical
Priority to PCT/CH2001/000004 priority patent/WO2001050825A1/en
Priority to CH1232/01 priority
Priority to CH12322001 priority
Application filed by Elmicron Ag filed Critical Elmicron Ag
Priority claimed from US10/250,496 external-priority patent/US20040060728A1/en
Publication of WO2002054840A1 publication Critical patent/WO2002054840A1/en

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Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/38Improvement of the adhesion between the insulating substrate and the metal
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00Electroplating: Baths therefor
    • C25D3/02Electroplating: Baths therefor from solutions
    • C25D3/38Electroplating: Baths therefor from solutions of copper
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/107Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/423Plated through-holes or plated via connections characterised by electroplating method
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0364Conductor shape
    • H05K2201/0376Flush conductors, i.e. flush with the surface of the printed circuit
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09009Substrate related
    • H05K2201/09036Recesses or grooves in insulating substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09009Substrate related
    • H05K2201/09118Moulded substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/09563Metal filled via
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2072Anchoring, i.e. one structure gripping into another
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03Metal processing
    • H05K2203/0353Making conductive layer thin, e.g. by etching
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703Plating
    • H05K2203/0723Electroplating, e.g. finish plating

Abstract

The invention relates to a method for producing electroconductive structures. An electrically isolating substrate (101) is produced or prepared in such a way that it comprises a surface having cavities at the sites where the electroconductive structures are to be formed. At least some of said cavities have a cross-section which is perpendicular to a surface of the substrate (101) and in which the aspect ratio (the ratio between the depth (t) and the width (b) of the structures) is between 1:5 and 5:1, for example at least 2:3. The surface of the substrate is provided with an electroconductive layer which is thin in comparison to the characteristic dimensions of the cavities. The surface of the substrate is then galvanised until said cavities are full.

Description

METHOD FOR PRODUCING ELECTRIC CONDUCTIVE STRUCTURES

The invention is concerned with the filling of recesses in plastics with metal for technical purposes. A method for filling recesses in plastics have uses in the field of manufacture of electrical connection elements, for example. Printed circuit boards, and flexible printed circuit boards, high-density interconnects, ball grid array (BGA) substrates, Chip Scale Packages (CSP), Multi-chip Module (MCM) substrates etc .. They can also be used for semiconductor devices, other elements such as micro-planar coils, micro relays, etc.

In particular, the invention relates to a method according to the first claim. Also the subject of this patent application include a connection element and a semi-finished product according to the further independent claims.

The ever continuing miniaturization in the field of micro-electronics also has an effect on the production of electrical connecting elements, in particular printed circuit boards, etc. interconnects. It exists in many applications, the need to replace the conventional printed circuit board manufacturing step through new methods. The conventional production of circuit structures based on photochemical process and that the mechanical drilling of through holes. More recent approaches (this microperforation. See international Publication WO 00/13062) comprise the boring of small holes by means of lasers or by plasma etching or by mechanical pressing in perforating tools in printed circuit board material.

During the drilling of micro holes is increasingly carried out with new, appropriate to the current requirements methods, the structuring of conductor tracks is still performed with the proven itself method of photo-structuring. But this involves a large number of manufacturing steps, including exposure, development and stripping of photoresist. It is thus relatively complex and includes by the large number of chemical process steps also umweltschutzliche disadvantages.

In contrast to conventional methods in the U.S. Patent 6,005,198 a process for the production of circuit boards is described which provides, inter alia, the simultaneous pressing of U-shaped grooves and of cup-shaped recesses by an embossing tool in an insulating and preferably thermoset substrate. For the formation of blind holes for electrical connection of two printed circuit layers of the cup-shaped depressions material must then still be chemically or mechanically removed. Then the channels and the wells are metallized. This is done for example., By forming a conductive paste is pressed with a rubber roller to the wells. Alternatively, also coated the entire substrate and then insulating material (etching resist) may be incorporated with a rubber roller to the wells. In a subsequent etching process because the etch resist in the presence of the recesses metal layer is protected. By this process, some processing steps are saved. The procedure requires but still several wet-chemical processes. Due to the necessary for the operability of the process relatively wide U-shape of the recesses also are limits to the miniaturization. Moreover, the conductor tracks by design either relatively little conductive, curable paste ( "Conductive ink") or they are comparatively thin. For this reason, the achievable reliability and transmitted by the conductor tracks performance limits. The method has in practice proved to be not very effective because the impressions of the conductor pastes and the etch resist is always accompanied by smearing these materials on the remaining surface. however, the surface must be absolutely free of coatings and clean, with the result that this mechanically after the coating process and curing must be sanded.

In US Patent 6,035,527 a novel method for producing printed circuit board is disclosed. In a first step in a substrate recesses are formed for interconnects. Subsequently, a homogeneous deposition of conductive material is effected for example. By a chemical vapor Deposition method. Subsequently, conductive material is removed, whereby remaining in the wells some conductor material forming conductor tracks.

In US Patent 4,651,417 a circuit board manufacturing method is described in which a substrate recesses taught mechanically to the conductor tracks. Thereafter, the substrate is homogeneously coated with material, for which a vacuum deposition process, namely a "magnetically enhanced sputtering" method is used. Finally, the conductor material is ground again by the substrate surface, remaining in the wells conductor material and forming the conductor tracks. When the do not satisfy achieved layer thickness, can not material to be electrodeposited in addition. in the US Patent 4,912,844 a process for circuit board manufacture is described, according to which channels for interconnects pressed into a substrate, and then filled with solder.

British Laid-Open Publication 2212331 and Japanese Patent Application 11 146698 each show a method for manufacturing of printed circuit boards made of plastic, where a pattern of depressions pressed into the deformable plastic material and then a conductive paste is pressed into the recesses.

All of these approaches show that the mechanical Teach of interconnect structures as an alternative to the dominant application in the photochemical process the experts busy for quite some time and stimulates. Nevertheless, none of these methods has prevailed until now. Reasons for this include the following:

- Practically all of the methods described above require that in a process step conductor material or semiconductor material residues are mechanically removed from lying between the conductor tracks surfaces. but this is not suitable for very fine conductor structures. As alternatives, at least one of the aforementioned documents are called the selective removal of material from the surfaces by means of laser ablation. As a highly sequential process but this is not economical.

- Vacuum deposition (sputtering, CVD, vapor deposition) are very slow and costly processes. Also, the introduction of mechanical elastic conductor paste (with squeegee, etc.) has been found to be only suitable for mass production. The proposed approaches, it is hardly possible to simultaneously produce very fine conductor track structures and conductors with a relatively large conductivity. The interconnects in accordance with the approaches are all either very thin or limited in specific conductance (conductor paste ...)

The invention has the object to provide a method for preparing electrically conductive structures using recesses in a substrate. In this case, the method should allow the structures such as circuit traces and through holes can have the smallest possible lateral dimensions. Compared to the prior art, however, the reliability and the performance of the structures must not be smaller. In conducting paths, therefore, the requirement that, in comparison to existing systems with respect to the surface less flat sectional portions, ie, a sufficiently large depth should have in the substrate. Follows The manufacturing process should be realized economically and based on existing technology equipment.

A method having these properties is provided by the invention are available, as defined in the claims.

The process is characterized essentially by the fact that depressions are taught for conductor patterns and galvanically filled. In a subsequent step conductor material is optionally removed from the lying between the conductor tracks sites. Galvanic processes are fast and efficient. The electroplated conductor structures can be, for example made of copper. the material of the structures obtained has a high specific conductivity. Nevertheless, the galvanic filling of interconnect structures has never been considered. A major reason for this is shown in the figure lb. The Figure shows the so-called. "Voids" formation. The lines 41 'show the profile of the surface at various amounts deposited material. Since the conductive material 103 preferably "in the plating on the coated substrate 101" at corners and hardly accumulates in wells to form a kind of cavity ( "shrink") 111 ', when the ratio between the width and depth of the to be replenished depression is small. Therefore, were wells in which the aspect ratio of greater than 1: 3 or 1: 3, 1: 2 or even the second one or more, not been considered for the galvanic filling into consideration when the structures to prevent the voids formation but very be selected flat, the miniaturization limits undesirably; also it is then difficult to remove conductive material in the areas between the conductor patterns, without the conductor material itself is completely removed from the conductor structures, the filling of very flat structures according to the state. art is illustrated with reference to FIG la. In the figure, a typical substrate shape is shown 101 ', which is a e having thin coating, and in which a conductor layer was electroplated 103 '. The lines 41 'shown show the course of the surface of the conductor material at different amounts of applied material. Even with relatively large layer thicknesses are depressions in the substrate on the surface still visible.

One approach to the prevention of the "shrink" formation is the "pulse-plating" or the so-called. "Reverse-pulse plating" process. According to this latter method, the current is repeatedly reversed, resulting in that material alternately to will be eliminated, the substrate and removed again. this can be avoided in the best case a "bubble cavity" formation when the aspect ratio is not too large. but the expenditure on equipment to be used and the energy are major disadvantages.

The US Patent 6,211,071 deals without concrete details with the conventional galvanic filling of structures with a characteristic Grosse of 2 microns or less for the manufacture of integrated circuits. It made no statements about whether "pulse plating" or "reverse-pulse plating ', etc. is used. In order to prevent the "voids" formation is proposed therein that the edges of the recesses are chamfered, whereby a larger aspect ratio can be achieved. But is disadvantageous among other things that yet again much area by the chamfers (conductor width) is claimed. The production the bevels of production engineering not easy and would be transferred only with great effort on circuit boards. in addition are the dimensions in the range of 0.1 microns. this in electrochemical and chemical processes dominate in these "nanostructures" diffusion and not, as with microstructures with which the invention is concerned mainly convection (flow). Next, the wafer according to the teaching of this document must be planarized chemical mechanical after filling.

The inventive method is based on the realization that it is possible to wells with steep ( "vertical" or substantially parallel) walls, with aspect ratios of 1: 5 to 5: 1 or more, and having dimensions of less than about 10 .mu.m to several 100 microns galvanically fill. the finding that the galvanic filling of channel-shaped in essence, ie elongated recesses is possible with such aspect ratios, is surprising. the relationship between the structure depth and total deposited in the plating material may be surprisingly low. A important finding, the use of copper or other electrolytes, such as are used in decorative electroplating. It surprisingly, it has been found that such electrolytes are suitable in an excellent manner for the filling of void-free recesses for forming conductor structures.

In decorative electroplating a bright and often smooth surface is sought by electroplating, usually with the lowest possible cost. Especially decorative effect, for example. Nickel, chromium or silver. Frequently, however, deposited on a surface prior to the application of these metals copper. Acid copper electrolytes are inexpensive and have high deposition rates. By suitable organic additives may be caused to scratches etc. leveled also the effect. The invention makes use of this effect.

The inventive method is essentially characterized by the fact that the recesses in a electrically insulating substrate after coating with a first conductive layer ( "seed layer") are completely galvanically filled and free of voids The recesses have an aspect ratio of 1:. 5 to 5 : 1, preferably between 2; 3 and 2.5: 1, a width of between 5 microns and 100 microns more preferably between 10 microns and 500 microns and, for example between 15 microns and 300 microns..

According to a first preferred embodiment is carried out applying the first conductive layer surface on the whole with the conductor pattern to be provided the substrate surface. The filling is then carried out by the whole substrate is electroplated with conductive material to grow until the recesses are filled with conductor material. It attaches also to the lying between the conductor structures surfaces conductor material. Therefore, after filling a re-wet chemical what is caused by removal of conductor material is performed until the surfaces are free of a conductor coating again.

According to one embodiment it is assumed that a substrate which has been so cast by means of a suitable form or injected in that the recesses are formed during casting or spraying.

The substrate may have been formed as a thermoset and hardened on a mold which has recesses corresponding elevations.

A further embodiment provides that the substrate has been generated from a precursor having a flat surface. The wells are taught by laser ablation, by (mechanical) milling or drilling using a micro tool through platisches molding ( "stamping"), etc..

The respective depression forming step may have been followed by a wet chemical or subsequent cleaning by a plasma cleaning step.

A further possibility is that the depressions photochemically, or with a conventional LIGA (Rönten lithography, electroplating, and molding) process (or the like), etc. are taught. The wells may also have been produced by means of plasma ablation, using an appropriate mask or protective layer. The conductor patterns, which have been produced by filling depressions can fulfill various functions. They can serve as conventional conductors or contacts between different conductive layers in electrical connection elements (printed circuit boards, HDIs etc.). They can also form contact surfaces act as impedances or the generation of specific electric and / or magnetic fields serve etc.

So that the surface portions located between the conductor patterns are free from conductor material, is then removed again on the filling of the depressions conductor material. This is preferably done again by wet chemistry in a conventional way, it is a major achievement of the invention that it is possible that the ablated conductive material layers -. In the context of this specification is the talk of the, residual layer thickness' - thin in comparison to the dimensions of the structures. This makes the galvanic filling and the ablating cost-effective and environmentally friendly compared to the prior art.

It has been found that according to one embodiment of the invention, a residual layer thickness of between 2 and 30 microns or can be obtained from 2 to 10 microns even if the depth and width of the filled structures 20 to 50 microns moves in the area, wherein after electroplating step, the surface is substantially smooth as glass flat or even - a very stunning result.

The aspect ratio (the ratio of depth to width) is as mentioned between 1: 5 and 5: 1, preferably between 1: 2 and 3: 1, particularly preferably between 2: 3 and 2.5: 1 for some applications at least 1 : 1 or at least 3: 2nd The inventive method is surprisingly simple and very quickly and economically. In addition, the fact affects the attractiveness of the process is positive, that acidic copper electrolyte solutions (dekorativ-) galvanic applications on the market are available at low cost as a mass product.

It should also be briefly noted here that a copper electrolyte from the decorative plating is used with appropriate additives according to a preferred and important embodiment of the galvanic filling the wells. Of course, the method is also applicable to other electrolytes from the coating technique, which contain additives that have a smoothing effect or einebnend.

The invention allows easy optimization of interconnect cross-sections in elements of connection. However, the conductor paths may, for example, have a substantially rectangular cross-section, which here has a much more favorable compared to the prior art aspect ratio.

In contrast to printed circuit boards according to the prior art, the invention also permits readily conductor tracks of different thickness to be produced. It can be produced, for example. Power traces and signal traces on the same printed circuit board and in a processing step.

The electrolyte is an aqueous solution and has at least three groups of components:

A. A transition metal or noble metal salt, eg., A copper sulfate, copper fluoroborate, copper acetate, copper nitrate, copper cyanide, etc., acid, eg. Sulfuric acid, a sulfonic acid, fluoroboric acid, sulfamic acid, hydrochloric acid, etc.

C. Organic additives such as, sulfur-containing aliphatic propanesulfonic acid derivatives, thiourea and derivatives, Dithioalkylsäurederivate, orthophosphoric acid, thiophosphoric acid esters, aromatic sulfur compounds, gelatin, molasses, phenazonium derivatives, polyalkylenglycol ether, formaldehyde, dithiocarbonates, mercapto, Dithiocarbamylverbindungen, B enzothiazolyl compounds, ethylene amine compounds, Methylendisulf id-compounds, succinic acid compounds, Sulfobernsteinsäureverbindungen.

The electrolyte may further comprise a buffering agent, an alkali or alkaline earth metal salt, and / or other organic or inorganic additives (e.g. NaCl.).

In more embodiments of the invention will be described in more detail with reference to drawings. In the drawings:

Figures 2a, 2b and 3 is a very schematic representation of the inventive approach, a cross-section perpendicular with reference to

Substrate surface,

4 schematically shows a plan view of a cut along a horizontal plane container for carrying out the electroplating process step as a batch process,

- Figures 4a and 4b details of Figure 4, Figure 4c shows a vertical section through the arrangement of Figure 4,

Figure 5 very schematically an example of an arrangement for carrying out the galvanic coating / filling as a continuous process,

6 shows a diagram for the electrolyte circuit according to a particular variant,

Figures 7 to 10 schematically illustrates a selection of methods for Teach of recesses in the electrically insulating plates,

Figures 11a, 11b and 11c show sections through a portion of a circuit board during various stages in the manufacturing process,

- Figures 12a, 12b and 12c show sections through a portion of an embodiment of the inventive electrical connection element during various stages of manufacture,

Figures 13a, 13b and 13c show sections through a portion of a further embodiment of the inventive electrical connection element during various stages of manufacturing.

In Figures 2a and 2b, a substrate 101 is shown with recesses which are filled according to the embodiment of the invention. In a first step, a coating with a thin conductor layer is applied to the substrate one hundred and first "Thin" in this context means an in comparison with the characteristic dimensions of the recesses small thickness, for example. About 50-500 nm, 100-300 nm, 150-250 nm, etc. Thus, for example, between one thousandth and several hundredths of the width of a typical well. The application can be done for example in a vacuum chamber by sputtering. other methods such as chemical Vapor deposition (CVD), thermal evaporation, anodic deposition, simple, wet chemical deposition or other chemical or physical methods are possible. as the coating material is preferably copper is used, but other conductive materials such as silver, chromium, titanium, etc. are possible. In certain polymeric materials, copper may be directly applied without any problems with the adhesion strength may occur. In other cases, so-called adhesive layers of chromium, titanium or tungsten must first deposited be. In a second step is usually Ku pfer applied. In such a case continues. the thin conductive layer so of two or possibly more metallic layers together.

Subsequently, the wells are galvanically filled. The lines 41 provide thereby the surface of the conductor layer 103 during various stages of electroplating. As is clear from the figure, very quickly reaches a flat surface. The dashed line in the figures represent the surface plane of the substrate. The Great b and t represent width, respectively depth of the recess. In addition to the illustrated in the Figures, approximately rectangular or U-shaped cross-sections, any other, beibringbare with a die cross-sections for the wells are conceivable.

also shown in the figures is the residual thickness r, ie the thickness of the deposited material at the locations of the surface to which the end or intermediate product to be free of conductive material. It has been shown that depending on the electrolyte and the electroplating process, the remaining layer thickness, ideally between 10 μ m and 30 microns, between 10 μ m and 20 microns or even between 10 μ m and hold 15 microns can. This applies in a broad range of dimensions of the recesses of between 20 μ m and 50 microns, practically independent of the size of the recesses. Often can the condition r <t, meet in most cases r <2t problems.

When filling is no "reverse pulse plating" is used for the electroplating, ie electroplating, for example. Used, that the polarity is not, or when galvanizing eg. More than twice reversed. The materials used include copper, but in principle also other conductor materials in question, for example. Silver. in the electroplating step will be discussed in more detail below. Following the processing step, the substrate layer has a filling the depressions and furthermore the entire substrate surface covering plating on.

In a further step according to Figure 3, the plating is removed until the conductor material 103 'only and is the locations available in which it is provided, thus, for example. In recesses for interconnects, via holes and contact points. The removal can be done by wet chemical etching. This can be a conventional type, for example. In the chemical bath or by spraying with an etching solution happen. Alternatively, to etch but other removal methods can be used, for example. Mechanical removal methods such Feinschleifen- "overlap" or other chemical or physical removal methods.

Galvanizing or electroplating with copper according to the embodiment described herein, the invention may be in a device according to the figures 4 and 4c are performed. At this point, a batch process is described where a sample is introduced into an electrolytic cell, processed, and is subsequently removed from the cell. Figure 4 schematically shows a top view of a device for electroplating in a vertical arrangement. Figure 4c shows a section along the line CC of Figure 4. The apparatus comprises a container 51 in which peripherally two anode rods 53 and centrally a cathode rod are attached 55th The cathode rod 56a is used for holding and contacting a steel plate 56 shown in FIG 4a in front view and in a reduced scale with an opening. The opening 56a is provided with a clamping device 56b, which serves to hold the coated substrate. Further, a diaphragm 57 and a shutter 59 are provided. The diaphragm 57 serves to ensure that no anode sludge 60 in the area surrounding the cathode electrolyte device. The aperture serves to laterally delimited shielding currents or electrical fields (see Figure 4b). Next as perforated dielectric tube formed means 61 are provided, through which the necessary acidic copper electrolyte for each air injection takes place. In addition, not yet drawn pump and filter means are provided through which the electrolyte discharged, filtered, and is supplied to the container. The electrolyte circulation caused by this means is, for example, 3 to 5 times the electrolyte volume per hour.

Essential that are filled -free in the plating process step, wells "voids" having a as explained above, relatively large aspect ratio, the composition of the electrolyte.

It has been shown that the method of the conventional electroplating for decorative purposes - with appropriate adjustments - can be used for this purpose. Such procedures have not been for

Use in printed circuit board technology (or for application to electrical connectors in general) considered. They have been used exclusively to improve surface gloss (decorative). For the growth of material on surfaces with recesses, generally of structured surfaces or, more generally, for the functional electroplating they have not been considered.

The electrolyte has according to a first embodiment, the following components: sulfuric acid (H 2 SO 4): 10-200 g / l of copper sulfate (CuSO 4 x 5 H 2 O): 50-500 g / L sodium chloride (NaCl): 10-250 mg / L, and the organic additives:

HSO C-WL base gloss of the company HSO in Solingen, Germany: 0.5-5 mL / L HSO C-WL gloss carrier: 0.5-5 mL / L HSO C-WL Brightener 0.05-2 mL / L

Particularly advantageously, the results are the following parameters:

Sulfuric acid 45-70 g / L, copper sulfate 200-230 g / L, sodium chloride, 100-190 mg / L, HSO C-WL base gloss 2.2 to 4.2 mL / L, HSO C-WL gloss carrier 1.6-2 , 8 mL / L, HSO C-WL gloss addition of 0.15 to 0.9 mL / L.

Optimum results are obtained with 45-60g / L sulfuric acid, 210-230 g / L copper sulfate, 140-170 mg / L sodium chloride, 2.6-3.8 mL / L HSO C-WL base gloss, 1, 7-2, 5 mL / L HSO C-WL gloss substrate and 0.2-0.6 mL / L HSO C-WL gloss addition. According to a second embodiment are used for the inorganic components the same compositions as for the first embodiment: sulfuric acid (H 2 SO 4): 10-200 g / L, preferably 45-70 g / L and, for example 45-60 g / L copper sulfate. (CuSO 4 x 5 H 2 O): 50-500 g / L, preferably 200-230 g / L and, for example 210-230 g / L.

Sodium chloride (NaCl): 10-250 mg / L, preferably 100-190 mg / L and, for example 140-.

170 mg / L. The organic components are provided, but in the (conventional decorative electroplating) HSO C-OF-process of the Fa. Schmidt in Solingen (DE).

A third embodiment:

- copper sulfate (CuSO 4 x 5 H 2 O): 50-500 g / L, preferably 200-230 g / L and, for example 210-230 g / L..

- sulfuric acid (H 2 SO 4): 10-200 g / L, preferably 45-70 g / L and, for example 50 to 60 g / L.

- 50-100 mg / L, preferably 75-90 mg / L chloride ions

Organic components: Novostar-ER Enthone OMI in Germany - batch solution 1-6 mL / L, preferably 1.5-5 mL / L and, for example 2-4.5 mL / L;. Leveler 0.05-1.0 mL / L, preferably 0.1-0.7 mL / L and, for example, 0.2-0.5 mL / L, gloss carrier 0.05-1.0 mL / L, preferably 0, 2 to 1.0 mL / L and example. 0.3-0.8 mL / L.

A fourth embodiment:

the "Copper Gleam BL" method of global Shipley is used (headquarters in Marlborough, MA 01752, USA).:

Copper sulphate: 50-500 g / L, preferably 170-210 g / L, for example 190-205 g / L, Schwefelsäufre. 10-200 g / L, preferably 30-80 g / L, for example 30-50 g / cc. L,

Chloride ion. 50-150 mg / L, preferably 70-120 mg / L, for example 80-100 mg / L.

Organic components:

Carrier Copper Gleam BL: 1-10 mL / L, preferably 2.5-5.0 ml / L, for example 2,8-4.0 mL / L..

Leveler Copper Gleam BL: 1-10 mL / L, preferably 1.5 ml / L, for example 1,5-3.0 mL / L..

The following procedure can be used:

1. Cleaning in an acidic solution. 2. Rinse in deionized water

3. Pickling in an acidic solution (eg. In sulfuric acid)

4. Galvanic building in a copper electrolyte,

5. Rinse in deionized water

6. drying.

The following procedure can be used to set a copper electrolyte:

1. A properly cleaned electrolytic tub is filled up to 70% of the final volume with deionized water.

2. Inorganic salts such as copper sulfate are added and residue released. Alternatively, a highly concentrated solution of the salts oriented can be used. When copper sulfate, a solution of 300 g / L of copper sulfate can be used, for example..

3. careful addition of sulfuric acid and hydrochloric acid or the sodium chloride with vigorous stirring, followed by cooling the solution to room temperature.

4. After cooling to room temperature can be up to 100% of the total volume with deionized water. After extensive mixing of the electrolyte, an analysis of the inorganic components (Cu, sulfuric acid, chloride) are performed. 5. Incorporation of the electrolyte at a current density of 1-2 A / dm 2, during a few hours.

6. Add the requisite amounts of organic additives and re-incorporation of the electrolyte at 1-2 A / dm 2, during a few hours.

7. Analysis of the organic additives of corresponding methods and possibly supplementing the missing quantities.

8. The electrolyte is now ready for use.

In the figure 5 shows a device for carrying out the embodiment of the invention the galvanic filling is also shown as a continuous process. is shown quite schematically a horizontal arrangement. But there are also, especially in large installations, complicated arrangements and pulleys, etc. conceivable. In this embodiment, as a continuous process do not support the coated substrate is required. The functioning as a cathode substrate 1 (with coating) is, for example, as described above, formed as a flexible foil and is tensioned by rollers. It is, for example, moves during the whole process and pulled in a horizontal direction through the electrolyte container. The anodes 53 'are mounted above and below or on both sides of the substrate. The device has Lufteinströmmittel and also depending on the diaphragms and aperture, which should not be described here again. In addition, not shown nozzles for the continuous generation of a flow of electrolyte are provided. By this flow - in the figure indicated by arrows - it is prevented that the electrolyte depleted with time in the vicinity of the cathode locally.

A diagram of a variant for carrying out the inventive method is shown in FIG. 6 In this variant, the copper deposition process is carried out on the coated substrate in an electrolytic cell 51 ", which from a container 63" is separated, is brought into which copper from the solid state into the electrolyte in solution. There takes place a continuous circulation of electrolyte, depleted electrolyte from the electrolysis' cell 51 is transported from the container into the electrolytic cell "in the container 63" and enriched with copper electrolyte.

To generate the example. Channel-shaped depressions for the conductor structures there are many known and new opportunities. Reference to the figures 7 to 10 a selection from the various options is shown schematically.

The substrate 1 of Figure 7 is deformed by an embossing step by an embossing tool 21 plastically, so that the depressions are formed. It has been shown that thermoplastics and thermosets exist which are suitable in an excellent manner for the minting of PCB substrates. Examples of suitable piatisch deformable materials are liquid crystal polymers (liquid crystal polymers, LCPs). Other possibilities are polysulfones, epoxy resins, which are deformable above the glass transition temperature, certain polyester (PEEK), polycarbonate, etc. The embossing step can be carried out under protective gas in a vacuum chamber or in an atmosphere containing oxygen or, for example.. According to FIG 8, the substrate also by injection molding in molds 23, 25 are manufactured which have elevations. In the figure, an injection passage is schematically represented 27; the air can escape through the separation level 29th

By Figure 9 it is indicated that the recesses can be made in substrate 1 by laser ablation. A laser light source 31 is indicated very schematically in the figure.

According to FIG 10, the substrate is in a first step with a patterned resist layer 33rd The structuring takes place, eg. In a conventional manner. Subsequently, the wells are taught wet-chemically or by etching.

The inventive method is particularly suitable for the production of fine structures with high aspect ratios between 1: 3 suitable, since the depth of the channels is limited by the thickness of the dielectric used: 5 and 3: 1 or>. 2 Since the thickness of, for example, in the range of 10 -. Is 200 micrometers, the conductor conduits have usually widths between 5 or 10 and a maximum of some 100 microns. In PCB applications specially fine conductor lines are therefore very simple and economical to manufacture. However, larger covered with metal surfaces are needed in virtually all applications. So the pads for the relatively large on the circuit board components to be soldered mostly and also the power supply conductors (Vcc and GND), for example, often have to be carried out extensively. These areas would after plating have too low a copper layer thickness, and after thinning the copper, the copper would be etched away in these two-dimensional regions. Figures 11a, 11b and 11 c show this in schematic form. The Figure 12 shows a substrate 201 after the embossing step. In the figure, the same substrate 12b is shown, wherein it is provided by the coating and the electroplating with a copper layer 203rd After the etching back as shown in FIG 12c remains only in the vicinity of stages as well as in the depressions copper 203 'back.

The embossing step may, alternatively, to press against each other be effected by two dies by embossing via rotating rolls ( "roll embossing").

The Nachreinigungs- or post-treatment step occurs for example. With plasma etching. Alternatively, a wet chemical process would be conceivable.

So far, only flat structures have been considered for the galvanic filling with conductive material. This is due, among other things, that the material naturally there accumulates in electroplating, where the electric fields are large, ie preferably at corners and edges. The here to be described embodiment of the invention is based but that conductor tracks are pre-formed and filled up, which have a cross section in which the aspect ratio as the ratio of depth to width of at least 1: 1 or more: 2 and for example, approximately. 1

In order to produce these large-scale structures with the process of this invention can meet various design measures:

The trainees as the contact surface area is screened into fine structures. This can be accomplished by parallel or intersecting fine channels with an optimum for the process of this invention aspect ratio. In such a case very good power planes or umbrella levels also can be made because they are carried out in conventional applications usually screened. However, if pads are made for soldering, the gridded area would not allow good soldering quality and the process must be modified so that closed soldering surfaces can be formed.

One possibility is shown in Figures 12a, 12b and 12c, where an electric connection member after the embossing step, after the electroplating step or after the etching back is prepared analogously to the figures 11a to 11c. It consists in aufzurastern the flat areas with very fine, the substrate 301 during the embossing step inflicted structures 301a. These structures have recesses and intermediate elevations. The depth of these structures, that is the recesses lies eg. At T / 2, if T represents the depth of the channel-shaped recesses for interconnects. This leads to a thickening of the copper in these artificial Feinstrasterzonen and after the thinning of the copper remains a closed residual layer 303a '. The screening can be done in vielfältigster manner, for example parallel conductor lines, intersecting conductor lines etc.

This effect can also be achieved by producing an embossing tool, which also includes larger, flat structures in addition to the fine structures with recesses and projections therebetween. A corresponding electrical connecting element is shown in Figures 13a, 13b and 13c during various stages of manufacturing. When galvanizing the fine structures are filled quickly and then the sheet-like structures are electroplated. This results in the sum of a slightly thicker layer of copper in these two-dimensional regions and after the thinning of the copper remains a closed residual layer 403a ', the protrusions are also covered by the etch back step or with copper. Rasterizing the planar areas for soldering areas has the advantage that the copper layer is mechanically firmly anchored on the dielectric, whereby the adhesive strength of the solder pads can be greatly increased the advantage.

The exemplary embodiments, with reference to which the invention has been explained above, are limited to the production of printed circuit boards. With knowledge of the invention, the skilled artisan will recognize that the invention is equally suitable for making other electrical interconnect components.

Further, in the above description, the simplicity sake, it was considered that the product of the process is a finished fastener. The skilled person will of course readily recognize that in addition to the steps described above still further processing steps for completing an electrical connection element can be undertaken. Further, the method for the production of semifinished products for further processing is suitable for a connecting element. Such a semi-finished product can be processed with other components to form a multi-layer electrical connection element, for example..

producible with the process of this invention electrical connection elements can have a variety of possible values ​​and are generally used in which electrical connecting elements come to be used in areas. In addition to conventional uses in which the circuit board is equipped with one another electrically coupled elements, a connecting element according to the invention, of course, is highly suitable for applications in which miniaturization is advanced. Next, reference is made also to uses in which the current carrying capacity of the conductor tracks is essential. Such uses are facilitated by the fact that, as described above, an inventive fastener tracks may have a specially favorable cross section.

A major finding of the invention is the possibility of galvanic filling of (micro- ,, ") structures with widths in the range between about 10 microns and 100 microns, in some cases, of significantly broader structures. Depending on the requirements, the aspect ratio and the remaining layer thickness, the inventive method can also be supplemented with method steps which are based on known methods for coating. The invention includes a method which includes a step or sub-step a) on a conventional PCB electroplating b) pulse-plating or reverse-pulse-plating, or c) based on a other conventional electroplating processes.

Countless other, based on the concept of the invention embodiments are conceivable. In particular, the electrolyte solutions listed above are only examples. There are known many other electrolyte solutions from the prior art.

Claims

PATENT CLAIMS
is produced or prepared 1. A method of producing electrically conductive structures, wherein an electrically insulating substrate (1) having a surface with recesses at the locations where the structures are to be built, at least some depressions perpendicular to a surface of the
The substrate having a cross section in which the aspect ratio, namely the ratio between the depth (t) and width (b) of the structures between 1: 5 and 5: 1, wherein the substrate surface at least at the points at which it
has depressions, is provided with an electrically conductive layer which is thin compared to the characteristic dimensions of the
Recesses, and wherein subsequently the surface of the substrate is plated until the cavities are filled and a substantially flat surface is formed.
2. The method according to claim 1, characterized in that the thin electrically conductive layer is deposited substantially on an entire surface of the substrate, and wherein subsequent to the plating of the substrate conductor material is removed until those between
Conductor structures lying locations of the substrate are free of a metal coating, which will not have a conductive surface.
3. The method according to claim 2, characterized in that the removal is carried out wet-chemically.
4. The method according to any one of the preceding claims, characterized in that the recesses, an exhibit perpendicular to a surface of the substrate a cross-section in which the aspect ratio, namely the ratio between the depth (t) and width (b) of the structures is at least 1: 1 and for example at least 3:. 2 and no more than 5: 1.
5. The method according to any one of the preceding claims, characterized in that the structures with recesses of a width (b) which is in the range between about 10 microns and 100 microns.
6. The method according to any one of the preceding claims, characterized in that the electrolytic water used for electroplating and at least the following three components:
- a transition metal or precious metal salt, for example, a copper sulfate, copper fluoroborate, copper acetate, copper nitrate, copper cyanide.
Acid, eg. Sulfuric acid, a sulfonic acid, fluoroboric acid, sulfamic acid, hydrochloric acid
Organic additives. sulfur-containing aliphatic propanesulfonic acid derivatives, thiourea and derivatives, Dithioalkylsäurederivate, orthophosphoric acid, thiophosphoric acid esters, aromatic
Sulfur compounds, gelatin, molasses, phenazonium derivatives,
Polyalkylenglycol ether, formaldehyde compounds, dithiocarbonates, mercapto, Dithiocarbamylverbindungen, Benzothiazolylverbindungen, ethylene amine compounds, Methylendisulfidverbindungen, succinic compounds Sulfobernsteinsäureverbindungen or other organic compounds.
7. The method according to claim 6 characterized in that the electrolyte 10- 200 g / L sulfuric acid, having 50-500 g / l of copper sulphate and 10-250 mg / L sodium chloride, and organic additives.
8. The method according to claim 7, characterized in that the electrolyte of 20- 100 g / L and preferably 45-70 g / L sulfuric acid, 180-280 g / L and preferably 200-230 g / L of copper sulphate as well as 100-190 mg / has L and preferably 140-170 mg / L sodium chloride.
9. Semi-finished products for use as a component of an electrical connection element or electrical connection element, produced by the method according to one of claims 1 to 8, characterized in that it comprises an insulating substrate (101) having recesses, wherein at least some of the recesses a in a surface the insulating layer perpendicular cross-section having, in which it applies a measured at the widest point, the width (b) of between 0.5 microns and 100 microns and an aspect ratio, namely a ratio between depth (t) and the width (b) of between 1: 1 are have and substantially completely filled with electrically-applied conductor material: 5 and 5. FIG.
10. precursor for use together with a wiring pattern by a method according to any one of claims 1 to 9, comprising an electrically insulating substrate having a surface which has depressions, at least some of the depressions have a cross section, in which it applies a measured at the widest point width (b) of between 0.5 μ m and 100 μ m and an aspect ratio, namely a ratio between depth (t) and the width (b) of between 1: 5 and 5: 1.
11. The use of an acidic aqueous electrolyte comprising a salt with a transition or noble metal, eg. Cu, Ni, Ag, Au, Pt, Pd, and with organic
Additives, and with the property that when it is applied in the electrolyte of dissolved metal from the electrolyte in a plating process on a surface with irregularities, such as scratches etc., the bumps are leveled when the average thickness of the deposited metal of the order of magnitude of the depth is uneven, for filling of cavities in a production process of electronic elements to conductor structures.
12. Use according to claim 11, characterized in that the salt is a copper salt.
13. Use according to claim 11 or 12, characterized in that the solution is such that trenches of a width and a depth of each of between 20 .mu.m and 50 .mu.m are galvanically filled once the thickness Sends
(R) of the residual layer of the deposited layer between the depressions a
Thickness of 10 to 30 microns, preferably 10 to 20 microns has been reached.
PCT/CH2002/000001 2000-01-04 2002-01-03 Method for producing electroconductive structures WO2002054840A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CHPCT/CH01/00004 2001-01-04
PCT/CH2001/000004 WO2001050825A1 (en) 2000-01-04 2001-01-04 Method, facility and device for producing an electrical connecting element, electrical connecting element and semi-finished product
CH1232/01 2001-07-04
CH12322001 2001-07-04

Applications Claiming Priority (3)

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US10/250,496 US20040060728A1 (en) 2001-01-04 2002-01-03 Method for producing electroconductive structures
JP2002555595A JP2005501394A (en) 2001-01-04 2002-01-03 The method for manufacturing a conductive structure
EP20020726979 EP1348320A1 (en) 2001-01-04 2002-01-03 Method for producing electroconductive structures

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