WO2002041371A1 - Structure semiconductrice contenant un materiau a constance dielectrique elevee - Google Patents

Structure semiconductrice contenant un materiau a constance dielectrique elevee Download PDF

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Publication number
WO2002041371A1
WO2002041371A1 PCT/US2001/031990 US0131990W WO0241371A1 WO 2002041371 A1 WO2002041371 A1 WO 2002041371A1 US 0131990 W US0131990 W US 0131990W WO 0241371 A1 WO0241371 A1 WO 0241371A1
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WO
WIPO (PCT)
Prior art keywords
layer
monocrystalline
growing
earth metal
alkali earth
Prior art date
Application number
PCT/US2001/031990
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English (en)
Inventor
Jamal Ramdani
Ravindranath Droopad
Lyndee Hilt
Jay Curless
Stefan Zollner
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Motorola, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola, Inc. filed Critical Motorola, Inc.
Priority to JP2002543681A priority Critical patent/JP2004514288A/ja
Priority to KR10-2003-7006563A priority patent/KR20030051820A/ko
Priority to EP01981536A priority patent/EP1338029A1/fr
Priority to AU2002213173A priority patent/AU2002213173A1/en
Publication of WO2002041371A1 publication Critical patent/WO2002041371A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer

Definitions

  • This invention relates generally to semiconductor structures and devices and to a method for their fabrication, and more specifically to semiconductor structures and devices and to the fabrication and use of semiconductor structures, devices, and integrated circuits that include a non-stoichiometric, high dielectric constant oxide to reduce leakage current density.
  • Epitaxial growth of single crystal oxide thin films on silicon is of great interest in numerous device applications, such as, for example, ferroelectric devices, nonvolatile high density memory devices, and next-generation MOS devices. Also, in the preparation of these films, it is pivotal to establish an ordered transition layer or buffer layer on the silicon surface for the subsequent growth of the single crystal oxides, such as, for example, perovskites. Some of these oxides, such as BaO and BaTi0 3, were formed on silicon
  • SrTi0 3 on silicon (100) using an SrO buffer layer has been accomplished. See, e.g., T. Tambo et al., Jpn. J. Appl. Phys., Vol. 37, p. 4454-4459 (1998).
  • the SrO buffer layer was thick (100 A), thereby limiting application for transistor films, and crystallinity was not maintained throughout the growth.
  • SrTi0 3 has been grown on silicon using thick oxide layers (60- 120 A) of SrO or TiO. See, e.g., B.K. Moon et al., Jpn. J. Appl. Phys., Vol. 33, p. 1472-1477 (1994). These thick buffer layers, however, would limit the application for transistors.
  • these types of oxide layers are fabricated using molecular oxygen and are formed thin ⁇ i.e., less than 50 A). Accordingly, a result is leaky films in which high electrical leakage is experienced due to oxygen deficiencies or vacancies. Furthermore, these films require a post-growth anneal in oxygen to reduce leakage current density across the oxide layer.
  • FIG. 1 illustrates schematically, in cross section, a semiconductor structure fabricated in accordance with one embodiment of the present invention
  • FIG. 2 illustrates schematically, in cross section, a semiconductor device structure fabricated in accordance with an alternative embodiment of the present invention
  • FIG. 3 illustrates schematically, in cross section, a structure in accordance with a further embodiment of the present invention
  • FIG. 4 illustrates schematically, in cross section, a semiconductor device structure fabricated in accordance with yet a further embodiment of the present invention
  • FIG. 5 illustrates schematically, in cross section, a semiconductor device structure fabricated in accordance with another embodiment of the present invention
  • the following example illustrates a process, in accordance with one embodiment of the invention, for fabricating such a semiconductor structure having a low leakage current density.
  • the process starts by providing a monocrystalline semiconductor substrate comprising, for example, silicon and/or germanium.
  • the semiconductor substrate is a silicon wafer having a (100) orientation.
  • the substrate may be oriented on axis or, at most, about 0.5° off axis.
  • At least a portion of the semiconductor substrate has a bare surface, although other portions of the substrate, as described below, may encompass other structures.
  • the term "bare" in this context means that the surface in the portion of the substrate has been cleaned to remove any oxides, contaminants, or other foreign material.
  • bare silicon is highly reactive and readily forms a native oxide.
  • the term "bare" is intended to encompass such a native oxide.
  • a thin silicon oxide may also be intentionally grown on the semiconductor substrate, although such a grown oxide is not essential to the process in accordance with the invention.
  • the native oxide layer is first removed to expose the crystalline structure of the underlying substrate. The following process is generally carried out by molecular beam epitaxy (MBE), although other processes, such as those outlined below, may also be used in accordance with the present invention.
  • MBE molecular beam epitaxy
  • the native oxide can be removed by first thermally depositing a thin layer of strontium, barium, a combination of strontium and barium, or other alkali earth metals or combinations of alkali earth metals in an MBE apparatus.
  • strontium the substrate is then heated to a temperature of about 750° C to cause the strontium to react with the native silicon oxide layer.
  • the strontium serves to reduce the silicon oxide to leave a silicon oxide-free surface.
  • the resultant surface which exhibits an ordered 2x1 structure, includes strontium, oxygen, and silicon.
  • the ordered 2x1 structure forms a template for the ordered growth of an overlying layer of a monocrystalline oxide.
  • the template provides the necessary chemical and physical properties to nucleate the crystalline growth of an overlying layer.
  • the native silicon oxide can be converted and the substrate surface can be prepared for the growth of a monocrystalline oxide layer by depositing an alkali earth metal oxide, such as strontium oxide, strontium barium oxide, or barium oxide, onto the substrate surface by MBE at a low temperature and by subsequently heating the structure to a temperature of about 750°C. At this temperature a solid state reaction takes place between the strontium oxide and the native silicon oxide causing the reduction of the native silicon oxide and leaving an ordered 2x1 structure with strontium, oxygen, and silicon remaining on the substrate surface.
  • an alkali earth metal oxide such as strontium oxide, strontium barium oxide, or barium oxide
  • the substrate is cooled to a temperature in the range of about 200-800°C and a layer of strontium titanate is grown on the template layer by molecular beam epitaxy.
  • the MBE process is initiated by opening shutters in the MBE apparatus to expose strontium, titanium and oxygen sources.
  • the ratio of strontium and titanium is approximately 1:1.
  • the partial pressure of oxygen is initially set at a minimum value to grow stoichiometric strontium titanate at a growth rate of about 0.3-0.5 nm per minute. After initiating growth of the strontium titanate, the partial pressure of oxygen is increased above the initial minimum value.
  • the process described above illustrates a process for forming a semiconductor structure including a silicon substrate and an overlying oxide layer by the process of molecular beam epitaxy.
  • the process can also be carried out by the process of chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), migration enhanced epitaxy (MEE), atomic layer epitaxy (ALE), physical vapor deposition (PVD), chemical solution deposition (CSD), pulsed laser deposition (PLD), or the like.
  • CVD chemical vapor deposition
  • MOCVD metal organic chemical vapor deposition
  • MEE migration enhanced epitaxy
  • ALE atomic layer epitaxy
  • PVD physical vapor deposition
  • CSSD chemical solution deposition
  • PLD pulsed laser deposition
  • alkaline earth metal titanates, zirconates, hafnates, tantalates, vanadates, ruthenates, and niobates such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide can also be grown.
  • FIG. 1 illustrates schematically, in cross section, a structure 100 in accordance with one embodiment of the present invention.
  • Structure 100 may be a device such as, for example, a gate dielectric component for a MOS device or any high dielectric constant device.
  • Structure 100 includes a monocrystalline semiconductor substrate 101.
  • Substrate 101 may comprise any suitable monocrystalline semiconductor material, such as, for example, silicon (Si), germanium (Ge), silicon germanium (Si-Ge), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAIAs), aluminum gallium arsenide (AIGaAs), and indium gallium phosphide (InGaP).
  • substrate 101 comprises a monocrystalline silicon wafer.
  • a monocrystalline oxide layer 103 is formed overlying substrate 101.
  • monocrystalline oxide layer 103 is a monocrystalline oxide material selected for its crystalline compatibility with the underlying substrate and with the overlying compound semiconductor material in this embodiment, iayer 103 may comprise, for example, stoichiometric alkali earth metal titanate, such as barium titanate (BaTiOs), strontium titanate (SrTi0 3 ), or barium strontium titanate (Sr z Ba ⁇ - z Ti ⁇ 3, 0 ⁇ z ⁇ 1).
  • a stoichiometric alkali earth metal titanate is achieved where the ratio of alkali earth metal to titanium is 1 :1.
  • layer 103 is a layer of stoichiometric SrTi0 3 having a thickness of about 2 - 10 monolayers and preferably a thickness of about 5 monolayers.
  • monocrystalline oxide layer 104 is formed overlying layer 103.
  • monocrystalline oxide layer 104 is a monocrystalline oxide material selected for its crystalline compatibility with layer 103.
  • layer 104 may comprise, for example, non-stoichiometric alkali earth metal titanate, such as barium titanate, strontium titanate, or barium strontium titanate.
  • a non- stoichiometric alkali earth metal titanate is achieved where the ratio of alkali earth metal to titanium is greater than 1 :1 , and may be achieved by establishing different flux rates for the alkali earth metal and titanium during formation of the alkali earth metal titanate layer.
  • a non-stoichiometric alkali earth metal titanate will be formed having a ratio of alkali earth metal to titanium greater than 1 :1.
  • the ratio of alkali earth metal to titanium is less than or equal to about 1.8:1.
  • layer 104 is a layer of non-stoichiometric SrTi0 3 and can have a thickness of about 2 - 10 monolayers and preferably a thickness of about 5 monolayers.
  • the combined equivalent oxide thickness of layer 103 and 104 is less than or equal to about 1.5 nm.
  • a third monocrystalline oxide layer 105 is formed overlying layer 104.
  • Layer 105 may comprise, for example, stoichiometric alkali earth metal titanate, such as barium titanate (BaTi0 3 ), strontium titanate (SrTi0 3 ), or barium strontium titanate (Sr z Ba ⁇ - z Ti0 3 , 0 ⁇ z ⁇ 1).
  • layer 105 is a layer of stoichiometric SrTi0 3 and can have a thickness of about 2 - 10 monolayers and preferably a thickness of about 5 monolayers.
  • a conductive gate electrode (not shown) may be formed on layer 105 in accordance with techniques well known to those skilled in the art.
  • FIG. 2 illustrates schematically, in cross section, a semiconductor device structure 200 in accordance with another embodiment of the present invention.
  • Device structure 200 may be a device such as, for example, a MOS device or any high dielectric constant device.
  • Structure 200 includes a monocrystalline semiconductor substrate 201 , preferably a monocrystalline silicon wafer.
  • a monocrystalline oxide layer 203 is formed overlying substrate 201.
  • Monocrystalline oxide layer 203 is preferably a monocrystalline oxide material selected for its crystalline compatibility with the underlying substrate and with the overlying compound semiconductor material.
  • layer 203 may comprise, for example, non-stoichiometric alkali earth metal titanate, such as barium titanate (Ba x Ti 1 - x 0 3 ), strontium titanate (Sr x Ti ⁇ - 0 3 ), or barium strontium titanate ((SrzBa ⁇ xTi ⁇ Os, 0 ⁇ x ⁇ 1 , 0 ⁇ z ⁇ 1).
  • layer 203 is a layer of non- stoichio etric SrTi0 3 and can have a thickness of about 2 - 10 monolayers and preferably a thickness of about 5 monolayers.
  • An additional monocrystalline oxide layer 204 is formed overlying layer 203.
  • Monocrystalline oxide layer 204 is preferably a monocrystalline oxide material selected for its crystalline compatibility with layer 203.
  • layer 204 may comprise, for example, stoichiometric alkali earth metal titanate, such as barium titanate, strontium titanate, or barium strontium titanate.
  • layer 204 is a layer of stoichiometric SrTi0 3 and can have a thickness of about 2 - 10 monolayers and preferably a thickness of about 5 monolayers. In one aspect of this embodiment, layers 203 and 204 have a combined equivalent oxide thickness of less than or equal to about 1.5 nm.
  • layers 203 and 204 collectively comprise a gate dielectric for a high dielectric constant semiconductor device, such as a MOS device.
  • a conductive gate electrode 205 may be formed on layer 204 in accordance with techniques well known to those skilled in the art to complete the device structure. Processing may then continue in accordance with standard processing techniques to form a substantially complete integrated circuit incorporating a device structure of the present invention, such as that illustrated in FIG. 2.
  • FIG. 3 illustrates schematically, in cross section, a structure 300 in accordance with a further embodiment of the present invention.
  • Structure 300 may be a structure such as, for example, a gate dielectric component for a MOS device or any high dielectric constant device.
  • Structure 300 includes a monocrystalline semiconductor substrate 301 , preferably a monocrystalline silicon wafer.
  • a monocrystalline oxide layer 302 is formed overlying substrate 301.
  • monocrystalline oxide layer 302 is a monocrystalline oxide material selected for its crystalline compatibility with the underlying substrate and with the overlying compound semiconductor material.
  • layer 302 may comprise, for example, non-stoichiometric alkali earth metal titanate, such as barium titanate (Ba x Ti ⁇ - x 0 3 ), strontium titanate (Sr x Ti ⁇ - x 0 3 ), or barium strontium titanate ((Sr z Ba 1 - z ) ⁇ Ti ⁇ - x 0 3 , 0 ⁇ x ⁇ 1 , 0 ⁇ z ⁇ 1).
  • An additional monocrystalline oxide layer 303 is formed overlying layer 302.
  • Monocrystalline oxide layer 303 is preferably a monocrystalline oxide material selected for its crystalline compatibility with layer 302.
  • layer 303 may comprise, for example, stoichiometric alkali earth metal titanate, such as barium titanate, strontium titanate, or barium strontium titanate.
  • a plurality of alternating layers of non-stoichiometric alkali earth metal titanate and stoichiometric alkali earth metal titanate are formed overlying layer 303.
  • the stoichiometric/non-stoichiometric nature of layers 302, 303, and additional layers is not critical, so long as the layers alternate between non-stoichiometric and stoichiometric as the structure is formed.
  • a stoichiometric alkali earth metal titanate layer not be formed overlying another stoichiometric alkali earth metal titanate layer, and that a non-stoichiometric alkali earth metal titanate layer not be formed overlying another non-stoichiometric alkali earth metal titanate layer.
  • a third monocrystalline oxide layer 304 is formed overlying layer 303.
  • Layer 304 may comprise, for example, a non-stoichiometric alkali earth metal titanate.
  • a fourth monocrystalline oxide layer 305 is formed overlying layer 304.
  • Layer 305 may comprise, for example, a stoichiometric alkali earth metal titanate.
  • FIG. 4 illustrates schematically, in cross section, a semiconductor device structure 400 fabricated in accordance with one alternative embodiment of the present invention, wherein semiconductor device structure 400 comprises a MOS device.
  • Structure 400 includes a monocrystalline semiconductor substrate 401 , preferably a monocrystalline silicon wafer. Drain region 402 and source region 403 are formed in substrate 401 using techniques well known to those skilled in the art, such as, for example, ion implantation.
  • a channel region 408 is defined by drain region 402 and source region 403 as the portion of substrate 401 between regions 402 and 403.
  • a monocrystalline oxide layer 404 is formed overlying substrate 401 adjacent channel region 408.
  • Layer 404 is preferably a monocrystalline oxide material selected for its crystalline compatibility with the underlying substrate and with any overlying compound semiconductor material.
  • layer 404 may comprise, for example, stoichiometric alkali earth metal titanate, such as barium titanate (BaTi0 3 ), strontium titanate (SrTi0 3 ), or barium strontium titanate (Sr z Ba- ⁇ - z Ti0 3 , 0 ⁇ x ⁇ 1 , 0 ⁇ z ⁇ 1).
  • layer 404 is a layer of stoichiometric SrTi0 3 having a thickness of about 2 - 10 monolayers and preferably a thickness of about 5 monolayers.
  • a second monocrystalline oxide layer 405 is formed overlying layer 404.
  • Layer 405 is preferably a monocrystalline oxide material selected for its crystalline compatibility with layer 404.
  • layer 405 may comprise, for example, non-stoichiometric alkali earth metal titanate, such as barium titanate, strontium titanate, or barium strontium titanate.
  • layer 405 is a layer of non-stoichiometric Sr x Ti ⁇ - x 0 3 , with 0 ⁇ x ⁇ 1 , having a thickness of about 2 - 10 monolayers and preferably a thickness of about 5 monolayers.
  • a third monocrystalline oxide layer 406 is formed overlying layer 405.
  • Layer 406 may comprise, for example, stoichiometric alkali earth metal titanate, such as barium titanate (BaTi0 3 ), strontium titanate (SrTi0 3 ), or barium strontium titanate (Sr z Ba ⁇ - z Ti0 3 , 0 ⁇ x ⁇ 1, 0 ⁇ z ⁇ 1).
  • layer 406 is a layer of stoichiometric SrTi0 3 having a thickness of about 2 - 10 monolayers and preferably a thickness of about 5 monolayers.
  • a conductive gate electrode 407 is then formed on layer 406 in accordance with techniques well known to those skilled in the art to complete the structure of the MOS device.
  • FIG. 5 illustrates schematically, in cross section, a semiconductor device structure 500 fabricated in accordance with a further embodiment of the present invention, wherein semiconductor device structure 500 comprises a MOS device.
  • Structure 500 includes a monocrystalline semiconductor substrate 501 , preferably a monocrystalline silicon wafer. Drain region 502 and source region 503 are formed in substrate 501 using techniques well known to those skilled in the art, such as, for example, ion implantation.
  • a channel region 510 is defined by drain region 502 and source region 503 as a portion of substrate 501 between regions 502 and 503.
  • a monocrystalline oxide layer 504 is formed overlying substrate 501.
  • layer 504 is a monocrystalline oxide material selected for its crystalline compatibility with the underlying substrate and with an overlying compound semiconductor material layer 505.
  • layer 504 may comprise, for example, an alkali earth metal titanate, an alkali earth metal hafnate, or an alkali earth metal zirconate.
  • layer 504 is a layer of (Ba,Sr)Ti0 3 having a thickness of about 2 - 10 monolayers.
  • Compound semiconductor layer 505 may comprise, for example, silicon germanium (Si-Ge), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAIAs), aluminum gallium arsenide (AIGaAs), or indium gallium phosphide (InGaP).
  • Si-Ge silicon germanium
  • GaAs gallium arsenide
  • InGaAs indium gallium arsenide
  • InAIAs indium aluminum arsenide
  • AIGaAs aluminum gallium arsenide
  • InGaP indium gallium phosphide
  • a monocrystalline oxide layer 506 is then formed overlying layer 505 and channel region 510.
  • Layer 506 is preferably a monocrystalline oxide material selected for its crystalline compatibility with layer 505.
  • layer 506 may comprise, for example, stoichiometric alkali earth metal titanate, such as barium titanate, strontium titanate, or barium strontium titanate.
  • layer 506 is a layer of stoichiometric SrTi0 3 having a thickness of about 5 monolayers.
  • a second monocrystalline oxide layer 507 is formed overlying layer 506.
  • Layer 507 may comprise, for example, a non-stoichiometric alkali earth metal titanate having a ratio of alkali earth metal to titanium of greater than 1 :1. In one embodiment, layer 507 is a layer of non-stoichiometric Sr x Ti- ⁇ - x 0 3 having a thickness of about 5 monolayers. Further, in accordance with this embodiment of the invention, a third monocrystalline oxide layer 508 is formed overlying layer 507. Layer 508 may comprise, for example, a stoichiometric alkali earth metal titanate. In one embodiment, layer 508 is a layer of stoichiometric SrTi0 3 having a thickness of about 5 monolayers.
  • layers 506, 507 and 508 exhibit a bandgap of greater than about 3.2 eV.
  • a conductive gate electrode 509 is then formed on layer 508 in accordance with techniques well known to those skilled in the art to complete the structure of the MOS device.
  • various layers of the semiconductor device may be formed using a variety of growth deposition methods, including, but not limited to molecular beam epitaxy (MBE), chemical beam epitaxy (CBE), metal-organic molecular beam epitaxy (MOMBE), ultra-high vacuum chemical vapor deposition (UHVCVD), physical vapor deposition (PVD), metal-organic chemical vapor deposition (MOCVD) or the like.
  • MBE molecular beam epitaxy
  • CBE chemical beam epitaxy
  • MOMBE metal-organic molecular beam epitaxy
  • UHVCVD ultra-high vacuum chemical vapor deposition
  • PVD physical vapor deposition
  • MOCVD metal-organic chemical vapor deposition

Abstract

L'invention concerne une structure semiconductrice (400) et un procédé permettant de former une structure semiconductrice contenant un matériau à constance diélectrique élevée composée d'un substrat semiconducteur (401) monocristallin, d'une ou de plusieurs couches d'un matériau stoechiométrique monocristallin à constance diélectrique élevée (404), et d'une ou de plusieurs couches d'un matériau non-stoechiométrique à constance diélectrique élevée (405). Le matériau à constance diélectrique élevée peut comprendre un titanate métallique terreux alcalin et monocristallin, tel que (Ba,Sr)TiO3. Les dispositifs semiconducteurs fabriqués selon le mode de réalisation décrit dans cette invention présentent une densité de courant de fuite réduite.
PCT/US2001/031990 2000-11-14 2001-10-15 Structure semiconductrice contenant un materiau a constance dielectrique elevee WO2002041371A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2002543681A JP2004514288A (ja) 2000-11-14 2001-10-15 高誘電率材料を含む半導体構造体
KR10-2003-7006563A KR20030051820A (ko) 2000-11-14 2001-10-15 고 유전 상수 재료를 가지는 반도체 구조체
EP01981536A EP1338029A1 (fr) 2000-11-14 2001-10-15 Structure semiconductrice contenant un materiau a constance dielectrique elevee
AU2002213173A AU2002213173A1 (en) 2000-11-14 2001-10-15 Semiconductor structure having high dielectric constant material

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US71242500A 2000-11-14 2000-11-14
US09/712,425 2000-11-14

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JP (1) JP2004514288A (fr)
KR (1) KR20030051820A (fr)
CN (1) CN1475027A (fr)
AU (1) AU2002213173A1 (fr)
TW (1) TW507317B (fr)
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US7678633B2 (en) 2005-11-24 2010-03-16 National Tsing Hua University Method for forming substrates for MOS transistor components and its products
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EP0957522A2 (fr) * 1998-05-13 1999-11-17 Matsushita Electric Industrial Co., Ltd. Dispositif de mémoire à semiconducteur et son procédé de fabrication
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EP0810666A1 (fr) * 1996-05-30 1997-12-03 Oki Electric Industry Co., Ltd. Cellule de mémoire semiconductrice non-volatile et son procédé de fabrication
EP0957522A2 (fr) * 1998-05-13 1999-11-17 Matsushita Electric Industrial Co., Ltd. Dispositif de mémoire à semiconducteur et son procédé de fabrication
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Publication number Priority date Publication date Assignee Title
WO2003063227A2 (fr) * 2002-01-22 2003-07-31 Massachusetts Institute Of Technology Procede de passivation de la surface d'un semi-conducteur iii-v
WO2003063227A3 (fr) * 2002-01-22 2004-04-15 Massachusetts Inst Technology Procede de passivation de la surface d'un semi-conducteur iii-v
US6933244B2 (en) 2002-01-22 2005-08-23 Massachusetts Institute Of Technology Method of fabrication for III-V semiconductor surface passivation
WO2004032242A1 (fr) * 2002-09-30 2004-04-15 Freescale Semiconductor, Inc. Structures de dispositif semi-conducteur utilisant des sulfures metalliques
US6791125B2 (en) 2002-09-30 2004-09-14 Freescale Semiconductor, Inc. Semiconductor device structures which utilize metal sulfides
US7678633B2 (en) 2005-11-24 2010-03-16 National Tsing Hua University Method for forming substrates for MOS transistor components and its products
EP2166562A3 (fr) * 2008-09-22 2010-08-04 Imec Procédé de formation par ALD d'un condensateur doté d'une couche diélectrique à base de dioxyde de titane de strontium/baryum et dispositif de mémoire comprenant un tel condensateur

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EP1338029A1 (fr) 2003-08-27
AU2002213173A1 (en) 2002-05-27
TW507317B (en) 2002-10-21
CN1475027A (zh) 2004-02-11
JP2004514288A (ja) 2004-05-13
KR20030051820A (ko) 2003-06-25

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