WO2002041123A2

WO2002041123A2 - Encryption system

Info

Publication number: WO2002041123A2
Application number: PCT/EP2001/012908
Authority: WO
Inventors: Heinicke Dietrich Dipl-Math
Original assignee: Secware Technologies Ag; Dipl.-Math. Heinicke, Dietrich
Priority date: 2000-11-17
Filing date: 2001-11-08
Publication date: 2002-05-23
Also published as: DE10056989A1; AU2002229540A1; WO2002041123A3

Abstract

The invention relates to an application-specific integrated circuit (ASIC) for encoding and decoding data streams by means of a CPU and optionally a co-processor and an encryption algorithm that is implemented in the hardware of the system. The aim of the invention is to provide a generic ASIC that is highly secure and that at the same time allows for a high data throughput. For the purpose of encoding and decoding data streams, the application-specific integrated circuit (ASIC) is therefore provided with a PCMCIA interface functionally linked with a PCMCIA card that is configured as a database memory holding code information.

Description

encryption system

The invention relates to an application-specific integrated circuit (ASIC) for encrypting and decrypting data streams with a CPU and possibly a coprocessor and an encryption algorithm implemented in hardware.

Such ASICs are known, for example, as a so-called clipper chip or as a further hardware-based encryption method in the form of the so-called Me chip from the Leipzig company ESD.

Two classes of cryptographic methods are currently used: symmetrical and asymmetrical.

The first class is called symmetrical because it uses the same key for encryption and decryption. The weak point of symmetric cryptography is the secure exchange of the shared secret key of both parties. No suitable way could be found for this. This task was first developed by developers; finally solved by using asymmetric cryptography. In this method, a key pair exists for each user, in which one key is provided for encryption (private or secret key) and the other for decryption (public key). Asymmetric cryptographic methods are based on mathematical problems that are not or only extremely difficult to calculate. This is why the asymmetrical methods have a significantly lower data throughput than comparable safe symmetrical methods. Execution times and security are in a tough competitive situation. Larger numbers correspond to higher security and lower data throughput. Processes are therefore required that are based on a lower one Guarantee a high level of security. This is particularly important if these methods are used on devices that have a low computing capacity or if a large number of signatures have to be stored in a very limited memory. (See Funkschau 2000, Issue 18, pp. 52-54)

The object of the invention is therefore to create a generic ASIC which has high security and at the same time guarantees high data throughput.

This object is achieved in a generic ASIC in that it has a PCMCIA interface with an active connection to a PCMCIA card (26) which is designed as a database memory of key information. A fast availability of many keys is required for server systems. Security requires that these are in the memory of the ASIC and are not accessible to the host system. So that these keys are not lost in the event of a system failure, the key database is saved on a PCMCIA card. In the event of a system failure, the card can be easily inserted into a new system, so that no complex recovery actions have to be carried out.

In a further embodiment, the

Invention provided that the ASIC has an RS232 interface. The RS232 interface enables key data stored on smart cards to be read directly into the ASIC. This is an essential point in the security concept, which prevents key data from being spied on by Trojans on the PC. There is no way to read the key data from the ASIC using a PC. Insofar as reference is made to certain bus systems in this application, these are preferred configurations. However, the protection area should also extend to technically equivalent bus systems.

In a further advantageous embodiment of the invention it is provided that the ASIC has an active connection to a smart card for reading key data from the smart card. In order to make corruption or unauthorized reading (sniffing) of the secret key data coming from the smart card impossible, the smart card can be connected directly to the ASIC via the RS232 interface and a reader and is therefore not connected to the host system. This interface is also implemented on the ASIC itself. A smart card terminal with an integrated (PIN) keyboard can also be connected to the RS232 interface so that entries such as passwords do not run via the host system.

In a further advantageous embodiment it is provided that the ASIC has a PCI interface. Data traffic is handled via this PCI interface, which is also located on the ASIC. The interface can be configured according to the current, valid standard from 32 bit / 33 MHz to 64 bit / 66 MHz and is also able as a master to initiate transfers on the PCI bus of a host.

In an advantageous embodiment of the invention it is provided that the ASIC is a serial

Has high-speed interface, in particular to communicate with other ASICs of the same type.

In a further advantageous embodiment of the invention it is further provided that it is embedded 00) r - i _ !. o cn o ol o ol

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is available. Two amplifier circuits are used in the overdrive range, an acyclic ring oscillator and a high-clocked linear feedback shift register ette. The analog generated numbers are fed into the shift register chain, so that this becomes aperiodic and no longer predictable. In order to achieve a good statistical uniform distribution of the numbers, these are then processed using a software algorithm. A low-level subroutine monitors the

Random number generation and activates an emergency program in the event of critical environmental influences (physical attacks).

In a further advantageous embodiment of the invention, it is provided that the ASIC contains self-sufficient encryption and decryption units (VE) that can be operated in parallel, in particular with activated VEs. A VE is a self-sufficient unit that can encrypt and decrypt a data block. The parallel operation can

Processing performance can be increased many times over.

Further advantageous refinements are described in subclaims 11 to 26.

In a further advantageous embodiment of the invention, it is provided that the ASIC has an active connection to a host system, in particular with software for password and key management. This configuration is particularly suitable for an entry-level variant in the form of a PCI

Plug-in card interesting, where it is configured so that only one VE is unlocked. With this system, the password and key management is completely via software running on the host system regulated. The product range is then scalable up to server systems with several PCI cards working in parallel, each equipped with a 64 bit / 66 MHz PCI interface, all VEs, smart card connection and a PCMCIA back-up card.

In an advantageous embodiment of the invention it is provided that the ASIC has a module for a key management and / or a module for generating random noise and / or a module for an intrusion detection and / or a module for a digital signature and / or a Module for a certification and / or a module for asymmetrical encryption and / or for a key exchange protocol and / or a module for a one-way function (hash algorithm) and / or for a standard algorithm on a symmetrical basis. The ASIC according to the invention connects a high-speed implementation of the encryption algorithm together with a module for key management, random noise and intrusion detection within a physical-technical unit. The ASIC achieves its full performance and full coverage of possible encryption tasks through its additionally separately integrated modules for digital signature and certification, asymmetric encryption and through

Key exchange protocols, through one-way functions (hash algorithms) and standard algorithms on a symmetrical basis. The presence of standard algorithms enables the use of ASICs within heterogeneous communication landscapes and thus ensures compatibility with other products.

The properties of the ASIC develop particularly advantageously if it is provided as part of a stand-alone system. co ω ΛJ M _i. _ι cn o cn O cn o cn

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Operating system and / or the random number preparation and / or a serial number and / or a certification key and / or a memory for initialization parameters for the analog circuits

are write-protected, there is a

particularly high security. The operating system and software running on the integrated C are managed and managed

controls all processes on the ASIC. There must therefore be no possibility of reading out or manipulating this data. With external memory modules, however, the possibility would exist, so that the system

dispenses with this and stores the entire software directly on the ASIC. For this purpose, a 256 KB flash memory is used, on which the operating system,

Initialization and configuration data as well as other software is stored permanently. It is possible to add customer-specific software to the system memory afterwards in order to achieve higher performance in the end application. Part of the memory is provided with write protection that cannot be deactivated. Parts of the

Operating system, the random number preparation, the

Serial number of the ASIC, certain certification keys (e.g. from trust centers) as well as various initialization parameters for the analog one

operate a network ASIC and thus implement an independent system (network router with encryption function) that is independent of a host computer.

Finally, an advantageous embodiment of the invention provides that a Diffie-Hellmann key exchange protocol is provided for the key management. The PCI card with the ASIC can also be used on key generation servers after activation of the corresponding functionalities. It is possible to build up a complex key hierarchy with partial, group and general keys. The keys have a length of 1683 bits and are primarily stored on smart cards. The smart cards have their own operating system, which is secured

Allows data transfers using public key cryptography. The statistical and personalized keys, or keys that are uniquely assigned to certain servers, are mainly used for authentication to a communication partner and for subsequent connection establishment. The encryption of the actual data packets to be exchanged takes place with dynamic keys that are generated online on the chip. The key comparison between the communication partners takes place according to the Diffie-Hellman key exchange protocol. This ensures that the keys never leave the hardware. After using the dynamic keys for an encryption session, they cannot be reconstructed from the memory of the corresponding one

Encryption unit deleted. Since the keys are never elsewhere, a compromise is not possible.

The invention is described in a preferred embodiment with reference to a drawing, wherein Further advantageous details can be found in the figures of the drawing. Functionally identical parts are provided with the same reference numerals.

The drawings show in detail:

FIG. 1 shows the schematic structure of the ASIC according to the invention,

Figure 2 shows the schematic block diagram of an ASIC on a PCI card and

Figure 3 shows the use of the ASIC in PCI cards.

The structure of the ASIC 2 according to the invention is shown in FIG. The modules for the CPU 9, a RISC processor, possibly a mathematical coprocessor, a flash memory 10 and the circuit module for the random number generation 11 are arranged on its surface. In the flash memory 10 are permanently

Software modules for key management, digital signature, certification, asymmetrical encryption and key exchange protocols, one-way functions and standard algorithms as well as the generated keys.

For intrusion detection, the ASIC has further circuit modules, namely one or more power-on-reset modules, a temperature detection module and a clock detection module.

An RS232 interface 5 and a PCMCIA interface 4 are provided for password entry and key storage. In addition, a PCI module 3 is integrated on the ASIC.

The keys generated by the RISC processor are sent to one to 15 freely configurable connections and

Decryption units (VEs) 12 forwarded. This are also located on the physical unit of the ASIC. These receive the incoming data packets intended for encryption or decryption and use them to generate the encrypted or decrypted data packets intended for output. The data packet exchange takes place via a PCI interface to and from the VEs.

A VE essentially consists of a data input line via which the data packets are stored in an input memory. A

Processing logic processes the data packets temporarily stored in the input memory with the aid of the keys stored in a key memory according to an algorithm. The processing logic forwards the processed data words to the output memory. From there they can be called up via the data output line. The processing logic receives the parameters and mode commands required for processing via another line.

FIG. 2 shows the configuration of the ASIC 2 on a PCI card 1 which can be inserted into a PCI slot in a host system. The ASIC communicates via the PCI bus present in the host system by means of the PCI module 3 provided on the ASIC 2 as an interface. In addition, data exchange with the PCMCIA card 6 via the PCMCIA module 4 is possible. The RS232 module 5 manages the data exchange with the SmartCard reader 7 and the SmartCard 8. The SmartCard reader 7 can be designed as a terminal with a PIN keyboard.

FIG. 3 shows a parallel arrangement of a plurality of PCI cards 1 and 14, each equipped with an ASIC 2. The three PCI cards 14 shown communicate via the common PCI bus 15 with a host system (not shown). Each ASIC 2 is independent of the host system connected by means of the PCMCIA interface 4 provided thereon to a PCMCIA card 6 serving as back-up memory and via the RS232 interface 5 also provided on the ASIC 2 to a password input keyboard 7, in which a smart card 8 with reader as a smart card terminal is integrated, connected via the RS232 bus 16.

In this way, an extremely secure encryption and decryption system with high data throughput is implemented.

LIST OF REFERENCE NUMBERS

1. PCI plug-in board

2. ASIC

3. PCI module

4. PCMCIA module

5. RS 232 module

6. PCMCIA card

7. Smart card reader or smart card terminal with keyboard

8. Smart card

9. CPU

10. Flash

11. Random number generator

12. Encryption and decryption unit

13. Data storage

14. PCI card

15. PCI bus

16. RS 232 bus

Claims

claims

1. Application-specific integrated circuit (ASIC) for encrypting and decrypting data streams with a CPU and possibly a coprocessor and at least one hardware-implemented encryption algorithm, characterized in that it has a PCMCIA interface (4) with an active connection to a PCMCIA card (6), which is designed as a database memory of key information.

2. ASIC according to claim 1, characterized in that it has an RS232 interface (5).

3. ASIC according to claim 1 or 2, characterized in that it has an active connection to a smart card reader (7) for reading key data from the smart card (8).

4. ASIC according to claim 1, 2 or 3, characterized in that it has a PCI interface (3).

5. ASIC according to claim 1, 2, 3 or 4, characterized in that it has a serial high-speed interface, in particular to communicate with other ASICs of the same type.

6. ASIC according to at least one of the preceding claims, characterized in that it has an embedded flash option (10), the embedded flash option preferably being provided with a write protection mechanism.

7. ASIC according to at least one of the preceding claims, characterized in that in particular the operating system and / or the random number preparation and / or a serial number and / or a

Certification key and / or a memory for initialization parameters for the analog circuits are read-only.

8. ASIC according to at least one of the preceding claims, characterized in that it is a

Has module for intrusion detection.

9. ASIC according to at least one of the preceding claims, characterized in that it is a

Module (11) for the generation of physical effects based

Has random numbers.

10. ASIC according to at least one of the preceding claims, characterized in that it contains autonomously working encryption and decryption units (VE) (12) which can be operated in parallel,

__ especially with 1 to 15 VEs enabled.

I i

¹ - *

11. ASIC according to at least one of the preceding claims, characterized in that the encryption and decryption units (12) with different and non-static

Keys are operable.

12. ASIC according to at least one of the preceding claims, characterized in that a

Program memory (13) for the operating system including software is designed as part of the ASIC (2), which is preferably designed as a flash memory (10).

13. ASIC according to at least one of the preceding claims, characterized in that it is a

Includes long number arithmetic module (9).

14. ASIC according to at least one of the preceding claims, characterized in that it is a

Contains module for the generation of cryptographically usable prime numbers.

15. ASIC according to at least one of the preceding claims, characterized in that it has a module for a key management.

16. ASIC according to at least one of the preceding claims, characterized in that it is a

Contains management module, which is designed to prevent reading of key data from the ASIC.

17. ASIC according to at least one of the preceding claims, characterized in that it is a

Has module for a digital signature.

18. ASIC according to at least one of the preceding claims, characterized in that it contains a module for key certification.

19. ASIC according to at least one of the preceding claims, characterized in that it has at least one module for an asymmetrical

Has encryption and / or for a key exchange protocol.

20. ASIC according to at least one of the preceding claims, characterized in that at least one module for key exchange, in particular on one Key exchange protocol based, is provided.

21. ASIC according to at least one of the preceding claims, characterized in that it has at least one module for forming cryptographic hash values.

22. ASIC according to at least one of the preceding claims, characterized in that it has at least one module for symmetrical encryption, in particular for keys with a length of at least 1024 bits, preferably with the possibility of forming cryptographic check bits.

23. ASIC according to at least one of the preceding claims, characterized in that it is provided as part of a stand-alone system.

24. ASIC according to at least one of the preceding claims, characterized in that it is arranged on a PCI card (1) and a

Interface (3) for a PCI bus.

25. ASIC according to at least one of the preceding claims, characterized in that it has an active connection to a host system, in particular with software for

Password and key management.

26. ASIC according to at least one of the preceding claims, characterized in that the CPU

(9) and / or the PCI interface (3) are designed to be integrated into the standard cell structure of the ASIC (2).