WO2002039796A1 - Definable integrated passives for circuitry - Google Patents
Definable integrated passives for circuitry Download PDFInfo
- Publication number
- WO2002039796A1 WO2002039796A1 PCT/US2001/051138 US0151138W WO0239796A1 WO 2002039796 A1 WO2002039796 A1 WO 2002039796A1 US 0151138 W US0151138 W US 0151138W WO 0239796 A1 WO0239796 A1 WO 0239796A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- component elements
- passive component
- pattern
- conductive material
- forming
- Prior art date
Links
- 238000000034 method Methods 0.000 claims abstract description 26
- 239000003990 capacitor Substances 0.000 claims abstract description 20
- 239000004020 conductor Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000151 deposition Methods 0.000 claims abstract description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 4
- 238000007667 floating Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 230000008901 benefit Effects 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 238000010276 construction Methods 0.000 description 3
- 239000013598 vector Substances 0.000 description 3
- 239000008204 material by function Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000011858 nanopowder Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000003618 dip coating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
Definitions
- the present invention relates to integrated passive circuitry designs and fabrication thereof.
- a method of forming integrated circuitry in a single plane comprising a plurality of passive components selected from the group consisting of capacitors, resistors, and inductors, the method comprising the steps of forming on a substrate a first pattern of conductive material and a first set of passive component elements, and depositing a patterned dielectric layer onto the substrate, wherein the first pattern of conductive material provides electrical connectivity to the first set of passive component elements.
- the substrate comprises alumina.
- the first set of passive component elements optionally comprises interdigitated capacitor electrodes.
- the method may also comprise the step of forming a floating plane over the dielectric layer.
- the first set of passive component elements may comprise a first set of electrodes of a set of parallel plate capacitors.
- the inventive method additionally may also comprise the further step of forming a second pattern of conductive material and a second set of passive component elements wherein the second pattern of conductive material provides electrical connectivity to the second set of passive component elements.
- the second set of passive component elements preferably comprises a second set of electrodes of a set of parallel plate capacitors paired with the first set of electrodes.
- the inventive method additionally may also comprise the step of forming a second pattern of conductive material and a second set of passive component elements, wherein the second pattern of conductive material provides electrical connectivity to the second set of passive component elements.
- an integrated circuit in a single plane formed by the aforementioned process of the invention may comprise a plurality of interdigitated capacitor electrodes.
- Fig. 1 is a cross-section view of an interdigitated capacitor apparatus of the invention, formed according to the method of the present invention (arrows indicate electric field vectors);
- Fig. 2 is a cross-section view of an interdigitated capacitor with floating plate formed according to the method of the present invention (arrows indicate electric field vectors);
- Fig. 3 is a cross-section view of a parallel-plate capacitor formed according to the present invention (arrows indicate electric field vectors).
- DESCRIPTION OF THE PREFERRED EMBODIMENTS (BEST MODES FOR CARRYING OUT THE INVENTION)
- the present invention is a novel integrated passive (capacitor, resistor and inductor) design and construction process involving definition of electrically functional materials.
- the primary advantage of the technology is the capability to form or insert multiple electrically functional components within the same plane. Connection of passive to active components is made using standard circuit patterns. In contrast, traditional integrated passives are fabricated in a multi-layer construction with each plane serving a single function. Connection of the passives to the surface mounted active components is achieved through circuit patterning and vias that serve as conductive paths between individual layers.
- the capacitor design of the present invention includes opposing conductive electrodes separated by a dielectric. Distinct from conventional designs, the capacitor design of the present invention includes definition or patterning of the dielectric.
- the dielectric layer is formed in specific areas on one or both electrode surfaces. In the case of an interdigitated electrode pattern 10, the dielectric 12 is deposited on both electrodes 14,14" (see Fig. 1) on a substrate 16 (e.g., alumina). A floating plate electrode 18 can be added, which increases the electric field and capacitance (see Fig. 2). In the case of a parallel plate electrode pattern, the dielectric is placed between two parallel plate electrodes 20,20' (see Fig. 3).
- a bottom electrode pattern is formed on an electrical substrate, e.g., alumina, using conventional plating, photoresist and/or etching processes.
- a photo or ultraviolet sensitive dielectric layer is coated onto the entire substrate using conventional film forming processes such as spin or dip coating.
- the dielectric layer is preferentially exposed to ultraviolet radiation to induce curing or polymerization of the dielectric coating.
- the unexposed dielectric coating is removed from the electrical substrate through solvent washing. (Specific areas of the dielectric coating remain over the bottom electrode pattern.)
- a top electrode patterned is formed above the bottom electrode pattern on top of the dielectric coating.
- connection to the top and bottom capacitor planes is made through circuit patterns formed with the bottom and top electrodes.
- electrically functional materials is not limited to photo patterning. Physical masking or other processes can also be used for preferential deposition.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
A method of fabricating a passive integrated circuit. The integrated circuitry is fabricated in a single plane, the circuitry including passive components such as capacitors, resistors, and inductors. The method features the steps of forming on a substrate (16) a first pattern (10) of conductive material and a first set of passive component elements, and depositing a patterned dielectric layer (12) onto the substrate. The first pattern of conductive material provides electrical connectivity to the first set of passive component elements. An apparatus fabricated according to method is disclosed.
Description
INTERNATIONAL APPLICATION
DEFINABLE INTEGRATED PASSIVES FOR CIRCUITRY
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation-in-part application of U.S. Patent Application Serial No. 09/458,363, entitled "Dielectric Material Including Particulate Filler", filed on December 9, 1999, and of U.S. Patent Application Serial No. 09/305,253, entitled "Integral Capacitance for Printed Circuit Board Using Dielectric Nanopowders", filed on May 4, 1999, both by William F. Hartman, Kirk M. Slenes, and Kristen J. Law, and the specifications thereof are incorporated herein by reference. The latter application claimed the benefit of the filing of U.S. Provisional Patent Application Serial No. 60/084,104, entitled "Integral Capacitance for Printed Circuit Board Using Dielectric Nanopowders", filed on May 4, 1998, and the specification thereof is also incorporated herein by reference.
This application claims the benefit of the filing of U.S. Provisional Patent Application Serial
No. 60/247,583, entitled "Definable Integrated Passives for Advanced Circuitry", filed on November 9, 2000, and the specification thereof is incorporated herein by reference.
GOVERNMENT RIGHTS The U.S. Government has a paid-up license in this invention and the right in limited circumstances to require the patent owner to license others on reasonable terms as provided for by the terms of Grant No. DMI-9761618 awarded by the U.S. National Science Foundation.
BACKGROUND OF THE INVENTION Field of the Invention (Technical Field):
The present invention relates to integrated passive circuitry designs and fabrication thereof.
Background Art:
Traditional integrated passives are fabricated in a multi-layer construction with each plane serving a single function. Connection of the passives to the surface mounted active components is
achieved through circuit patterning and vias that serve as conductive paths between individual layers. Illustrative of the prior art are U.S. Patent Nos. 5,578,860, 5,818,090, 5,923,077, 5,998,275, and 6,021 ,050. The present invention provides the capability to form or insert multiple electrically functional components within the same plane.
SUMMARY OF THE INVENTION (DISCLOSURE OF THE INVENTION) Thus, there is provided according to the invention a method of forming integrated circuitry in a single plane, the circuitry comprising a plurality of passive components selected from the group consisting of capacitors, resistors, and inductors, the method comprising the steps of forming on a substrate a first pattern of conductive material and a first set of passive component elements, and depositing a patterned dielectric layer onto the substrate, wherein the first pattern of conductive material provides electrical connectivity to the first set of passive component elements. Preferably, in the forming step the substrate comprises alumina. Also, in the forming step the first set of passive component elements optionally comprises interdigitated capacitor electrodes. The method may also comprise the step of forming a floating plane over the dielectric layer. Optionally, in the forming step the first set of passive component elements may comprise a first set of electrodes of a set of parallel plate capacitors.
The inventive method additionally may also comprise the further step of forming a second pattern of conductive material and a second set of passive component elements wherein the second pattern of conductive material provides electrical connectivity to the second set of passive component elements.
The second set of passive component elements preferably comprises a second set of electrodes of a set of parallel plate capacitors paired with the first set of electrodes.
The inventive method additionally may also comprise the step of forming a second pattern of conductive material and a second set of passive component elements, wherein the second pattern of conductive material provides electrical connectivity to the second set of passive component elements.
Thus, there also is provided according to the present invention an integrated circuit in a single plane formed by the aforementioned process of the invention. The circuit may comprise a plurality of interdigitated capacitor electrodes.
Objects, advantages and novel features, and further scope of applicability of the present invention will be set forth in part in the detailed description to follow, taken in conjunction with the accompanying drawings, and in part will become apparent to those skilled in the art upon examination of the following, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated into and form a part of the specification, illustrate one or more embodiments of the present invention and, together with the description, serve to explain the principles of the invention. The drawings are only for the purpose of illustrating one or more preferred embodiments of the invention and are not to be construed as limiting the invention. In the drawings:
Fig. 1 is a cross-section view of an interdigitated capacitor apparatus of the invention, formed according to the method of the present invention (arrows indicate electric field vectors);
Fig. 2 is a cross-section view of an interdigitated capacitor with floating plate formed according to the method of the present invention (arrows indicate electric field vectors); and
Fig. 3 is a cross-section view of a parallel-plate capacitor formed according to the present invention (arrows indicate electric field vectors).
DESCRIPTION OF THE PREFERRED EMBODIMENTS (BEST MODES FOR CARRYING OUT THE INVENTION) The present invention is a novel integrated passive (capacitor, resistor and inductor) design and construction process involving definition of electrically functional materials. The primary advantage of the technology is the capability to form or insert multiple electrically functional components within the same plane. Connection of passive to active components is made using standard circuit patterns. In contrast, traditional integrated passives are fabricated in a multi-layer construction with each plane serving a single function. Connection of the passives to the surface mounted active components is achieved through circuit patterning and vias that serve as conductive paths between individual layers.
The present invention is illustrated herein for capacitors. As understood by one of ordinary skill in the art, the invention can be appropriately modified for resistors and inductors, through substitutions of component compositions, as generally known in the art. As in conventional designs, the capacitor design of the present invention includes opposing conductive electrodes separated by a dielectric. Distinct from conventional designs, the capacitor design of the present invention includes definition or patterning of the dielectric. The dielectric layer is formed in specific areas on one or both electrode surfaces. In the case of an interdigitated electrode pattern 10, the dielectric 12 is deposited on both electrodes 14,14" (see Fig. 1) on a substrate 16 (e.g., alumina). A floating plate electrode 18 can be added, which increases the electric field and capacitance (see Fig. 2). In the case of a parallel plate electrode pattern, the dielectric is placed between two parallel plate electrodes 20,20' (see Fig. 3).
The preferred process sequence for fabrication of a parallel plate capacitor incorporating the integrated passive design of the present invention is described below. Similar processes are used for resistors and inductors.
1. A bottom electrode pattern is formed on an electrical substrate, e.g., alumina, using conventional plating, photoresist and/or etching processes.
2. A photo or ultraviolet sensitive dielectric layer is coated onto the entire substrate using conventional film forming processes such as spin or dip coating.
3. The dielectric layer is preferentially exposed to ultraviolet radiation to induce curing or polymerization of the dielectric coating.
4. The unexposed dielectric coating is removed from the electrical substrate through solvent washing. (Specific areas of the dielectric coating remain over the bottom electrode pattern.)
5. A top electrode patterned is formed above the bottom electrode pattern on top of the dielectric coating.
6. Connection to the top and bottom capacitor planes is made through circuit patterns formed with the bottom and top electrodes.
Note that definition of the electrically functional materials is not limited to photo patterning. Physical masking or other processes can also be used for preferential deposition.
Although the invention has been described in detail with particular reference to these preferred embodiments, other embodiments can achieve the same results. Variations and modifications of the present invention will be obvious to those skilled in the art and it is intended to cover in the appended claims all such modifications and equivalents. The entire disclosures of all references, applications, patents, and publications cited above are hereby incorporated by reference.
Claims
1. A method of forming integrated circuitry in a single plane, the circuitry comprising a plurality of passive components selected from the group consisting of capacitors, resistors, and inductors, the method comprising the steps of: forming on a substrate a first pattern of conductive material and a first set of passive component elements; and depositing a patterned dielectric layer onto the substrate; wherein the first pattern of conductive material provides electrical connectivity to the first set of passive component elements.
2. The method of claim 1 wherein in the forming step the substrate comprises alumina.
3. The method of claim 1 wherein in the forming step the first set of passive component elements comprises interdigitated capacitor electrodes.
4. The method of claim 3 additionally comprising the step of forming a floating plane over the dielectric layer.
5. The method of claim 1 wherein in the forming step the first set of passive component elements comprises a first set of electrodes of a set of parallel plate capacitors.
6. The method of claim 5 additionally comprising the step of forming a second pattern of conductive material and a second set of passive component elements wherein the second pattern of conductive material provides electrical connectivity to the second set of passive component elements.
7. The method of claim 6 wherein the second set of passive component elements comprises a second set of electrodes of a set of parallel plate capacitors paired with the first set of electrodes.
8. The method of claim 1 additionally comprising the step of forming a second pattern of conductive material and a second set of passive component elements wherein the second pattern of conductive material provides electrical connectivity to the second set of passive component elements.
9. An integrated circuit in a single plane formed by the process of claim 1.
10. The circuit of claim 9 comprising a plurality of interdigitated capacitor electrodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| AU2002234166A AU2002234166A1 (en) | 2000-11-09 | 2001-11-09 | Definable integrated passives for circuitry |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US24758300P | 2000-11-09 | 2000-11-09 | |
| US60/247,583 | 2000-11-09 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO2002039796A1 true WO2002039796A1 (en) | 2002-05-16 |
| WO2002039796A8 WO2002039796A8 (en) | 2002-09-26 |
Family
ID=22935461
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2001/051138 WO2002039796A1 (en) | 2000-11-09 | 2001-11-09 | Definable integrated passives for circuitry |
Country Status (2)
| Country | Link |
|---|---|
| AU (1) | AU2002234166A1 (en) |
| WO (1) | WO2002039796A1 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3290756A (en) * | 1962-08-15 | 1966-12-13 | Hughes Aircraft Co | Method of assembling and interconnecting electrical components |
| US4000054A (en) * | 1970-11-06 | 1976-12-28 | Microsystems International Limited | Method of making thin film crossover structure |
| US4294009A (en) * | 1978-06-29 | 1981-10-13 | Le Material Telephonique | Method of manufacturing a hybrid integrated circuit |
-
2001
- 2001-11-09 WO PCT/US2001/051138 patent/WO2002039796A1/en not_active Application Discontinuation
- 2001-11-09 AU AU2002234166A patent/AU2002234166A1/en not_active Abandoned
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3290756A (en) * | 1962-08-15 | 1966-12-13 | Hughes Aircraft Co | Method of assembling and interconnecting electrical components |
| US4000054A (en) * | 1970-11-06 | 1976-12-28 | Microsystems International Limited | Method of making thin film crossover structure |
| US4294009A (en) * | 1978-06-29 | 1981-10-13 | Le Material Telephonique | Method of manufacturing a hybrid integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| AU2002234166A1 (en) | 2002-05-21 |
| WO2002039796A8 (en) | 2002-09-26 |
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