WO2002037565A2 - Procede permettant de connecter des conducteurs sur differents niveaux d'un dispositif microelectronique et appareil associe - Google Patents

Procede permettant de connecter des conducteurs sur differents niveaux d'un dispositif microelectronique et appareil associe Download PDF

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Publication number
WO2002037565A2
WO2002037565A2 PCT/US2001/045250 US0145250W WO0237565A2 WO 2002037565 A2 WO2002037565 A2 WO 2002037565A2 US 0145250 W US0145250 W US 0145250W WO 0237565 A2 WO0237565 A2 WO 0237565A2
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WIPO (PCT)
Prior art keywords
layer
depositing
dielectric layer
metallic layer
metallic
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PCT/US2001/045250
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English (en)
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WO2002037565A3 (fr
Inventor
Sundeep N. Nangalia
Robert L. Wood
Philip Alan Deane
Bruce William Dudley
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Mcnc
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Priority to AU2002220022A priority Critical patent/AU2002220022A1/en
Publication of WO2002037565A2 publication Critical patent/WO2002037565A2/fr
Publication of WO2002037565A3 publication Critical patent/WO2002037565A3/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]

Definitions

  • the present invention relates to microelectronic devices and, more particularly, to a method of connecting conductors on different levels of a microelectronic device and associated apparatus.
  • Semiconductor devices are typically fabricated according to a layer methodology, wherein, for example, a blanket layer is deposited over a substrate.
  • the blanket layer may then be coated with a photoresist that is patterned to selectively define areas of the photoresist which remain on the blanket layer, the areas of the photoresist remaining on the blanket layer typically defining the portions of the blanket layer to be removed.
  • the blanket layer is then etched to remove the unwanted portions thereof before the photoresist is thereafter removed.
  • the remaining portions of the blanket layer define the desired features in the particular layer of the device. Such features may include, for example, bonding pads or metallization lines corresponding to the device circuitry.
  • An alternative layer fabrication method typically involves depositing and patterning a photoresist layer over the substrate such that the remaining photoresist defines the desired features for a particular layer. A material is then deposited within the open areas defined by the photoresist. The photoresist is thereafter removed such that the material remains deposited over the substrate and comprises the desired features in the desired configuration.
  • a typical microelectronic device may comprise many layers fabricated according to one of the above processes. Such devices may include various metallization layers for electrically connecting other metal layers or for allowing electrical connections to be formed externally to the device.
  • metallization layers in a microelectronic device are generally more sensitive to manufacturing defects encountered in the fabrication process than are dielectric layers. For instance, a dust particle may be enough to disrupt continuity in a metallization line or an incomplete etching process may cause a short circuit between metallization lines. Defective metallization often results in an unusable device and reduces the yield of the device fabrication process.
  • SHOCC Seamless High Off-Chip Connectivity
  • the metallization layers are typically connected to larger scale devices or external electrical connections and therefore require large pitch conductors for forming the necessary electrical connections.
  • These large pitch conductors may be configured in, for example, a Ball-Grid- Array (BGA) type coarse pitch.
  • BGA Ball-Grid- Array
  • an interposer may be required to route very fine pitch conductors from one surface thereof to coarse pitch conductors at the opposite surface.
  • Interposers or separate substrates for metallization layers are commonly fabricated in a build-up process or are formed from pre-existing substrate materials such as, for example, PC board on FR4 or ceramic circuits on ceramic green tape.
  • substrate materials such as, for example, PC board on FR4 or ceramic circuits on ceramic green tape.
  • holes or other features of a correspondingly fine pitch must be formed in the substrate/interposer.
  • Laser ablation has typically been the only method capable of forming the necessary fine pitch holes/features in the substrate. However, laser ablation is limited in processing flexibility and may, for instance, be unable to readily compensate for variances in the parameters defining the substrate.
  • the laser may not be able to produce the holes/features according to specification without optimizing the laser power beforehand or reworking the substrate to achieve the desired configuration.
  • laser ablation of holes/features may be a time-consuming process limited by, for example, the number of laser devices and the speed of the mechanism controlling the position of the lasers for the particular process.
  • laser ablation methods may be limited in the magnitude of the pitch that may be produced, wherein the pitch of the holes/features capable of being produced by the laser device may not be as fine as required by the particular process. Similar situations may be encountered in other instances where an electrical connection through a substrate is required.
  • a dielectric layer is deposited over a first metallic layer before a via is formed in the dielectric layer such that the via extends through the dielectric layer.
  • a via metal is then deposited in the via, using the dielectric layer as a stencil, so as to at least partially fill the via.
  • the via metal is deposited such that it is electrically connected to the first metallic layer.
  • a second metallic layer is then deposited over the via metal such that the second metallic layer is also electrically connected to the via metal.
  • the via metal thereby forms an electrical connection between the first metallic layer and the second metallic layer on opposing surfaces of the dielectric layer.
  • the dielectric layer thus forms both a stencil for the deposition of the via metal and an interlevel dielectric between the two metallic layers, while functioning as a structural substrate for the microelectronic device.
  • the dielectric layer is insolublized following deposition thereof over the first metallic layer and prior to depositing the via metal in the via.
  • the dielectric layer is comprised of a photoimagable spin-on epoxy or polymer.
  • the first metallic layer may be configured in a Ball-Grid- Array (BGA) type coarse pitch
  • the second metallic layer may be configured in a seamless high off-chip connectivity (SHOCC) type fine pitch.
  • the method may further comprise electrically connecting a microelectronic circuit to at least one of the first metallic layer and the second metallic layer.
  • One advantageous embodiment of the present invention further comprises a particular method of electrically connecting conductors on different levels of a microelectronic device. First, a sacrificial layer is deposited over a microelectronic carrier. A first metallic layer is then deposited over the sacrificial layer.
  • a dielectric layer is then deposited over the first metallic layer, whereafter a via is formed in the dielectric layer extending through the dielectric layer.
  • a via metal is then deposited in the via, using the dielectric layer as a stencil, so as to at least partially fill the via and such that the via metal is electrically connected to the first metallic layer.
  • a second metallic layer is then deposited over the via metal such that the second metallic layer is electrically connected to the via metal. Since the via metal electrically connects the first metallic layer to the second metallic layer on opposing surfaces of the dielectric layer, the dielectric layer forms both a stencil for the deposition of the via metal and an interlevel dielectric, separating the first metallic layer from the second metallic layer, while also functioning as a structural substrate for the microelectronic device.
  • the sacrificial layer may comprise a dissolvable layer deposited over the microelectronic carrier, followed by an etch stop layer deposited over the dissolvable layer, wherein the dissolvable layer may be comprised of phosphosilicate glass and the etch stop layer may be comprised of titanium.
  • the first metallic layer may further comprise a plating base deposited over the sacrificial layer, wherein the plating base may be comprised of copper, aluminum, gold, and/or chromium.
  • the method may further include selectively depositing a contact layer over the first metallic layer prior to depositing the dielectric layer, wherein the contact layer may be comprised of, for example, a layer of gold deposited between opposing layers of nickel, nickel, gold, copper, and/or a solder material.
  • the method may further comprise insolublizing the dielectric layer prior to depositing the via metal within the via, wherein the dielectric layer may be comprised of, for example, a photoimagable spin-on epoxy or polymer.
  • a metal fill layer is deposited over the dielectric layer so as to at least fill the via and form the via metal which may be comprised of, for example, copper, nickel, gold, and or a solder material.
  • the dielectric layer is then planarized such that the fill layer fills the via and forms a coplanar surface with the dielectric layer.
  • the sacrificial layer is removed, such as by dissolving the dissolvable layer, so as to separate the dielectric layer from the microelectronic carrier.
  • the plating base and a nickel layer of the contact layer may also be removed so as to expose the gold layer of the contact layer.
  • a microelectronic circuit may then be electrically connected to at least one of the contact layer and the second metallic layer.
  • the first metallic layer may be configured in a BGA type coarse pitch and the second metallic layer may be configured in a SHOCC type fine pitch.
  • Another advantageous aspect of the present invention comprises an alternate method of electrically connecting conductors on different levels of a microelectronic device.
  • a via is formed in the dielectric layer extending through the dielectric layer.
  • a metallic conformal layer is then deposited over the dielectric layer such that the conformal layer is electrically connected to the first metallic layer through the via.
  • a via metal is then deposited in the via so as to at least partially fill the via and such that the via metal is electrically connected to the conformal layer.
  • a second metallic layer is then deposited over the via metal such that the conformal layer and the via metal thereby form an electrical connection between the first metallic layer and the second metallic layer on opposing surfaces of the dielectric layer.
  • the dielectric layer thereby forms a stencil for the deposition of the via metal and an interlevel dielectric, while also functioning as a structural substrate for the microelectronic device.
  • the sacrificial layer further comprises a dissolvable layer over the microelectronic substrate, wherein the dissolvable layer may comprise, for instance, phosphosilicate glass.
  • the first metallic layer may comprise a selectively deposited etch stop layer over the sacrificial layer, wherein the etch stop layer may comprise, for example, titanium.
  • the conformal layer may further comprise a plating base deposited over the dielectric layer, wherein the plating base may include, for example, a layer of titanium over a layer of phase chromium-copper over a layer of copper, copper, chromium, aluminum, nickel, and/or gold.
  • the via metal is deposited as a fill layer over the conformal layer, wherein the via metal at least fills the via and may be comprised of, for example, copper, gold, nickel, and/or a solder material.
  • the dielectric layer is then planarized following deposition of the fill layer such that the fill layer and the conformal layer fill the via and form a coplanar surface with the dielectric layer.
  • the sacrificial layer is removed as to separate the dielectric layer from the microelectronic carrier. Thereafter, the first metallic layer is removed so as to expose the conformal layer.
  • the first metallic layer is configured in a BGA type coarse pitch while the second metallic layer is configured in a SHOCC type fine pitch.
  • a microelectronic circuit may thereafter be electrically connected to at least one of the conformal layer and the second metallic layer.
  • a further advantageous aspect of the present invention comprises a microelectronic device having an electrical connection through a dielectric layer.
  • the device comprises a first conductor, a second conductor, and a dielectric layer.
  • the dielectric layer is deposited over the first conductor and de.fines a via filled with a via metal.
  • the dielectric layer is preferably used as a stencil for deposition of the via metal in the via.
  • the second conductor is thereafter deposited over the via metal to electrically connect the first conductor to the second conductor through the dielectric layer such that the dielectric layer forms both a stencil for the deposition of the via metal and an interlevel dielectric in the microelectronic device, while also functioning as a structural substrate for the microelectronic device.
  • one of the conductors is configured in a BGA type coarse pitch while the other conductor is configured in a SHOCC type fine pitch.
  • the dielectric layer comprises a photoimagable spin-on epoxy or polymer, while the via metal is comprised of, for example, copper, nickel, gold, and/or a solder material.
  • the microelectronic device may further comprise a microelectronic circuit electrically connected to at least one of the first conductor and the second conductor.
  • embodiments of the present invention advantageously provide a process for forming an electrical connection between conductors on opposing surfaces of a substrate in a microelectronic device that is relatively easily applied in a cost-effective manner while permitting flexibility in the configuration miniaturization of the microelectronic device electrically connected thereto.
  • Using a photoimagable spin-on epoxy or polymer as a stencil for the deposition of the via metal, while retaining the epoxy between metal layers as the interlevel dielectric provides a structural substrate for the microelectronic device while reducing the amount of process steps as compared to the prior art while producing a simpler and more flexible process.
  • FIG. 1 is a cross-sectional view schematically illustrating an apparatus for connecting conductors on different levels of a microelectronic device according to one embodiment of the present invention.
  • FIGS. 2A - 2G are cross-sectional views schematically illustrating a method of connecting conductors on different levels of a microelectronic device according to an embodiment of the present invention.
  • FIGS. 3A - 3H are cross-sectional views schematically illustrating a method of connecting conductors on different levels of a microelectronic device according to an alternate embodiment of the present invention.
  • FIG. 1 schematically illustrates a cross-section of a microelectronic device having an electrical connection through a dielectric layer according to one embodiment of the present invention.
  • Some microelectronic devices such as, for example, seamless high off-chip conductivity (SHOCC) type devices, move certain metallization layers from the device to a separate substrate to reduce the number of manufacturing steps necessary to fabricate the device while increasing the yield of the process. Accordingly, the separate substrate having the metallization layers thereafter serves as an interposer for electrically connecting the microelectronic device into corresponding electronic circuitry.
  • SHOCC type device arrangement is indicated generally by the numeral 100 in FIG. 1 and comprises a microelectronic device 110, an interposer 120, and other electronic circuitry 130.
  • the interposer 120 generally comprises a dielectric layer 122 having a first conductor 124 on one surface and a second conductor 126 on the opposing surface.
  • a via metal 128 electrically connects the first conductor 124 to the second conductor 126 through the dielectric layer 122.
  • the microelectronic device 110 has a circuit contact 112 that contacts and forms an electrical connection with the second conductor 126, while the electronic circuitry 130 has a corresponding contact 132 that contacts and forms an electrical connection with the first conductor 124.
  • the circuit contact 112 and the second conductor 126 are scaled in a SHOCC type fine pitch while the contact 132 and the first conductor 124 are configured in a BGA type coarse pitch.
  • the interposer 120 thereby provides a more robust electrical connection than if the circuitry contact 112 were to directly interface with the contact 132.
  • the interposer 120 provides a more flexible mechanism for interfacing various conductors.
  • the second conductor 126 may be separated into a plurality of portions each engaging a via metal 128 to form an electrical connection with the first conductor 124, thereby allowing multiple circuit contacts 112 to be electrically connected to the contact 132 on the opposing surface of the interposer 120.
  • the interposer 120 is "built-up" in an layering process, wherein the dielectric layer 122 serves both as a stencil for the deposition of the via metal 128 as well as an interlevel dielectric separating the first conductor 124 from the second conductor 126.
  • the built-up fabrication method thereby provides increased flexibility for varying the scale and configuration of the contacts 112 and 132 while providing a more precise and consistent interposer 120 than with prior art methods which form the necessary features in the interposer 120 using laser ablation.
  • FIGS. 2A-2G disclose a sequence of cross-sectional views schematically illustrating a method of electrically connecting conductors on different levels of a microelectronic device, indicated generally by the numeral 200, according to one embodiment of the present invention.
  • a microelectronic carrier 210 such as, for example, a silicon wafer, over which is deposited a sacrificial layer 220.
  • the features of the device are fabricated over a microelectronic carrier comprising, for instance, a silicon wafer.
  • a layer or element when a layer or element is described herein as being over another layer or element, it may be formed directly on the layer, at the top, bottom, or side surface area thereof. Alternatively, one or more intervening layers may be provided between the layers.
  • the sacrificial layer 220 may comprise, for example, a layer of phosphosilicate glass (PSG).
  • PSG phosphosilicate glass
  • an etch stop pad 230 may be deposited over the sacrificial layer 220, wherein the pad 230 may be comprised of, for example, titanium.
  • a plating base 240 is then deposited, generally as a blanket layer, over the sacrificial layer 220 and the etch stop pad 230.
  • the plating base 240 is comprised of, for example, copper that is evaporated or sputter-coated over the preceding layer(s), but may also be comprised of aluminum, gold, and/or chromium.
  • the purpose of the etch stop pad 230 and the plating base 240 will become more apparent when described further herein.
  • a photoresist 250 is deposited over the plating base 240 and then patterned to selectively define open an area therein, generally in a location where the etch stop pad 230 is underlying the plating base 240.
  • Spin coating of the photoresist 250 with subsequent patterning is well known to those skilled in the art and will not be described further herein.
  • a contact layer 260 is deposited over the plating base 240 in the open area.
  • the contact layer 260 comprises a layer of nickel 260a with a layer of gold 260b deposited thereover, and a second nickel layer 260c deposited over the gold layer 260b.
  • the two nickel layers 260a and 260c and the gold layer 260b may all be deposited using, for example, an electroplating process.
  • the contact layer 260 may also comprise nickel, gold, copper, and/or a solder material.
  • a dielectric layer 270 is deposited over the contact layer 260.
  • the dielectric layer 270 may comprise, for example, a photoimagable spin-on epoxy or polymer.
  • the dielectric layer 270 may then be patterned and selective portions thereof removed such that the dielectric layer 270 defines a via 280 over the contact layer 260.
  • a via metal 282 is then deposited so as to at least partially fill the via 280, as shown in FIG. 2E.
  • the dielectric layer 270 may be insolublized following deposition thereof and prior to deposition of the via metal 282.
  • the dielectric layer 270 is planarized to obtain a flat surface.
  • the dielectric layer 270 may be planarized by a chemical-mechanical polishing (CMP) process.
  • CMP chemical-mechanical polishing
  • the planarizing process planarizes both the dielectric layer 270 and the via metal 282 such that the via metal 282 fills the via 280 and forms a coplanar surface with the dielectric layer 270.
  • a thin film circuit 290 is formed over the dielectric layer 270 as shown in FIG. 2F.
  • the circuit 290 may comprise, for example, a benzocyclobutene (BCB) layer 290a, with an opening defined thereby over the via metal 282.
  • a second metallic layer 290b such as, for instance, an aluminum line is then deposited in the opening defined by the BCB layer 290a by an evaporation process such that the second metallic layer 290b is in electrical contact with the via metal 282.
  • the sacrificial layer 220 is then removed by dissolution such that the microelectronic carrier 210 is separated from the device 200.
  • the etch stop 230, the plating base 240, and one of the nickel layers 260a are all removed such that the gold layer 260b is exposed.
  • the via metal 282 forms an electrical connection between the second metallic layer 290b disposed on one side of the dielectric layer 270 to the nickel layer 260c, and thus the gold layer 260b, generally disposed on the opposite surface of the dielectric layer 270.
  • the dielectric layer 270 is used as a stencil for the deposition of the via metal 282, but also remains in the final device 200 as a structural substrate for the device 200 that also serves as the interlevel dielectric between the contact layer 260 and the second metallic layer 290b.
  • FIGS. 3A-3H disclose a cross-sectional sequence schematically illustrating an alternate method of electrically connecting conductors on different levels of a microelectronic device, the microelectronic device being indicated generally by the numeral 300.
  • the process begins with a sacrificial layer 320 deposited over a microelectronic carrier 310, wherein the sacrificial layer 320 may comprise, for example, phosphosilicate glass while the microelectronic carrier 310 may be, for instance, a silicon wafer.
  • An etch stop pad 330 may thereafter be selectively deposited over the sacrificial layer 320 as a first metallic layer 330 and may be comprised of, for example, titanium.
  • a dielectric layer 340 is then deposited over the first metallic layer 330 and the sacrificial layer 320 in a blanket layer, wherein the dielectric layer 340 may be comprised of a photoimagable spin-on epoxy or polymer.
  • the dielectric layer 340 is thereafter patterned so as to define a via 350 over the first metallic layer 330 extending through the dielectric layer 340. Once the via 350 is formed, the dielectric layer 340 is insolublized.
  • a plating base 360 is then deposited over the dielectric layer 340, wherein the plating base 360 may be comprised of copper, deposited by an evaporation process to form a conformal coating over the dielectric layer 340 without filling the via 350.
  • the plating base 340 may include a layer of phase chromium-copper (not shown) deposited over the copper, further with a layer of titanium (not shown) deposited thereover, wherein the phase chromium-copper comprises the underbump metallurgy as is known in the art.
  • the plating base 360 may also be comprised of chromium, aluminum, nickel, and/or gold.
  • a photoresist 370 is deposited over the plating base 360 and patterned to define an open area corresponding to the via 350.
  • a via metal 380 is thereafter deposited in the via 350, wherein the via metal 380 may be comprised of copper deposited by an electroplating process or other materials such as, for example, nickel, gold, and/or a solder material.
  • the dielectric layer 340 is planarized by, for example, a CMP process to obtain a flat surface as shown in FIG. 3F.
  • the plating base 360 and the via metal 380 combine to fill the via 350 and to form a coplanar surface with the dielectric layer 340.
  • a thin film circuit 390 is formed over the planarized dielectric layer 340.
  • the thin film circuit 390 may further comprise, for example, an insulating layer 390a and a second metallic layer 390b.
  • the insulating layer may comprise spin cast benzocyclobutene (BCB)
  • the second metallic layer 390b may comprise an aluminum line formed by evaporation within an opening formed in the insulating layer 390a over the via 350.
  • BCB spin cast benzocyclobutene
  • the second metallic layer 390b may comprise an aluminum line formed by evaporation within an opening formed in the insulating layer 390a over the via 350.
  • an electrical connection is formed between the second metallic layer 390b, the via metal 380, and the plating base 360.
  • the sacrificial layer 320 is then dissolved to separate the carrier 310 from the dielectric layer 340 and the first metallic layer 330 also removed to expose the plating base 360.
  • An electrical connection is therefore formed between the second metallic layer 390b and the plating base 360 by way of the. via metal 380.
  • the dielectric layer 340 thereby serves as both a stencil for the deposition of the via metal 380 and the plating base 360 as well as an interlevel dielectric, while functioning as a structural substrate for the device 300.
  • a common feature is the use of a dielectric layer that serves as a stencil for a subsequent deposition process, but also remains in the device as a structural substrate as well as an interlevel dielectric.
  • the number of process steps generally required to build up such a device are reduced.
  • the deposition of a dielectric layer would ordinarily require the deposition of the dielectric layer, followed by a photoresist layer and a photoresist patterning step to define portions of the dielectric layer to be removed.
  • the dielectric layer would then have to be etched to form the necessary features before the photoresist is removed.
  • the same result may be achieved by the deposition of a dielectric layer with subsequent patterning to define the desired features, before the dielectric layer is insolublized to remain in place and to serve as a structural member in the device.
  • a dielectric layer with subsequent patterning to define the desired features
  • the dielectric layer is insolublized to remain in place and to serve as a structural member in the device.
  • Such an elimination of process steps is advantageous in a manufacturing process.
  • embodiments of the present invention also provide further advantages in that a build-up method of manufacturing an electronic device as described is more flexible than prior art processes employing laser ablation of existing substrates to form the necessary device.
  • Embodiments of the present invention therefore, provide a process for forming an electrical connection between conductors on * opposite surfaces of a substrate in a microelectronic device that is relatively easily applied, is generally cost effective, and permits flexibility in the configuration of the device so as to be applicable to a wide variety of microelectronic devices, also taking into account the scale of such devices.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention se rapporte à un procédé permettant de connecter électriquement des conducteurs sur différents niveaux d'un dispositif microélectronique. Une couche diélectrique est déposée sur une première couche métallique, et un trou d'interconnexion est ensuite formé dans la couche diélectrique, de façon à s'étendre à travers cette dernière. Un métal d'interconnexion est ensuite déposé dans le trou d'interconnexion, de sorte que ledit trou soit en contact électrique avec la première couche métallique. Une seconde couche métallique est ensuite déposée sur le métal d'interconnexion de sorte que la seconde couche métallique soit en contact électrique avec le métal d'interconnexion. Le métal d'interconnexion constitue ainsi une connexion électrique entre la première et la seconde couche métallique sur des surfaces opposées de la couche diélectrique. La couche diélectrique constitue ainsi un stencil permettant de déposer le métal d'interconnexion et un diélectrique intercouche séparant la première couche métallique de la seconde, tout en fonctionnant comme un substrat structurel pour le dispositif microélectronique. Le procédé de la présente invention permet notamment de connecter un conducteur à pas fin sur un côté de la couche diélectrique à un conducteur à grand pas sur le côté opposé. L'invention traite également d'un appareil associé audit procédé pouvant comprendre un circuit microélectronique connecté électriquement à au moins une des deux couches métalliques.
PCT/US2001/045250 2000-11-06 2001-11-01 Procede permettant de connecter des conducteurs sur differents niveaux d'un dispositif microelectronique et appareil associe WO2002037565A2 (fr)

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US70723300A 2000-11-06 2000-11-06
US09/707,233 2000-11-06

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WO1999005717A1 (fr) * 1997-07-22 1999-02-04 Commissariat A L'energie Atomique Procede de fabrication d'un film conducteur anisotrope a inserts conducteurs
US20010005050A1 (en) * 1997-11-28 2001-06-28 Kenji Ohsawa Semiconductor device, method making the same, and electronic device using the same

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