WO2002035851A2

WO2002035851A2 - Low bandwidth universal video/graphics interface

Info

Publication number: WO2002035851A2
Application number: PCT/EP2001/011783
Authority: WO
Inventors: Jens Rennert; Ralph Escherich
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2000-10-20
Filing date: 2001-10-11
Publication date: 2002-05-02
Also published as: KR20020064943A; JP2004512783A; WO2002035851A3

Abstract

The invention provides an efficient implementation of a digital video and graphics interface, such as a D1 like 10 or 8 bit interface, suitable for transmitting high quality non-subsampled digital video and graphics data. The invention also defines D1 like serialized data formats for use in transmitting the non-subsampled data via D1 like interfaces. The invention may be operated in the following operating modes: 1) single stream/single interface mode, in which a single data stream is transmitted via a single interface; 2) dual stream/single interface mode, an extension of the single stream/single interface mode, in which one interface is used to transmit two different data streams; 3) single stream/dual interface mode for transmitting a subsampled YUV data stream up to full HD (high definition) resolution clock rates; and 4) quadruple stream/dual interface mode suitable for transmitting high bandwidth HD digital video data streams, in which two interfaces are used to transmit four different data streams.

Description

Low bandwidth universal video/graphics interface

B ACKGROUND OF THE INVENTION

The invention generally relates to video/graphics interfaces, and more particularly to implementation of a Dl like interface suitable for transmitting non- subsampled digital video and graphics data, e. g., YUV and RGB data. A Dl interface is widely accepted in the digital video world to transfer digital video data between devices. It is defined as a YUV 4:2:2 subsampled video interface. A traditional Dl interface allows subsampled YUV data to be sent across a parallel 8 or 10 bit interface. Data are sent as pairs of YU followed by a pair of YV data. Because of the low bandwidth display devices in consumer applications, a subsampling of UN was acceptable. The current transition to high-definition television (HDTN) products, however, demands high quality video and graphics data going across digital video and graphics interfaces. A conventional way to transmit high quality YUN 4:4:4 non-subsampled images is to convert a serialized data format to a full parallel format. That, however, significantly increases the pin count of the devices as well as device costs. Therefore, there is a need for a low cost, effective implementation of a digital video and graphics interface suitable for transmitting high quality non-subsampled digital video and graphics data.

SUMMARY OF THE INVENTION The present invention provides an efficient implementation of a digital video and graphics interface, such as a Dl like 10 or 8 bit interface, suitable for transmitting high quality non-subsampled digital video and graphics data. The invention also defines Dl like serialized data formats for use in transmitting the non-subsampled data via Dl like interfaces.

The invention may be operated in the following operating modes: 1) single stream/single interface mode, in which a single data stream is transmitted via a single interface;

2) dual stream/single interface mode, an extension of the single stream/single interface mode, in which one interface is used to transmit two different data streams; 3) single stream/dual interface mode for transmitting a subsampled YUV data stream up to full HD (high definition) resolution clock rates; and

4) quadruple stream/dual interface mode suitable for transmitting high bandwidth HD digital video data streams, in which two interfaces are used to transmit four different data streams.

In accordance with a first embodiment of the invention, a data formatter is provided. The data formatter comprises a data formatting circuit, having a first interface, that is configured to receive a first input stream of digital video/graphics data and format the data for outputting via the first interface; and a controller, operably coupled to the data formatting circuit, that is configured to cause the data formatting circuit to operate in a first operating mode in which the data formatting circuit outputs components of the video/graphics data (e.g., YUN or RGB) in a first predetermined serialized format via the first interface. In one example, the first predetermined serialized format includes a non-subsampled format.

According to a variation of the first embodiment of the invention, the data formatting circuit is further configured to receive a second input stream of digital video/graphics data and format both the first and second input streams for outputting via the first interface; and wherein the controller is further configured to cause the data formatting circuit to operate in a second operating mode in which the data formatting circuit outputs the components of the two input streams of data in a second predetermined serialized format via the first interface.

A data formatter, according to a second embodiment of the invention, comprises a data formatting circuit, having first and second interfaces, that is configured to receive a first input stream of digital video/graphics data and format the data for outputting via the first and second interfaces; and a controller, operably coupled to the data formatting circuit, that is configured to cause the data formatting circuit to output, in one operating mode, components of the video/graphics data in a first predefined format via the first and second interfaces.

According to a variation of the second embodiment of the invention, the data formatting circuit is further configured to receive second, third and fourth input streams of digital video/graphics data and format the four input streams for outputting in a second predefined format; and the controller is further configured to cause the data formatting circuit to output, in another operating mode, the components of the four input streams of data via the first and second interfaces in a second predefined format. A video/graphics processor that incorporates a data formatter of the invention is also provided.

Other objects and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is explained in further detail, and by way of example, with reference to the accompanying drawings wherein: FIG. 1 shows a functional block diagram of an exemplary system suitable for implementing the present invention;

FIG. 2 shows a functional block diagram of a video/graphics processor according to the present invention;

FIG. 3A-3D illustrates exemplary formatted outputs at an interface of the processor of FIG. 2 operated in a first operating mode;

FIG. 4A-4D illustrates exemplary formatted outputs at an interface of the processor of FIG. 2 operated in a second operating mode;

FIG. 5 illustrates an exemplary formatted output at the interfaces of the processor of FIG. 2 operated in a third operating mode; FIG. 6 shows a controller of the processor of FIG. 2;

FIG. 7 shows a variation of the processor of FIG. 2; and FIGS. 8A-8C illustrates exemplary formatted outputs at the interfaces of the processor of FIG. 7 operated in a fourth operating mode.

Throughout the drawings, the same reference numerals indicate similar or corresponding features or functions.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows a functional block diagram of an exemplary system suitable for implementing the present invention. As illustrated in FIG. 1, a digital video/graphics source 10 supplies digital video/graphics signals to a memory buffer 16. The digital data are stored in memory buffer 16 in a standard format. Upon command, a video/graphics data processor 20 receives the digital data for processing. Processor 20 transmits the processed data to a video/graphics encoder 26 in a predetermined format. Encoder 26 then encodes the data and transmits them to a display device 30 for displaying. FIG. 2 shows a functional block diagram of processor 20 according to the present invention. Processor 20 includes a conventional video/graphics processing pipeline 36 and an output formatter 40. As will be understood by those skilled in the art, pipeline 36 performs well-known functions, such as pixel formatting, color space conversion, transformation filtering and pixel mixing, etc. Output formatter 40 includes a data formatting circuit 46, which may be a multiplexer, and a controller 50 operably coupled to the formatting circuit. Formatting circuit 46 receives data streams 52 and 56 and outputs them in predetermined formats on interfaces 62 and 66, as will be further explained below. The outputs of formatting circuit 46 are provided to a mixer (not shown) for sending to encoder 26. Controller 50 receives various signals from pipeline 36, including Hbiank (horizontal blank), Nsync (vertical synchronization), Pcik (pixel clock) and Mcik (multiplexer clock), and controls formatting circuit 46 to operate in a desired mode.

According to one embodiment of the present invention, output formatter 40 may be operated in one of three operating modes. These three modes include: 1) a single stream/single interface mode, 2) a dual stream/single interface mode, and 3) a single stream/dual interface mode. In the first operating mode, only one data stream, such as data stream 52, is supplied to formatting circuit 46 by pipeline 36 and is formatted by formatting circuit 46 for outputting via a single interface, such as interface 62. The data stream may be either video data (i.e., YUN data) or graphics data (i.e., RGB data). FIGS. 3A-3D illustrate exemplary formatted outputs at an interface (e.g., interface 62) of processor 20 operated in the first operating mode, with a single data stream 52. FIG. 3 A shows an exemplary formatted output at interface 62, in the case that the single data stream includes graphics data. In the case that the single data stream 52 includes video data, an exemplary formatted output at interface 62 is illustrated in FIG. 3B. FIGS. 3C shows a variation of the formatted output shown in FIG. 3A, in which a dummy color component "X" is inserted (e.g., by replicating the previous color component) between the RGB data. By inserting "X", it allows easy division of the frequency of output formatter 40 to match the frequency of a receiving device, e.g., encoder 26. Similarly, FIG. 3D shows a variation of the formatted outpμt shown in FIG. 3B, with "X" being inserted in between the YUN data.

With regard to the examples in FIGS. 3C and 3D, an oversampled data clock of 2x or even 4x the frequency is possible with implementation of the interface.

FIG. 4A-4D illustrates exemplary formatted outputs at an interface of processor 20 operated in a second operating mode, which is an extension of the first operating mode. The second operating mode utilizes only one interface to transmit two data streams. This interface has to run at a higher clock rate, e.g., 3x, 4x, 6x or 8x pixel clock rate (which is between 13.5 to 75 MHz), but very expensive pins can be saved. In this second operating mode, with reference to FIG. 2, two data streams 52 and 56 are supplied to formatting circuit 46 by pipeline 36, and are formatted by formatting circuit 46 for outputting via a single interface, e.g., interface 62. Each of the two data streams 52 and 56 may again be either graphics data or video data. Exemplary formatted outputs at interface 62 are shown in FIGS. 4A-4D. As will be understood by persons skilled in the art, there are other data, e.g., SAN (start of active video) data, EAN (end of active video) data, etc., which are not illustrated in these figures. FIG. 4A shows an exemplary formatted output when data stream 52 is a graphics data stream and data stream 56 is a video data stream. FIG. 4B shows an exemplary formatted output when both data streams 52 and 56 are graphics data streams. FIG. 4C shows an exemplary formatted, non-subsampled output when both data streams 52 and 56 are video data streams. Finally, FIG. 4D shows an exemplary formatted, sub-sampled output when both data streams 52 and 56 are video data streams.

FIG. 5 illustrates an exemplary formatted output at the interfaces of processor 20 operated in a third operating mode. The third operating mode uses two interfaces to transmit only one data stream. In this third operating mode, with reference to FIG. 2, a single data stream, such as data stream 52, is supplied to formatting circuit 46 by pipeline 36, and is formatted by formatting circuit 46 for outputting via both interfaces 62 and 66. This mode is particularly suitable for transmitting high bandwidth, high definition (HD) digital video data streams. It allows transmission of a subsampled YUN data stream up to full HD resolution clock rates (e.g., 75 MHz).

FIG. 6 shows controller 50 of processor 20 of FIG. 2 according to the present invention. Controller 50 comprises a line sequencer 76 and a component sequencer 78. Line sequencer 76 is a state machine which keeps track of the basic elements of a video line. It is controlled by the synchronization signal H V-Sync coming from pipeline 36. The state machine transitions through four states: HACT (horizontal active area), HBLS (horizontal blank start), HBL (horizontal blanking interval), HBLE (horizontal blanking end). Depending on the current state of line sequencer 76, different control information is sent to component sequencer 78. Component sequencer 78 is another state machine which is responsible for the generation of the proper output format, i.e., the proper multiplex order of the RGB or YUV and the insertion of the SAV and EAV information into the output data stream. Inputs into component sequencer 78 are the control information provided by line sequencer 76 and the output mode specified in a control register (not shown).

FIG. 7 shows a video/graphics processor 100 according to another embodiment of the invention. This embodiment is a variation of processor 20 illustrated in FIG. 2 and may be used in place of processor 20 in the system illustrated in FIG. 1. The detailed descriptions of a pipeline 36 and an output formatter 140 including a data formatting circuit 146 and a controller 150 are omitted for simplicity. In this embodiment, instead of two data streams, there are four data streams 102, 104, 106 and 108 provided by pipeline 36. Furthermore, processor 100 may be operated in a fourth operating mode, in addition to the three operating modes described above. This fourth operating mode utilizes two interfaces 162 and 166 to transmit the four data streams. Each data stream may again be either graphics or video data stream.

FIGS. 8A-8C illustrates exemplary formatted outputs at interfaces 162 and 166. FIG. 8A shows the formatted output when two of the data streams are graphics data streams and the other two data streams are video data streams. FIG. 8B shows an exemplary formatted output when the four data streams are all graphics data streams. FIG. 8C shows an exemplary formatted output when the four data streams are all video streams. Other combinations of the data streams are also possible.

It should be noted that the formatted outputs shown in FIGS. 3A-3D, 4A-4D, 5 and 8A-8C are merely for illustration purposes. The orders of these components of the video/graphics data are not limited to those illustrated, and the components may include other types of data, such as Y, Cr, Cb. Furthermore, the data streams provided by the pipeline may be in oversampled formats. Additionally, the output formatter of the processor may include additional interfaces and may receive additional data streams. While the invention has been described in conjunction with specific embodiments, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, it is intended to embrace all such alternatives, modifications and variations as fall within the spirit and scope of the appended claims.

Claims

CLAIMS:

1. A data formatter (40), comprising: a data formatting circuit (46), having a first interface (62), that is configured to receive a first input stream of digital video/graphics data and format the data for outputting via the first interface; and - a controller (50), operably coupled to the data formatting circuit, that is configured to cause the data formatting circuit to operate in a first operating mode in which the data formatting circuit outputs components of the video/graphics data in a first predetermined serialized format via the first interface.

2. The formatter of claim 1, wherein the first predetermined serialized format includes a non-subsampled format.

3. The formatter of claim 1 , wherein the data formatting circuit is further configured to receive a second input stream of digital video/graphics data and format both the first and second input streams for outputting via the first interface; and wherein the controller is further configured to cause the data formatting circuit to operate in a second operating mode in which the data formatting circuit outputs the components of the two input streams of data in a second predetermined serialized format via the first interface.

4. The formatter of claim 3, wherein the second predetermined serialized format includes a non-subsampled format.

5. The formatter of claim 3, wherein the data formatting circuit includes a multiplexer and outputs the components of the two input streams of data by multiplexing the components of the two streams of data over the first interface.

6. The formatter of claim 3, wherein the components of each of the two input streams of data includes RGB.

7. The formatter of claim 3, wherein the components of each of the two input streams of data includes YUN.

8. A data formatter (100), comprising: a data formatting circuit (146), having first and second interfaces (162, 166), that is configured to receive a first input stream of digital video/graphics data and format the data for outputting via the first and second interfaces; and a controller (150), operably coupled to the data formatting circuit, that is configured to cause the data formatting circuit to output, in one operating mode, components of the video/graphics data in a first predefined format via the first and second interfaces.

9. The formatter of claim 8, wherein the first predefined format includes a subsampled format.

10. The formatter of claim 8, wherein the data formatting circuit includes a multiplexer and outputs the components of the first input stream of data by multiplexing the components of the stream of data over the first and second interfaces.

11. The formatter of claim 8 , wherein the data formatting circuit is further configured to receive second, third and fourth input streams of digital video/graphics data and format the four input streams for outputting in a second predefined format; and wherein the controller is further configured to cause the data formatting circuit to output, in another operating mode, the components of the four input streams of data via the first and second interfaces in a second predefined format.

12. The formatter of claim 8, wherein the second predefined format includes interleaved color components format.

13. The formatter of claim 8, wherein the data formatting circuit includes a multiplexer and outputs the components of the four input streams of data by multiplexing the components of the four streams of data over the first and second interfaces.

14. A processor (20), comprising: a processing pipeline (36) that is configured to receive video/graphics data, process the data and provide a first stream of digital video/graphics data; and a data formatter (40), operably coupled to the pipeline, that comprises: a data formatting circuit (46), having a first interface (62), that is configured to receive the first stream of digital video/graphics data and format the data for outputting via the first interface, and a controller (50), operably coupled to the data formatting circuit, that is configured to cause the data formatting circuit to operate in a first operating mode in which the data formatting circuit outputs components of the video/graphics data in a first predetermined serialized format via the first interface.

15. The processor of claim 14, wherein the pipeline is further configured to provide a second stream of digital video/graphics data; - wherein the data formatting circuit is further configured to receive the second stream of digital video/graphics data and format both the first and second input streams for outputting via the first interface; and wherein the controller is further configured to cause the data formatting circuit to operate in a second operating mode in which the data formatting circuit outputs the components of the two streams of data in a second predetermined serialized format via the first interface.

16. A processor (100), comprising: a processing pipeline (36) that is configured to receive video/graphics data, process the data and provide a first stream of digital video/graphics data; and a data formatter (140), operably coupled to the pipeline, that comprises: a data formatting circuit (146, 150), having first and second interfaces (162, 166), that is configured to receive the first stream of digital video/graphics data and format the data for outputting via the first and second interfaces; and a controller (150), operably coupled to the data formatting circuit, that is configured to cause the data formatting circuit to output, in one operating mode, components of the video/graphics data in a first predefined format via the first and second interfaces.

17. The processor of claim 16, wherein the data formatting circuit includes a multiplexer and outputs the components of the first input stream of data by multiplexing the components of the stream of data over the first and second interfaces.

18. The processor of claim 16, - wherein the pipeline is further configured to provide second, third and fourth streams of digital video/graphics data; wherein the data formatting circuit is further configured to receive the second, third and fourth streams of digital video/graphics data and format the four streams for outputting in a second predefined format; and - wherein the controller is further configured to cause the data formatting circuit to output, in another operating mode, the components of the four streams of data via the first and second interfaces in a second predefined format.

19. The processor of claim 16, wherein the data formatting circuit includes a multiplexer and outputs the components of the four input streams of data by multiplexing the components of the four streams of data over the first and second interfaces.

20. A method, comprising the steps of: receiving a first input stream of digital video/graphics data; - formatting the first input stream of data; outputting, in a first operating mode, components of the data in a first predetermined serialized format via a first interface.

21. The method of claim 20, further comprising the steps of: - receiving a second input stream of digital video/graphics data; formatting the second input stream of data; and outputting, in a second operating mode, the components of the two input streams of data in a second predetermined serialized format via the first interface.

22. A method, comprising the steps of: receiving a first input stream of digital video/graphics data; formatting the first input stream of data; and outputting, in one operating mode, components of the data in a first predefined format via first and second interfaces.

23. The method of claim 22, wherein the step of outputting includes multiplexing the components of the stream of data over the first and second interfaces.

24. The method of claim 22, further comprising the steps of: receiving second, third and fourth input streams of digital video/graphics data; formatting the four input streams of data; and outputting, in another operating mode, the components of the four input streams of data via the first and second interfaces in a second predefined format.

25. The method of claim 22, wherein the step of outputting includes multiplexing the components of the four streams of data over the first and second interfaces.