WO2002033556A3 - Dynamic queuing structure for a memory controller - Google Patents
Dynamic queuing structure for a memory controller Download PDFInfo
- Publication number
- WO2002033556A3 WO2002033556A3 PCT/US2001/029850 US0129850W WO0233556A3 WO 2002033556 A3 WO2002033556 A3 WO 2002033556A3 US 0129850 W US0129850 W US 0129850W WO 0233556 A3 WO0233556 A3 WO 0233556A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- memory
- attributes
- control unit
- service instructions
- memory controller
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
Abstract
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2001293027A AU2001293027A1 (en) | 2000-10-19 | 2001-09-24 | Dynamic queuing structure for a memory controller |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US69230400A | 2000-10-19 | 2000-10-19 | |
US09/692,304 | 2000-10-19 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2002033556A2 WO2002033556A2 (en) | 2002-04-25 |
WO2002033556A3 true WO2002033556A3 (en) | 2003-08-21 |
Family
ID=24780042
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2001/029850 WO2002033556A2 (en) | 2000-10-19 | 2001-09-24 | Dynamic queuing structure for a memory controller |
Country Status (2)
Country | Link |
---|---|
AU (1) | AU2001293027A1 (en) |
WO (1) | WO2002033556A2 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7418540B2 (en) | 2004-04-28 | 2008-08-26 | Intel Corporation | Memory controller with command queue look-ahead |
US20060064535A1 (en) * | 2004-09-22 | 2006-03-23 | Walker Robert M | Efficient multi-bank memory queuing system |
US8327057B1 (en) * | 2007-04-16 | 2012-12-04 | Juniper Networks, Inc. | Ordering write bursts to memory |
JP4746699B1 (en) * | 2010-01-29 | 2011-08-10 | 株式会社東芝 | Semiconductor memory device and control method thereof |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5375215A (en) * | 1990-11-09 | 1994-12-20 | Hitachi, Ltd. | Multiprocessor system having shared memory divided into a plurality of banks with access queues corresponding to each bank |
US5745913A (en) * | 1996-08-05 | 1998-04-28 | Exponential Technology, Inc. | Multi-processor DRAM controller that prioritizes row-miss requests to stale banks |
US6092158A (en) * | 1997-06-13 | 2000-07-18 | Intel Corporation | Method and apparatus for arbitrating between command streams |
-
2001
- 2001-09-24 WO PCT/US2001/029850 patent/WO2002033556A2/en active Application Filing
- 2001-09-24 AU AU2001293027A patent/AU2001293027A1/en not_active Abandoned
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5375215A (en) * | 1990-11-09 | 1994-12-20 | Hitachi, Ltd. | Multiprocessor system having shared memory divided into a plurality of banks with access queues corresponding to each bank |
US5745913A (en) * | 1996-08-05 | 1998-04-28 | Exponential Technology, Inc. | Multi-processor DRAM controller that prioritizes row-miss requests to stale banks |
US6092158A (en) * | 1997-06-13 | 2000-07-18 | Intel Corporation | Method and apparatus for arbitrating between command streams |
Also Published As
Publication number | Publication date |
---|---|
WO2002033556A2 (en) | 2002-04-25 |
AU2001293027A1 (en) | 2002-04-29 |
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