WO2002029581A3 - Configurable differential/single ended i/o - Google Patents

Configurable differential/single ended i/o Download PDF

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Publication number
WO2002029581A3
WO2002029581A3 PCT/US2001/028978 US0128978W WO0229581A3 WO 2002029581 A3 WO2002029581 A3 WO 2002029581A3 US 0128978 W US0128978 W US 0128978W WO 0229581 A3 WO0229581 A3 WO 0229581A3
Authority
WO
WIPO (PCT)
Prior art keywords
mode
single ended
data
differential
received
Prior art date
Application number
PCT/US2001/028978
Other languages
French (fr)
Other versions
WO2002029581A2 (en
Inventor
Brian L Smith
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Priority to AU2001289114A priority Critical patent/AU2001289114A1/en
Publication of WO2002029581A2 publication Critical patent/WO2002029581A2/en
Publication of WO2002029581A3 publication Critical patent/WO2002029581A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Dc Digital Transmission (AREA)

Abstract

A method and mechanism for communicating data in either a single ended or a differential mode on a same data bus. A transmitter is configured to receive a plurality of data bits in a single ended mode and a clock signal. A mode selector indicates whether the received data is to be conveyed in a single ended mode or a differential mode. If the mode selector indicates single ended mode, the received plurality of data bits are conveyed with a differential clock signal corresponding to the received clock signal. If the mode selector indicates differential mode, the transmitter converts the received data to a differential form prior to conveyance. A receiver is configured to receive a plurality of data bits and a clock signal. A mode selector indicates whether the received data is to be received as single ended data or differential data. If the mode selector indicates single ended mode, the received data is conveyed as single ended data. If the mode selector indicates differential mode, the received data is converted from differential form to single ended form and conveyed in single ended mode.
PCT/US2001/028978 2000-10-05 2001-09-17 Configurable differential/single ended i/o WO2002029581A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001289114A AU2001289114A1 (en) 2000-10-05 2001-09-17 Configurable differential/single ended i/o

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US68065900A 2000-10-05 2000-10-05
US09/680,659 2000-10-05

Publications (2)

Publication Number Publication Date
WO2002029581A2 WO2002029581A2 (en) 2002-04-11
WO2002029581A3 true WO2002029581A3 (en) 2003-04-17

Family

ID=24731981

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/028978 WO2002029581A2 (en) 2000-10-05 2001-09-17 Configurable differential/single ended i/o

Country Status (2)

Country Link
AU (1) AU2001289114A1 (en)
WO (1) WO2002029581A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100871711B1 (en) 2007-05-03 2008-12-08 삼성전자주식회사 Multi-phase transmitter/receiver for single-ended signaling and differential signaling and clocking method to convert differential signaling to single-ended signaling
KR20100134285A (en) * 2009-06-15 2010-12-23 삼성전자주식회사 Signal transmitting method, signal transmitting apparatus and signal transmitting system
US11449453B2 (en) * 2020-04-16 2022-09-20 Mediatek Inc. Multi-package system using configurable input/output interface circuits for single-ended intra-package communication and differential inter-package communication

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0482336A1 (en) * 1990-09-25 1992-04-29 National Semiconductor Corporation Switchable transceiver interface device
US5920204A (en) * 1996-12-11 1999-07-06 Lsi Logic Corporation On/off control for a balanced differential current mode driver
US6243776B1 (en) * 1998-07-13 2001-06-05 International Business Machines Corporation Selectable differential or single-ended mode bus

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0482336A1 (en) * 1990-09-25 1992-04-29 National Semiconductor Corporation Switchable transceiver interface device
US5920204A (en) * 1996-12-11 1999-07-06 Lsi Logic Corporation On/off control for a balanced differential current mode driver
US6243776B1 (en) * 1998-07-13 2001-06-05 International Business Machines Corporation Selectable differential or single-ended mode bus

Also Published As

Publication number Publication date
AU2001289114A1 (en) 2002-04-15
WO2002029581A2 (en) 2002-04-11

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