WO2002025800A1

WO2002025800A1 - Switching mode power supply with high efficiency

Info

Publication number: WO2002025800A1
Application number: PCT/KR2001/001603
Authority: WO
Inventors: Joon-Ho Park
Original assignee: Park Joon Ho
Priority date: 2000-09-25
Filing date: 2001-09-25
Publication date: 2002-03-28
Also published as: KR20020024444A; KR100387382B1; AU2001292401A1

Abstract

A Switching Mode Power Supply (SMPS), which can operate at a high switching frequency by preventing any oscillation within a circuit, is provided. The SMPS includes: a power output unit for outputting a 1st power and 2nd power; a switching unit for switching the 2nd power on/off according to a switching signal to output a square wave signal having the 2nd power level and a frequency of the switching signal; an inverter for receiving the square wave signal having the 2nd power level and amplifying it to a square wave signal having the 1st power level; and an output rectifying unit for rectifying the square wave signal output from the inverter and outputting DC power. Since the SMPS provides V1 and V2, to a main power amplifier (output side of the power transformer) and a switching frequency oscillator (PWM control circuit), respectively, no oscillation happens even when a switching frequency increases and thus high efficiency can be obtained.

Description

SWITCHING MODE POWER SUPPLY WITH HIGH EFFICIENCY

Technical Field

The present invention relates to a Switching Mode Power Supply (SMPS), and more particularly, to an SMPS that can operate at a high switching frequency by preventing any oscillation within a circuit.

Background Art

A Switching Mode Power Supply (SMPS) designer has attempted to not only reduce the size of a transformer as much as possible by increasing a switching frequency (fs) but also decrease energy loss caused by coil resistance by reducing the number of coil turns. In an existing circuit configuration, if a switching frequency exceeds 100 KHz, oscillation is generated and the voltage applied across a load connected to an output terminal is attenuated. That is, original input power is not fully transmitted to the output terminal of the power supply.

Disclosure of the Invention

To solve the above-described problems, it is an object of the present invention to provide various types of Switching Mode Power Supplies (SMPSs) with high efficiency, in which power supplied to a switching frequency oscillator is isolated from power supplied to a main power amplifier in a converter circuit and thus no oscillation generates even when a switching frequency increases.

It is another objective of the present invention to provide a rectifier with a simple configuration for converting AC power used as an input to the power supply into DC input power.

To achieve the objective, a 1^st SMPS according to the present invention includes: a power output unit for outputting a 1^st power and a 2^nd power; a switching unit for switching the 2^nd power on/off according to a switching signal to output a square wave signal having the 2^nd power level and a frequency of the switching signal; an inverter for receiving the square wave signal having the 2^nd power level and amplifying it to a square wave signal having the 1^st power level; and an output rectifying unit for rectifying the square wave signal output from the inverter and outputting DC power.

To achieve the objective, a 2^nd SMPS according to the present invention includes: a power output unit for outputting a 1 ^st power and a 2^nd power; a switching unit for switching the 2^nd power on/off according to a switching signal to output a square wave signal having the 2^nd power level and a frequency of the switching signal; and an inverter having a 1^st switching element which switches on when the voltage of the received square wave signal having the 2^nd power level is positive and outputs a positive voltage signal of the 1 ^st power level, and a 2^nd switching element which switches on when the voltage of the received square wave signal having the 2^nd power level is negative and outputs a negative voltage signal of the 1^st power level, for outputting the square wave signal having the 1 ^st power level. To achieve the objective, a 3^rd SMPS according to the present invention includes: a power output unit for outputting a 1^st power and a 2^nd power; a switching unit for switching the 2^nd power on/off according to a switching signal to output a square wave signal having the 2^nd power level and a frequency of the switching signal; and an inverter having an upper output unit and a lower output unit that switch on/off alternately depending on the logic level of the square wave signal, for setting up a current path through (+) terminal of the 1 ^st power, the upper output unit and a middle tab terminal of the 1 ^st power which forms an output terminal sequentially or through the middle tab terminal of the 1^st power, the lower output unit and (-) terminal of the 1^st power, sequentially and for amplifying the received square wave signal having the 2^nd power level into a square wave signal having the 1^st power level.

To achieve the objective, a 4^th SMPS according to the present invention includes: a power output unit for outputting a 1 ^st power and a 2^nd power; a switching unit for switching the 2^nd power on/off according to a switching signal to output a square wave signal having the 2^nd power level and a frequency of the switching signal; and an inverter having a 1 ^st output unit through a 4^th output unit that switch on/off alternately according to the logic level of the square wave signal, for setting up a current path through (+) terminal of the 1 ^st power, the 1^st output unit, an output terminal, the 4^th output unit and (-) terminal of the 1^st power, sequentially, or through (+) terminal of the 1 ^st power, the 2^nd output unit, the output terminal, the 3^rd output unit and (-) terminal of the 1^st power sequentially, and for amplifying the received square wave signal having the 2^nd power level into a square wave signal having the 1 ^st power level.

To achieve the objective, a 5^th SMPS according to the present invention includes: a power output unit for outputting a 1 ^st power and a 2^nd power; a switching unit for switching the 2^nd power on/off according to a switching signal to output a square wave signal having the 2^nd power level and a frequency of the switching signal; and an inverter having an upper output unit and a lower output unit that switch on/off alternately according to the logic level of the square wave signal, for setting up a current path through (+) terminal of the 1 ^st power, the upper output unit and (-) terminal of the 1^st power, sequentially, or through (+) terminal of the 1^st power, the lower output unit and (-) terminal of the 1 ^st power, sequentially, and for amplifying the received square wave signal having the 2^nd power level into a square wave signal having the 1 ^st power level. To achieve another objective, a rectifier according to the present invention includes: at least two rectifying units, each rectifying unit comprising: an AC input unit for receiving AC power, clamping excessive input voltage to the safe level voltage and blocking excessive current of the input power; a current path setup unit for determining the path of current according to the phase of the input AC power; and an output unit that charges current flowing along the path determined by the current path setup unit and generates DC voltage The rectifying units have substantially the same internal configurations and generate the same voltage, and (+) and (-) output terminals of each rectifying unit are commonly connected to the (+) and (-) output terminals of other rectifying units respectively.

Brief Description of the Drawings

FIG. 1 is a block diagram showing an overall configuration of a Switching Mode Power Supply (SMPS);

FIGS. 2A and 2B are circuit diagrams showing the configuration of an input rectifier 1 1 shown in FIG. 1 ; FIGS. 2C and 2D are diagrams showing the input rectifier 1 1 of FIG. 2B in modular forms;

FIG. 2E shows another configuration of a low voltage generator 25 shown in FIG. 2A;

FIG. 3A is a circuit diagram showing a basic configuration of an inverter operating in a switching mode;

FIG. 3B is a timing diagram describing the operation of each part of the circuit shown in FIG. 3A;

FIG. 3C shows one example of the configuration of a PWM control circuit 31 shown in FIG. 3A; FIG. 4A is a more detailed circuit diagram of M1 in which supplementary elements are added to the transistor (Q2) of the output unit shown in FIG. 3A;

FIG. 4B is a more detailed circuit diagram of M2 in which supplementary elements are added to the transistor (Q3) out of the output unit shown in FIG. 3A;

FIG. 4C shows the circuit (M3) where the circuits shown in FIG. 4A are connected in parallel;

FIG. 4D shows the circuit (M4) where the circuits shown in FIG. 4C are connected in parallel;

FIG. 5A is a circuit diagram of a half bridge SMPS (Switching Mode Power Supply); FIG. 5B shows a detailed configuration of each output module (M1 1 ) included in the output rectifying units 57A and 57B of FIG. 5A;

FIG. 5C shows another configuration of a half bridge inverter of the SMPS circuit shown in FIG. 5A;

FIG. 5D shows a circuit diagram of a full bridge inverter; FIG. 5E shows an example of an output rectifying unit which is used to be connected to the bridge-type inverter shown in FIGS. 5A, 5C or 5D;

FIG. 5F shows an example of an output rectifying unit (57g) which is used to be connected to the bridge-type inverter shown in FIGS. 5A, 5C or 5D;

FIG. 6A shows the configuration of a push-pull SMPS; FIG. 6B shows another configuration of a push-pull inverter of the SMPS circuit shown in FIG. 6A;

FIG. 6C shows an example of an output rectifying unit which is used to be connected to the push-pull inverter shown in FIG. 6A or 6B; and

FIG. 6D shows another example of the output rectifying unit (67a) shown in FIG. 6A.

Best mode for carrying out the Invention

The present invention will now be described in detail by describing preferred embodiments thereof with reference to the accompanying drawings. FIG. 1 is a block diagram showing an overall configuration of a Switching Mode Power Supply (SMPS). When an input rectifier 11 receives AC power, it generates two DC powers (Vi and V₂). Then, the input rectifier 11 outputs Vi and V₂ respectively to an inverter 14 and a switching circuit 12. V-i, a high voltage DC power, determines the level of the output voltage of the inverter 14. V₂ is provided to the switching circuit 12. If a circuit (for example, a DC/DC converter shown in FIG. 2E) is added to the circuit shown in FIG. 1 , more stable and lower voltage (for example, 12 or 15 VDC) can be generated. An output unit of the SMPS includes the inverter 14, a power transformer 15 and an output rectifier 17. The switching circuit 12 operates at a pre-defined frequency and chops an input DC signal V₂ as a high frequency square wave. The square wave signal is provided to the inverter 14 through the drive transformer 13 and amplified into a high voltage power (Vi) and fed into the power transformer 15 to be attenuated to a pre-defined value depending on the coil winding ratio. The inverter 14 generates a square wave having the electric potential of Vi with the frequency of the square wave generated by the switching circuit 12.

The current feedback unit 18 detects the output current of the inverter 14 and feeds it back to the switching circuit 12. In addition, the final output voltage signal (V_out) of the output rectifier 17 is fed back to the switching circuit 12. The switching circuit 12 compares the feedback signals with a reference signal, and adjusts (PWM control) the level (magnitude) of the voltage and the current by adjusting the pulse phase of the switching signal. By doing so, the switching circuit 12 keeps V_out of the SMPS regular. The power transformer 15 adjusts the voltage of the high voltage square wave signal generated by the inverter 14 and the output rectifier 17 rectifies the adjusted square wave signal to generate DC power.

FIGS. 2A and 2B are circuit diagrams showing the configuration of an input rectifier 11 shown in FIG. 1. As shown in FIG. 2A, the input rectifier includes an AC input unit 21 , a high voltage generator 23 and a low voltage generator 25. The AC input terminal is connected with a barrister (Z-i), capacitors (Cn, Cι₂, Cι₃) and inductors (L-i, L₂) used to clamp excessive input voltage to make a safe level voltage, block excessive current of the input power and eliminate noise. The bridge diodes (BRi, BR₂) determine the current flow depending on the phase of the AC power and convert AC into DC. The switch (S1 ) selects AC input voltage (110V or 220V). The high voltage generator 23 includes thermistors (TH) whose resistance is reduced as the temperature becomes higher. The high voltage generator maintains the resistance of the thermistors regular irrespective of the current and prevents the instantaneous transient current of capacitors (Cι, C₂) for filter from damaging the circuit. The current flow through the diode (BRi) is determined depending on the phase of the input AC power, and the high voltage Vi is generated by the charging of the capacitors (Ci, C₂). The low voltage generator 25 generates the DC low voltage V when the diode is in a forward direction and the capacitors are charged.

FIG. 2B shows an AC-to-DC rectifier which can handle a high current and includes multiple rectifiers, wherein high voltage generators 23, the same as that shown in FIG. 2A, are configured in parallel and input terminals and output terminals are connected respectively in parallel. The bridge diode (BRi) of the high voltage generator 23 shown in FIG. 2A generates more heat as the operating current becomes larger and requires heatproof planes. In addition, capacitors with high capacitance are required, thus the size of the circuit is large.

As shown in FIG. 2B, the configuration of each module is substantially the same as that of the high voltage generator shown in FIG. 2A. Since the input terminals and the output terminals of modules are connected respectively with each other in parallel, the total output capacity can increase. For example, in case a 500 VA rectifier is designed, 10 modules of 50VA rate should be connected in parallel. Then, because the total input current is distributed to each module, the power loss of each module can be reduced. That is, since power loss is in proportion to the resistance and the square of the current, when n modules each having same resistance (R) are used, the power loss (Ploss) is calculated as follows. I , Rl²

/?_ = Λ x (-)- ^χ » = —

That is to say, if the entire operating current is regular and n modules having the resistance (R) are used, the power loss can be reduced by 1/n when compared to the use of one module having the resistance (R). Therefore, the efficiency of the SMPS can be enhanced.

The output filter 27 connected to the output terminal of each module is a pi-type (TT ) low pass filter including capacitors (CFn ~ CF₁₄) and the inductor (LF-i). The output filter removes the 2^nd, the 3^rd and higher harmonic noises generated by the switching with high frequency. Since the capacitor and the inductor used in this circuit have low current ratings, the size of the capacitor and the inductor core can be small and power loss is reduced.

The parallel-connected rectifier shown in FIG. 2B has multiple rectifier modules (AC to DC) each of which is for low current, is connected in parallel each other and has the same configuration. In the parallel-connected rectifier, the input power is distributed by 1/n to each module. Therefore, since the current rating needed by each module becomes lower, sizes of the electrical elements used in the module, such as capacitors and the inductor, can be reduced. In addition, heat generated by the bridge diode is reduced and additional heatproof planes are not needed. As a result, as shown in FIG. 2C, if the modules (Mi ~ M_n) are embodied in integrated circuits respectively and are connected in parallel, a rectifier for high power can be implemented. In an economical point of view, multiple rectifiers for low power connected in parallel are far more cost-effective (about 30 ~ 50%) than a single rectifier for high power. FIG. 2D is another implementation example of the modules shown in FIG. 2C. One or more layers of modules placed side by side are formed and the layers of multiple modules are connected in parallel to construct a single rectifier using a less space. In addition, the parallel-connected rectifier shown in FIG. 2B can be applied to a device which converts 3-phase AC input to DC power.

FIG. 2E is a circuit diagram showing the DC/DC converter connected to the output terminal of the low voltage generator 25 shown in FIG. 2A, which can obtain lower and more stable voltage power. The input DC power (Vj_n) is the output voltage (V₂) of the low voltage generator 25 shown in FIG. 2A. In FIGS. 3 through 6, the power fed as a switching power is the output power (V_out) of the circuit shown in FIG. 2E. For easy understanding, the low voltage power shown in each of FIGS. 3 through 6 will be marked as V₂.

In the embodiment shown in FIG. 2E, a transistor (Qi) operates as a switching element that is turned on or off in response to the switching signal generated by a PWM control circuit 31. A transformer (Ti) receives a high frequency square wave to the 1^st coil (N_p) which is connected between the input DC power (Vj_n) and the transistor (Qi) in response to the on/off switching of the transistor (Qi) and transforms it to provide the transformed power to the 2^nd coil. An input current detector 33 detects the current flowing through the 1^st coil of the transformer (Ti) depending on the on/off switching of the transistor (Qi) and feeds it back to the PWM control circuit 31. The PWM control circuit 31 controls the on/off duration of a switching signal (SW_0Ut) depending on an error signal generated as a result of the comparison between the reference signal and the output DC power signal +FB and a voltage level of the input current (which changes in line with the change of the input voltage V_in) detected by the input current detector 33, and controls the amount of current flowing in the 1^st coil. Rectifiers (37a, b, c) are connected to the 2^nd coil of the power transformer (Ti), convert AC power to DC power and output one or more regular voltages.

In the embodiment shown in FIG. 2E, the circuit for switching includes the PWM control circuit 31 for switching signal generation, the transistor (Qi), the transformer (Ti) for voltage drop and the transformer (T₂) for current detection. The transistor (Qi) is switched on/off by the square wave switching signal (SW_0Ut) generated by the PWM control circuit 31. While the transistor (Q-i) is turned on, current is charged in the 1^st coil of the transformer (Ti). Then, when the transistor (Qi) is turned off, the current charged in the 1^st coil is transmitted to the 2^nd coil. Depending on the winding ratio of the transformer (Ti), voltage is fed to both terminals of the 2^nd coil.

The input current detector 33 is positioned between a source terminal of the transistor (Qi) and the (-) terminal of V_ιn and feeds the signal (generated depending on the current when the transistor (Qi) is ON) back to the PWM control circuit 31 . The input current detector 33 senses the current change in line with the electric potential change of the input voltage (V|_n) or the input current change in line with the change of the output load, and feeds it to the PWM control circuit 31. To compensate for the current change, the PWM control circuit 31 controls the switching operation depending on the sensed signal. The input current detector 33 detects that the current (l_pp) changes as the input voltage (Vm) or the output voltage changes, converts the detected current into the voltage signal and feeds it back to the PWM control circuit 31. The PWM control circuit 31 reflects the variation of the input voltage (V,_n) or the output voltage and adjusts the pulse duration of the positive phase of the switching signal (SWout) so that the output voltage can be maintained regular. If the current (l_pp) increases, the current sensing voltage detected by the input current detector 33 and fed back to the PWM control circuit 31 also increases. Then, the PWM control circuit 31 adjusts the pulse duration of the switching signal (SW_0Ut) based on the current sensing voltage so that the current (l_pp) can be reduced. If the transistor (Qi) is ON, current is induced in the 2^nd coil by the current flowing through the 1^st coil of the current-coupling transformer (T₂). A resistance (R1 ) converts the current induced in the transformer (T₂) into the voltage signal. The voltage fed to a sensing terminal (SENSE) is determined based on the adjustment of the resistance value of a variable resistance (R₂). Capacitors (C₂, C₃) are used to remove ripples and noises, and a diode (D₂) is used to convert/rectify the detected square wave signal into the DC signal. When the current-coupling transformer (T₂) detects the change of the current flowing through the 1 ^st coil of the transformer (TO, since the 1 ^st side and the 2^nd side of the transformer (T₂) are isolated, a circuit for switching with high frequency can be configured. It is preferable that the ratio between the 1 ^st coil and the 2^nd coil of the transformer (T₂) is about 1 :50 ~ 200. For example, in the case of an SMPS for less than 10 W, when the continuous current (IPDC) flowing the 1 ^st coil of the main transformer (Ti) is 1 .0 A or less, it is preferable that the ratio between the 1 ^st coil and the 2^nd coil of the transformer (T₂) is 1 : 100. In addition, preferably, the material of the core of the transformer (T₂) is the same as that of the core of the main transformer (T-i).

The PWM control circuit 31 receives the output voltage signal (+FB) of the converter and the sensed voltage signal (SENSE) generated by the input current, and generates the square wave pulse for controlling on/off switching of the transistor (Qi). For more details on the configuration, FIG. 3C should be referred to.

A self-bias circuit 35 provides the operation power to the unit for outputting the switching signal (SW_0Ut) among the PWM control circuit 31. The current induced by an auxiliary coil (N_FB) of the 1 ^st side of the power transformer (Ti) is provided to the Vcc terminal of the PWM control circuit 31 through a diode (D1 ). Here, a capacitor (Ci) is used to remove ripples. The input power (Vι_n) is provided to elements within the PWM control circuit 31 other than the switching output unit. FIG. 3A is a circuit diagram showing the basic configuration of a bridge inverter or a push-pull inverter operating in a switching mode. The inverter receives the DC power (V-i , V₂) from the input rectifier 1 1 shown in FIG. 1 and generates the high voltage, high frequency square wave signal. In addition, the inverter converts a single square wave signal generated by the PWM control circuit 31 into two conjugate square wave signals. In the circuit configuration, the transformer (T converts the single square wave signal into two square waves with a 180 degree phase difference and can output a wave form that has little dead time. FIG. 3B is a timing diagram describing the operation of each part shown in FIG. 3A. Vi and V₂ are output by the input rectifier 1 1 shown in FIG. 1 . Vi is a DC power of high voltage and, as a power for amplification, determines the voltage level of the output signal ("high voltage power"). V₂ is provided to the 1^st side of the drive transformer (T and the PWM control circuit 31 , and is used to generate the square wave signal by the switching operation ("switching power").

The transistor (Q-i) operates as a switching element that is turned ON/OFF depending on the switching signal output by the PWM control circuit 31. The transformer (Ti) receives AC power on the 1^st coil connected between the transistor (Q1 ) and the input DC power (V₂) by on/off switching of the transistor (Q1 ), and provides the power to the 2^nd coil. The PWM control circuit 31 receives the output DC power (+FB) and generates the switching signal (SW_0Ut) by PWM-controlling depending on a difference signal generated as a result of comparison between the +FB and a reference signal. In addition, the sensed signal (SENSE), obtained after the current change caused by the change of the output load is sensed, is fed back to the PWM control circuit 31. The PWM control circuit 31 generates the switching signal (SW_0Ut) by reflecting the sensed signal.

The switching element is the transistor (Qi), switches on/off depending on the logic level of the switching signal (SW_0Ut) of the PWM control circuit 31 and switches on/off the current flowing the 1^st coil (N_p) of the power transformer (Ti). The current flowing the 1^st coil (N_p) of the transformer (TO, depending on on/off of the switching transistor (Qi), induces current into the 2^nd coil and the voltage is introduced to both ends of the 2^nd coil depending on the winding ratio. The square wave signal generated by the switching transistor (Qi) is transmitted to the 2^nd coil through the transformer (Ti) and input to gate terminals of two field effect transistors (Q₂, Qs)- The square waves fed to each field effect transistor (Q₂, Q3) have different poles. Therefore, the transistors (Q₂, Q₃) are alternatively turned on/off. The two transistors (Q₂, Q₃) amplify the input square wave signals. At the contact point between a source of the transistor (Q₂) and a drain of the transistor (Q₃), a square wave signal of high voltage (V-i) whose frequency is substantially the same as that of the input square wave signal is generated. When the transistor (Q-i) is selected, the following should be considered. It is preferable that the input gate capacitance of the transistor has a low value (example: 350 pF) and the internal resistance (RD_S(OΠ)) thereof has a low value (example: 0.3 Ohms or less). Then, power loss can be reduced.

The circuit diagram shows that the 1^st coil of the transformer (TO includes a primary coil (N_p) and an auxiliary coil (N_τ). The auxiliary coil (N_τ) stores energy while the switching transistor (Q0 is off, and returns the stored energy to the output side when the transistor (Q0 is switched on. That is, the auxiliary coil transfers the energy of the low-level signal (down part of the square wave) to the output side and thus increases the off signal level. Therefore, the auxiliary coil can provide the gate signal sufficient enough to turn the transistor (Q₃) on during the down part of the square wave. On the contrary, the primary coil (N_p) stores energy while the transistor (Q0 is on and provides the energy to the output side to turn the transistor (Q₂) on when the transistor (Q0 is off.

The primary coil (N_p) and the auxiliary coil (N_τ) are winded to have reversed poles. An ultra fast diode is used as D1 , which is positioned between the primary coil (N_p) and the auxiliary coil (NT) or between the auxiliary coil (N_τ) and the (-) terminal (-V ), and determines the direction of the current while the switching transistor (Q0 is off. The thickness and the number of turns in the auxiliary coil (NT) should be substantially the same as those of the primary coil (N_p).

Two transistors (Q₂, Q₃) are connected to the 2^nd coil of the transformer (TO- The drain of the transistor (Q₂) is connected to the (+) terminal of the high voltage power (Vi). The source of the transistor (Q₃) is connected to the (-) terminal (-Vi). The source of the transistor (Q₂) and the drain of the transistor (Q₃) are joined to form an output terminal.

FIG. 3B shows the operation status of the transistors (Q₂, Q3) depending on the switching signal generated by the PWM control circuit 31 , and the final output waveform (V_out) as well as the output waveform according to existing technology. Whenever the operation of the transistor (Q0 is switched on/off, 2^nd coils (Nsi, Ns₂) of the power transformer (TO generate square waveform signals which are 180° out of phase. The signals are fed to the gate terminals of transistors (Q₂ and Q₃) of the output side. At the output terminal, a square wave, which has the same frequency as the input square wave signal and a high voltage level V-_\ is generated. Referring to the output signal of the existing technology, the PWM control circuit generates a totem pole signal with a phase difference of 180 degrees and at least 20% dead time. Therefore, since the power is lost during the dead time, the efficiency of the existing technology is limited to maximum of 80%.

However, according to the present embodiment of the present invention, the auxiliary coil (N_τ) of the drive transformer (TO has the same number of turns as the basic winding (N_p), but the polarity of the auxiliary coil is opposite to that of the primary coil. Therefore, when the transistor (Q0 is turned on, the energy is charged in the coil and when the transistor is turned off, the charged current is provided to the gate input capacitance of the transistor (Q₃) to facilitate the turn-on of the transistor (Q₃). The current charge in the gate input capacitance of the transistor (Q₂) is executed by the energy stored in the 1^st coil (N_p) when the transistor (Q0 is turned on. Therefore, there is no dead time in the output signal, and thus the efficiency is high and ripples are small.

The design of the transformer (TO will be described below in detail. First, the output power (P_out) of the transformer (TO is shown below. P_0U n V_GS I_g)

Here, n is the number of transistors, V_Gs is the gate input voltage of each transistor, and Ig is the charged current (the current at the time when the transistor is turned on) of the capacitance between the gate and the source of the transistor.

^{s GS} dt ^RSS dt C ^OS - C ^ISS - C ^RSS dV_GS = 2 x V_GS (peak gate voltage) 1 dt = — - (switching time)

^ J s dV_DS = ^„_(max) (maximum input voltage between the drain and the source of the transistor)

If the transistors are connected to the output side of the transformer (TO in parallel, the power necessary to operate the transistors is the output power (P_out).

The peak current (l_pp) and the continuous current (l_PDc) flowing through the 1 ^st coil of the transformer (TO are calculated as follows. 2E.

I. = ^pp n I V m(mιπ) D max

PDC r 0.4

The power loss of the transistor (Q0 is

¹ p T OSS - ~ ^ RDS(on) x ^{Λ 1}7 P²DC

The inductance (Lp) of the 1 | St coil of the drive transformer (TO is calculated as follows.

γ _ V ιn(mιn) D max f

Here, Vj_n(min) is the lowest input voltage of the transistor (Q0, D_max is the maximum amplitude (0.45) of the square wave, I_PP is the peak current flowing through the 1 ^st coil of the transformer (TO and fs is the switching frequency.

The size of the core used in the transformer (TO is determined as follows.

Here, A_e is an effective area (cm²) of the core, A_c-is the total area (cm²) of the coil, Lp is the inductance of the 1^st coil, l_pp is the peak current in the 1 ^st coil, D is the diameter of the coil, and B_max = 1/2 x B_sat- The actual size of the coil should be more than the calculated value x 1.5. If the volume of the core is small, saturation of the core causes the output voltage to be low and the transient current may lead to unstable operation of the converter. The air gap (l_g) assigned to the transformer (TO, which is designed to prevent the saturation of the core, can be calculated as follows.

The number of turns in the 1^st coil (N_p), the auxiliary coil (N_τ) and the 2^nd coils (N_si, N_S2) of the transformer (TO can be calculated as follows The number of turns in the feedback coil (NFB) should be the same as in the 1^st coil (N_p).

„ _ B max I g _ _ E p E pp x 10^s

A e B m²ax °' A e B m²ax

N_τ = N_P

N_p x 24 x V_GS x 055 r_s2 = ^_(min) * 045

N_F v_GS

It is assumed that VF is 6.6 V.

The output voltage (+FB) of the converter and the sensed voltage (SΕΝSΕ) generated by the inverter output current are fed back to the PWM control circuit 31.

Then, the PWM control circuit generates the square wave pulse for on/off operation of the switching element (Q0- The configuration of the PWM control circuit will be described in more detail with reference to FIGS. 4A through 4D.

The self-bias circuit 35 provides the operation power to the unit for outputting the switching signal (SW_0Ut) within the PWM control circuit 31. The voltage induced by the feedback coil (ΝFB, the pole indication (dot; mark of the start point of the coil of Ν_FB) is opposite to that of the primary coil (N_p)) of the 1^st side of the power transformer (TO is supplied to the Vcc terminal of the PWM control circuit 31 through the diode (D1 ). The capacitor (CO is used to remove ripples. The input power (V_in) is provided to the elements within the PWM control circuit 31 other than the switching output unit. FIG. 3C shows an embodiment of the configuration of the PWM control circuit 31 shown in FIG. 3A and describes a current-mode control method. Vcc induced by the 1^st feedback coil (NF_B) of the power transformer (TO provides power to an amplifier 45 that outputs the switching signal (SW_0Ut). A clock generator 43, a flip-flop 44, an error amplifier 41 and a comparator 42 receive the input power (V₂) fed from a regulator 47 as operating power.

The error amplifier 41 compares the output signal (+FB) and the reference voltage (V_ref), and outputs an amplified error signal. The error signal is input to the comparator 42. The output current of the inverter is sensed and converted into voltage signal. Then, the sensed signal (SENSE) is input to the comparator 42. The comparator 42 compares the sensed signal depending on the peak switch current and the error signal related to the output signal, and inputs the comparison result to the RS flip-flop (latch, 44). The clock generator 43 generates the clock signal which is the square wave signal corresponding to the switching frequency (fs). The RS flip-flop 44 receives the output of the comparator 42 and the clock signal, and generates the switching signal (SW_0Ut) that makes the switching element transistor turn on/off depending on the logic level of the switching signal.

The main output voltage (+FB) fed back by the final output terminal is compared with the reference voltage (V_ref) by the error amplifier 41. The current feedback signal (SENSE) is compared with the reference voltage (1.2V) by the comparator 42. Then, the comparison result is input to the flip-flop 44. The flip-flop 44 increases/decreases (that is to say, generating the pulse-width-modulated signal in which the duty cycle of the clock signal is modified) the phase of the clock signal generated and input by the oscillator 43 depending on the output signal of the comparator 42, to generate the switching signal (SW_0Ut) and thus increases/decreases the current flowing in the transformer (TO depending on the change of the input voltage and the load so that the output voltage of the final output terminal can be maintained regular.

FIG. 4A is a more detailed circuit diagram of M1 , showing supplementary elements are added to the transistor (Q2) of the output unit shown in FIG. 3A. M1 includes the basic configuration of the upper output unit of FIG. 3A, an RC snubber circuit and an electric discharger. The circuit (M1 ) receives the square wave signal transmitted by the 1^st coil of the power transformer (TO, and the transistor (Q₂) is turned on/off under the control of the square wave signal whose level is changed in line with the winding ratio.

If the transistor (Q₂) is turned off, the electrical charge charged in the capacitance (Coss) between the drain and the source, which is the electrical

- charge accumulated while the transistor (Q₂) is turned on, is charged in the capacitor (Cd2) through the diode (Dd2). When the transistor (Q₂) is turned on, the electrical charge charged in the capacitor (Cd2) passes through the resistance (Rd2) and heat is emitted. Therefore, while the transistor (Q₂) is on, since the electrical charge by the capacitance (Coss) between the drain and the source is emitted by the resistance (Rd2), impact on the transistor (Q₂) is minimized and the heat generated from the transistor (Q₂) during the switching operation can be drastically lowered.

A resonance circuit is formed by the leakage inductance of the 1^st coil of the power transformer (TO for high frequency and the capacitance (C_GS) between the gate and the source of the transistor (Q₂) during the turn-off. The resonance circuit causes a transient over-voltage ringing in the transient status. The ringing may have an amplitude large enough to destroy the diode or the transistor during the turn-off period. The RC element including the resistance (R_s2) and the capacitor (C_S2) is a snubber circuit and prevents the ringing. In addition, the RC element is connected in parallel to the 2^nd coil of the power transformer (TO-

The gate resistance (R_g) connected to the gate terminal of the transistor (Q₂) is added to match the rising time of the square wave transmitted from the power transformer (TO and that of the transistor (Q₂). When it is assumed that the rising time of the input square wave is t_r and the capacitance between the drain and the source of the transistor is Cj_SS, the gate resistance (R_g) is calculated as follows. t„

R =

2.2C

FIG. 4B is a more detailed circuit diagram of M2, showing supplementary elements are added to the transistor (Q3) of the output unit shown in FIG. 3A. M2 includes an RC snubber circuit and an electric discharger as well as the basic configuration of the lower output unit of FIG. 3A. Since M2 is the same as M1 in terms of configuration except for the reverse pole indication (dot) of the 2^nd coil, a detailed explanation will be omitted.

FIG. 4C shows a circuit (M3) made up of a plurality of the circuits (M1 ) shown in FIG. 4A connected in parallel. As shown in FIG. 4C, since the current flowing in one transistor of M1 is distributed to multiple transistors, the amount of current flowing in each transistor is small. The RC snubber circuit is connected to each transistor (Qi, Q₂), and the electric dischargers 58 and 59 are located between the drain and the source of the respective transistors (Qi, Q₂). That is, the upper output unit of the 2^nd coil of the power transformer (TO is connected with multiple transistors (Q_{1 (} Q₂, ...) in parallel (drains are connected with their counterparts and sources are also connected with their counterparts), and each transistor includes the electric discharger and the emitted heat of each resistance (R_d) can be reduced.

In each module (571 , 572, ..) including the transistor and the snubber circuit, all the transistors (Qi, Q₂, ..) are turned on or off simultaneously. While the transistors (Q^ Q₂, ..) are turned on, the electric charge charged by a capacitance between the drain and the source is discharged by the electric dischargers (58, 59, ) connected to each transistor. If high power is required, more than 6 modules can be connected in parallel in order to minimize the power loss by the transistor in the output unit (and thus minimize the amount of heat emitted by the transistor). In that case, it is possible for several modules to share one electric discharger. Then, the size of the module including many circuit elements can be kept small and power loss can be minimized. Likewise, based on the same concept applied to M3 shown in FIG. 4C, in the lower output unit 53 shown in FIG. 3A, multiple transistors can be connected in parallel to form a circuit module (M4) shown in FIG. 4D. Since M4 is the same as M3 in terms of configuration except for the reverse pole (dot) indication of the 2^nd coil, a detailed explanation will be omitted.

As described in the above embodiment, the transistor groups (M3) operate during the positive phase of the square wave and the transistor groups (M4) operate during the negative phase of the square wave. When the square wave is input to gates of transistors, the current flowing in each transistor is reduced to 1/n and power loss is lowered. Therefore, even with no additional heat sink, the transistors can operate in a stable manner. FIG. 5A is a circuit diagram of a bridge SMPS for high voltage and high power. Since the configuration of the circuit including the 1^st coil of the transformer (TO is substantially the same as that shown in FIG. 3A, the diagram and the explanation thereof will be omitted here. FIG. 5A is a detailed circuit diagram of the blocks shown in FIG. 1 and the relations between elements in FIG. 5A and FIG. 1 are as follows: drive transformer (13; TO, inverter (14; 51 , 53), output transformer (15; T₃), output rectifier (17; 57a, b) and current feedback unit (18; 55).

The configuration of the inverter connected to the 2^nd coil of the transformer (TO is as follows. The inverter includes an upper (UP) output unit 51 and a lower (DOWN) output unit 53. Each output unit includes multiple circuit modules (M1 or M2). All the (a) terminals of the modules (M1 ) in the upper output unit 51 (the drains of the transistors) are connected together and to a high voltage (+V0- All the (b) terminals of the modules (M1) (the sources of the transistors) are connected together to form an output terminal (S) of the inverter. All the (d) terminals of the modules (M2) of the lower output unit 53 (the sources of the transistors) are connected together and to a (-) terminal of a high voltage power -Vi. All the (c) terminals of the modules (M2) (the drains of the transistors) are connected with all the (b) terminals of the modules (M2) of the upper output unit 51 to form the output terminal (S) of the inverter.

If the switching transistor (Q0 connected to the PWM control circuit 31 is turned on, transistors of the upper output unit 51 are turned on and transistors of the lower output unit 53 are turned off. Then, current flows from the (+) terminal of the high voltage +Vι to a middle tab. On the contrary, if the switching transistor (Q0 is turned off, the transistors of the upper output unit 51 are turned off and the transistors of the lower output unit 53 are turned on. Then, current flows through the middle tab of the high voltage Vi, transformers (T3, T2), transistors of the lower output unit 53, and (-) terminal of the high voltage -V_{1 ;} sequentially. That is, the square wave signal having the high voltage level is transmitted to the output transformer (T3) depending on on/off switching of the transistor (Q0-

The inverter connected to the 2^nd coil of the drive transformer (TO is configured and operated in the same way as that shown in FIG. 3A. In the upper output unit 51 and the lower output unit 53, multiple M1 s and M2s (shown respectively in FIGS. 4A and 4B) are connected in parallel (or the upper output unit 51 and the lower output unit 53 are replaced by M3 and M4 shown in FIGS. 4C and 4D), and then multiple transistors included in each output unit are connected in parallel. Since the current flowing in each transistor is reduced to 1/n (n is the number of transistors used in each output unit), power loss caused by the internal resistance (RD_S(_OΠ)) between the drain and the source of the transistor can be minimized. In addition, the heat generated by each transistor can be minimized and an additional heatproof plane is not necessary for stable operation. If the switching frequency of the inverter becomes higher, the power loss by the capacitance between the drain and the source of each transistor (MOSFET) also increases. In order to reduce the power loss, the snubber circuit including the diode (Dd), the capacitor (Cd) and the resistance (Rd) is positioned between the drain and the source of the transistor in each output unit (Refer to 4A, 4B, 4C and 4D.). Therefore, the power loss by the capacitance (Coss) between the drain and the source of the transistor is radiated by the resistance (Rd) and thermal runaway of the transistor can be prevented. The power loss caused by the internal resistance (RD_S(OΠ)) of n transistors is calculated as follows.

PRLOSS - - R ^ΛDS(θrt) x ^Λ x * n n - - ^{R m) X IpDC}

Therefore, if n transistors are connected in parallel as shown in the figure, power loss can be reduced to 1/n. In addition, multiple low power transistors connected in parallel are far more cost-effective than a single high power transistor. In the upper output unit 51 shown in FIG. 5A, three M1 modules of FIG. 4A may be connected in parallel. That is, the drains (a) of the transistors included in the modules are connected together, and the sources (b) of the transistors are also connected together. Likewise, in the lower output unit 53, three M2 modules of FIG. 4B may be connected in parallel. Because of the parallel connection, when the transistors of the output unit are turned on, the current flowing in each transistor becomes 1/3 of the total current and power loss caused by the transistor on-resistance (Rds) can be reduced to 1/3. In the embodiment shown in FIG. 5A, each output unit has 3 modules. However, if the number of modules increases, power loss can be further reduced, efficiency can be increased, but the physical size of the power supply will increase. If the number of modules decreases, the opposite situation will happen. Therefore, the number of modules can be adjusted depending on the rated power or the intended application.

The number of transistors used in output units 51 and 53 (or the number of modules can be adjusted depending on the output power capacity. It is preferable that the number of transistors included in the upper output unit 51 is the same as the number of transistors included in the lower output unit 53. In addition, the total number of transistors may be even and may exceed 20 ~ 30. If the input voltage of the high voltage power (V0 is 240V, the internal resistance (R_{DS (}on)) of the transistor is 0.5 Ohms and the current (I_PDC) flowing in each transistor is 0.5 A, and 30 transistors are used for circuit configuration, the maximum rated output power of the inverter and the efficiency can be indicated as follows.

Power loss at each transistor: P_te = 0.5 x 0.5² = 0.125 (W)

Total power loss of 30 transistors: P_to0 = 0.125 x 30 = 3.75 (W)

Total current:

I_e = 30 x 0.5 = 15 (A) Max. power:

P_out = 240 x 15 A = 3.6 (KW)

Efficiency:

3.6KW- 3.75W " ⁼ 6KW ⁼ ° " ⁼ "^%

The output unit of the inverter according to the present embodiment can be manufactured in a compact and light module form that has a certain rated output, and multiple modules can be connected in parallel to form a large capacity inverter.

The present embodiment can be applied to a centrally-controlled ballast that operates in a bundle electronic ballasts included in each florescent lamp,_a battery charger, or the motor device of a DC motor. In addition, since the transistors do not require an additional heatproof plane, the module size can be minimized and the efficiency can be drastically enhanced.

The configuration of the current feedback unit (55, S1 ), which senses the current transmitted from the inverter to the transformer (T3) and feeds it back to the PWM control circuit 51 , is described below. As for the current feedback unit 55, since the current (IPD_C) flowing in the transistor is sensitively changed in line with the changing input voltage and the output voltage, the 1^st coil of the current sensing transformer (T2) is positioned at the output side of the inverter as shown in the figure.

The output signal (SENSE) of the feedback unit 55 is fed back to the input terminal (SENSE) of the PWM control circuit 31 shown in FIG. 3A. The feedback unit 55 includes the current coupling transformer (T₂) and the polarity of the coil is as shown in the figure. The resistance (R₆, R₇) converts the current induced in the 2^nd coil of the transformer (T₂) into a voltage signal. If the switching transistor (QO shown in FIG. 3A is turned on, the current flows through the (+) terminal of the high voltage (V0, the upper output unit 51 and the output terminal of the inverter sequentially. If a forward bias is applied to the diode (D3), the current flows through the diode (D₃), while a reverse bias is applied to the diode (D4) and thus the current does not flow through the diode (D ). The capacitor (C₆) is used to remove AC noise and the variable resistor (VRO is used to adjust the voltage level of the output signal (SENSE). The voltage signal (SENSE) adjusted by the variable resistor (VRO is fed back to the PWM control circuit 31. If the switching transistor (QO is turned off, the current flows through the middle tab terminal of the high voltage power (V0, the 1^st coil of the transformer (T₃), the lower output unit 53 and the (-) terminal (- V0 of the high voltage power. In that case, a forward bias is applied to the diode (D4), and thus, the current flows, while a reverse bias is applied to the diode (D3) and the current does not flow.

The feedback unit 55 senses the output current and generates the sensing signal (SENSE) that controls the switching transistor (QO- The transformer (T₂) electrically isolates the switching circuit unit and the inverter output unit. The ground level of the feedback unit 55 is connected to the (-) terminal (- V₂) of the switching voltage and is electrically isolated from the high voltage power (V0 that adjusts the output level of the inverter. Therefore, oscillation and noise generated in the inverter output due to the high frequency operation of the switching transistor (QO can be prevented.

The output rectifying unit of the SMPS will be described below. The 1^st coil of the transformer (T₃, T₄) for output is connected to the output terminal of the inverter and the middle tab terminal of the high voltage power (V0- The 2^nd coil of the transformer is connected to the output rectifying unit. The transformer (T₃, T ) receives the high voltage level square wave output from the inverter and reduces the signal to a certain level of voltage depending on the winding ratio. The output rectifying unit rectifies the signal to provide DC power. FIG. 5A shows an example of a single output port for high power output.

The output side of the transistor (T₃, T₄) includes the rectifying element and the capacitor for filtering. The transformer operates as an inductor to store and transmit energy. The transistors are elements for rectification and the capacitors are elements for filtering. The present embodiment includes two transformers (T₃, T₄). The output rectifying unit (57a, b) is connected to the 2^nd coil of each transformer (T₃, T₄). The 1^st output rectifying unit (57a) includes two output modules 571 and 572 and capacitors (Co^ Co₂) for filtering, which are connected to both terminals of the output port. In addition, the 2^nd output rectifying unit (57b) includes two output modules 573 and 574 and capacitors (Co₃, Co₄) for filtering, which are connected to both terminals of the output port. The 1^st output rectifying unit 57a and the 2^nd output rectifying unit 57b have substantially the same internal configurations. The output terminals (a) and (b) of the modules are connected with their counterparts to form one output port (V_out).

The detailed configuration of each output module (M11 ) included in the output rectifying unit (57a, b) is shown in FIG. 5B. The output module includes an upper module (M11 a) and a lower module (M11 b). The upper module (M11a) and the lower module (M11 b) are connected to the 2^nd coil of the output transformer (T₃) and perform rectification in response to the operation of the transistor (Qn)- If the switching transistor (Q0 is turned on, the transistor (Q^) of the upper module (M11 a) is turned on. If the switching transistor (Q0 is turned off, the transistor (Q₁₂) of the lower module (M11 b) is turned on. Thus, DC power output is provided.

The upper module (M11 a) includes a snubber circuit in addition to the transistor (Qn)- The RC element including the resistance (R_s0 and the capacitor (C_sO is the 1^st snubber circuit used to prevent transient over-voltage ringing caused by the leakage inductance of the 1^st coil of the transformer (T₃) and the gate capacitance (CGS) of the transistor (Qn)- The RC element including the resistance (RdO and the capacitor (CdO i the 2^nd snubber circuit used to prevent transient over-voltage ringing caused by the leakage inductance of the 1^st coil of the transformer (T₃) and the capacitance (C_0Ss) between the drain and the source of the transistor (Qn)- A resonance circuit is formed during the turn-off by the leakage inductance of the 1^st coil of the transformer (T₃) for high frequency and the junction capacitance of the transistor for rectification. Such a resonance circuit may cause transient over-voltage ringing in a transient state. Ringing may have a large amplitude enough to destroy the transistor during the turn-off period and may cause noise and malfunction. The RC snubber circuit makes the ringing have a stable amplitude.

The gate resistance (R_g0 connected to the gate terminal of the transistor (Qn) is added to match the rising time of the square wave transmitted from the transformer (T₃) and that of the transistor (Q-iO-

The lower module (M11 a) has substantially the same internal configuration, snubber circuit and gate resistance functions and parameters as the upper module (M11 a). However, in the upper module (M1 1 a), the gate terminal of the transistor (Qι0 is connected to the coil with the pole indication (dot) of the transformer (T₃) while in the lower module (M11 b), the gate terminal of the transistor (Q₁₂) is connected to the coil without the polarity indication (dot) of the transformer (T₃). Therefore, the square wave power signal transmitted from the 1^st coil of the transformer (T₃) can flow depending on the logic level by turns.

In the output rectifying unit shown in FIG. 5A, two transformers (T₃, T₄) are connected in parallel and in each transformer, two output rectifying units (57a, b) are connected in parallel. The output power is distributed to two transformers and rectified instead of being concentrated on one transformer, and then, the divided output power is combined at the output terminal. Therefore, the current rating of each transformer need not be high and the efficiency can be enhanced, and the core size of the former can be reduced to about 1/4. Moreover, since two or more rectifying modules (M11 ) may be connected to one transformer, the current flowing inside of the transistor and the heat emitted by the transistor, can be distributed and additional heatproof plane is not required.

Transistors (preferably, field-effect transistors) are used as rectifying elements of the output rectifying module (M11 ) and snubber circuits are further included. The transistors are suitable for high current, and the snubber circuits are used to prevent ringing, to resolve problems caused by transient over-voltage and to obtain stable power even if the LC filter used in the existing output rectifier is not added. Especially, since the inductor element need not be used, compact modular power supply can be implemented. That is, according to the circuit of the present embodiment, there is almost no dead time between up and down pulses. Therefore, the efficiency can be enhanced to nearly 100% unlike the existing technology which has about 20% dead time. In addition, due to the dead time between pulses during the existing output rectification, the LC filter for smoothing the output voltage was necessary. However, the size of the core of the inductor for the output filter is designed to be almost the same as that of the core of the output transformer. However, in the present embodiment, such an LC circuit is not necessary and a simple circuit configuration can be implemented.

In addition, because power for supplying power is separated from that for operating the switching element by the current-coupling transformer (T₂) by instability of the output caused by oscillations that may be generated within the power supply circuit can be prevented. High switching frequency can be used (for example, 200 KHz ~ 2000 KHz) and the efficiency of the power supply can increase.

FIG. 5C shows another configuration of the half bridge inverter (that is, configuration between transformers Ti and T₃) of the power supply circuit shown in FIG. 5A. As shown in FIG. 5A, when multiple modules (M1 , M2) are used in the output unit of the inverter, the current flowing in each module (513 and 533 in FIG 5C.) of the upper output unit (51 c) and the lower output unit (53c) is sensed through the transformer (T₂) connected to the current feedback unit (55c) instead of the entire operation current. Then, the current ratings of the 1^st coil of the transformer (T2) can be lowered and the size of the transformer (T₂) can be reduced.

In FIG. 5C, (a) terminals of three modules (511 , 512, 513) of the upper output unit (51c) are connected together to the (+) terminal (+V0 of the high voltage power, (b) terminals of the two modules (511 , 512) are connected together to the 1^st coil of the transformer (T₃). However, (b) terminal of one module 513 is connected to the (b) terminals of two modules (511 , 512) through the 1^st coil of the transformer (T₂). (d) terminals of three modules (531 , 532, 533) of the lower output unit (53c) are connected together to (-) terminal (-V0 of the high voltage power, (c) terminals of the two modules (531 , 532) are connected together to the 1^st coil of the transformer (T₃). However, the (c) terminal of one module 533 is connected to the (b) terminal of one module 513 of the upper output unit (51 c). M1 of FIG. 4A or M3 of FIG. 4C can be used as the module of the upper output unit (51c). M2 of FIG. 4B or M4 of FIG. 4D can be used as the module of the lower output unit (53c). The entire functions of the circuit are the same as those described with reference to FIG. 5A.

FIG. 5D shows the circuit diagram of the full bridge inverter. Since the circuit connected to the 1^st coil of the drive transformer (TO is substantially the same as that shown FIG. 5A, the detailed description will be omitted.

The inverter connected to the 2^nd coil of the drive transformer (TO includes 1^st through the 4^th sub-output units (515, 516, 517, 518). Each module included in the 1^st sub-output unit 515 and the 4^th sub-output unit 518 can be M1 shown in FIG. 4A or M3 shown in FIG. 4C. Each module included in the 2^nd sub-output unit 516 and the 3^rd sub-output unit 517 can be M2 or M4 corresponding to M1 and M3. Each sub-output unit can include two or more modules which have the same configuration so that power loss in the output unit is minimized. The configuration and operation of the feedback unit (55d) are substantially the same as described with reference to FIG. 5A.

If the square wave signal is transmitted to the 2^nd coil of the drive transformer (TO (that is, of the square wave is fed to the gate of each transistor in the sub-output unit), on/off switching of transistors included in the 1^st sub-output unit through the 4^th sub-output unit (515-518) is controlled depending on the gate voltage. That is, if the transistors included in the 1^st sub-output unit 515 and the 4^th sub-output unit 518 are turned on simultaneously, transistors included in the 2^nd sub-output unit 516 and the 3^rd sub-output unit 517 are turned off simultaneously. If transistors included in the 1^st sub-output unit 515 and the 4^th sub-output unit 518 are turned off simultaneously, transistors included in the 2^nd sub-output unit 516 and the 3^rd sub-output unit 517 are turned on simultaneously. Then, the square wave amplified to the high voltage (V0 is generated. That is, when the switching transistor (QO shown in FIG. 3A is turned on, the transistors included in the 1^st sub-output unit 515 and the 4^th sub-output unit 518 are turned on simultaneously, and the transistors included in the 2^nd sub-output unit 516 and the 3^rd sub-output unit 517 stay turned off. Therefore, the current induced by the high voltage power (VO flows through the 1^st sub-output unit 515, the point S1 , the 1^st coil of the current-sensing transformer (T₂), the 1^st coil of the output transformer (T₃), the 4^th sub-output unit 518 and the (-) terminal (-V0 of the high voltage power sequentially. When the switching transistor (QO is turned off, transistors included in the 2^nd sub-output unit 516 and the 3^rd sub-output unit 517 are turned on simultaneously, and the transistors included in the 1^st sub-output unit 515 and the 4^th sub-output unit 518 stay turned off. Then, the current induced by the high voltage power (VO flows through the 3^rd sub-output unit 517, the point S2, the 1^st coil of the output transformer (T₃), the 1^st coil of the current-sensing transformer (T₂), the 2^nd sub-output unit 516 and the (-) terminal (-V0 of the high voltage power, sequentially. By the above operation, the inverter generates the square wave with high voltage and the inverter output is transmitted to the output rectifying unit through the transformer (T₃). That is, the direction of the current flowing in the 1^st coil of the transistor (T₃) varies in the opposite depending on the on/off operation of each transistor and the square wave amplified to the high voltage is obtained.

The configuration and the operation of the feedback unit (55d) are substantially the same as those of the feedback unit (55, SO shown in FIG. 5A. The feedback unit senses the current when the 1^st sub-output unit 515 and the 4^th sub-output unit 518 are turned on, or when the 2^nd sub-output unit 516 and the 3^rd sub-output unit 517 are turned on. Then, the feedback unit feeds the sensed current back to the PWM control circuit (Refer to FIG. 3A.). As described with respect to FIG. 5A, since the power (V₂) for a switching circuit and the power (VO for output are separated by the current-sensing transformer (T₂), any oscillation or noise caused by the high frequency operation can be prevented.

FIG. 5E shows an embodiment of an output rectifying unit connected to the bridge inverter shown in FIG. 5A, 5C or 5D. The output rectifying unit shown in FIG. 5E, which is another example of that shown in FIG. 5A, includes a 1^st rectifying unit (57e) and a 2^nd rectifying unit (57f) in order to provide two or more different output powers. Each rectifying unit uses one transformer and each transformer is connected to, if necessary, multiple rectifying modules (M11 , Refer to FIG. 5B).

The output transformer (T₃) is connected with four rectifying modules (571 , 572, 573, 574) and the output port of each module is connected with capacitors (C0₁, Co₂, Co₃, Co ) for charging/discharging. The output terminals (a) and (b) of the rectifying modules (M11 ) are connected together with their counterparts to form one output port (V_out0- The output transformer (T ) is connected with two rectifying modules (575, 576) and the output terminal of each module is connected with capacitors (Co₅, Co₆) for charging/discharging. The output terminals (a) and (b) of the rectifying modules (M11 ) are connected together with their counterparts to form another output port (V_out2)- As shown in the present embodiment, the number of transformers and rectifying modules connected to each transformer can vary depending on the number of outputs of the power supply and the power rating.

FIG. 5F shows an embodiment of the output rectifying unit (57g) connected to the bridge inverter shown in FIG. 5A, 5C or 5D. This embodiment shows that multiple output transformers can be used to obtain one output and thus the size of each transformer can be designed to be compact. In addition, even if rectifying modules are not configured in the same way, they can be connected in parallel. The output rectifying unit shown in FIG. 5F, which is another embodiment of that shown in FIG. 5A, includes three transformers (T₃, T₄, T₅) and rectifying modules (577, 578, 579) connected to each transformer. Each module uses diodes (D1, D₂) as rectifying elements. As snubber circuit including resistor (Rs) and capacitor (Cs) are connected to both ends of the diode in order to prevent ringing that may be caused by the leakage inductance of the 1^st coil of the transformer and the junction capacitance of the diode.

For low current, even if diodes are used as rectifying elements instead of transistors, power loss is small. Since the MOSFET transistor has low internal breakdown voltage, diodes connected in parallel are more suitable than transistors in order to obtain high voltage (normally 500 V or higher) rectifying output. Therefore, the present embodiment is more suitable when high voltage and low current are required. In addition, FIG. 5F shows that the rectifying module including diodes can be additionally connected in parallel with the rectifying module (580) including an additional transformer (T₆) and the module M11 (Refer to 5B.).

FIG. 6A shows the configuration of a push-pull SMPS. The circuit connected to the 1^st coil of the power transformer (TO is configured in the same way as in the circuit shown in FIG. 3A, thus the description will be omitted. FIG. 6A shows push-pull inverters (61 a, 63a) and an output rectifying unit (67a). Vi and V₂ are DC powers output from the input rectifier (11 ) shown in FIG. 1. Vi is a high voltage DC power (power for amplification) to determine the voltage level of the output signal. V₂ is provided to the 1^st side of the power transformer (TO and is the switching power to generate the square wave signal by the switching operation.

The push-pull inverters (61 a, 63a) include two forward-type output units. Each forward-type output unit provides the power to a load by a half cycle. Each module included in the upper output unit (61 a) can be either M1 of FIG. 4A or M3 of FIG. 4C. At least two modules can be connected in parallel. Each module included in the lower output unit (63a) can be either M2 or M4 corresponding to M1 or M3. At least two modules can be connected in parallel. That is, each output unit includes two or more modules which have the same configuration, thus minimizing power loss in the output unit. If the number of modules increases, the power loss caused by the internal resistance of the transistors is reduced in proportion to the increased number.

Modules included in the upper output unit (61 a) and the lower output unit (63a) have substantially the same internal configuration. However, the current is applied to the gate terminals of the transistors (Q-i, Q ) included in the upper output unit (61 a) in the same direction . as. the polarity of the 1^st coil of the transformer (TO- Meanwhile, the current is applied to the gate terminals of the transistors (Q₃, Q₄) included in the lower output unit (63a) in the opposite direction of the polarity of the 1^st coil of the transformer (TO- The transistors included in the upper output unit (61a) and the lower output unit (63a) are turned on/off alternately depending on the level of the square wave transmitted through the transformer (TO-

(a) terminals of modules 611 and 612 of the upper output unit (61 a) (that is, the drains of the transistors) are connected together to the up terminal of the 1^st coil of the output transistor (T₃). (b) terminals of modules (that is, the sources of the transistors) are connected together to the (-) terminal (-V0 of the high voltage power through the 1^st coil of the transformer (T₂). (a) terminals of modules (631 , 632) of the lower output unit (63a) (that is, the drains of the transistors) are connected together to the down terminal of the 1 ^st coil of the output transistor (T₃). (b) terminals of modules (that is, the sources of the transistors) are connected together to the (-) terminal (-V0 of the high negative voltage power through the 1^st coil of the transformer (T ).

The 1^st coil of the output transformer (T₃) is connected with the output terminal of the inverter. The output terminal includes the common (a) terminals of modules 611 and 612 included in the upper output unit (61 a), the (+) terminal of the high voltage power (V0, and common (a) terminals of modules 631 and 632 included in the upper output unit (63a). If the square wave signal is transmitted to the 2^nd coil of the drive transformer (TO, one of the transistor included in the upper output unit (61 a) and the transistor included in the lower output unit (63a) is turned on simultaneously depending on the logic level and the square wave is generated at the output port. The output signal is input to the output rectifying unit. That is, if the switching transistor (QO connected to the PWM control circuit 31 shown in FIG. 3A is turned on, the transistors included in the upper output unit (61 a) are turned on and the transistors included in the lower output unit (63a) are turned off. Then, current flows through the (+) terminal of the high voltage power (VO, the upper output unit (61 a), the 1^st coil of the transformer (T₂) and the (-) terminal (-V0 of the high voltage power. If the switching transistor (QO is turned off, the transistors included in the upper output unit (61a) are turned off and the transistors included in the lower output unit (63a) are turned on. Then, current flows through the (+) terminal of the high voltage power (VO, the lower output unit (63a), the 1 ^st coil of the transformer (T₂) and the (-) terminal (-V0 of the high voltage power. As described above, the square wave whose voltage level is amplified is generated at the 1^st coil of the output transformer by on/off switching of the switching transistor (QO and the square wave is transmitted to the 2^nd coil.

As the switching frequency of the inverter increases, the power loss by the capacitance C_0Ss between the drain and the source of each MOSFET also increases. For reduction of the power loss, in the output unit, the electric discharger including the diode (D_d), the capacitor (Cd) and the resistance (R_d) is positioned between the drain and the source of the transistor (Refer to FIGS. 4A, 4B and 4C). However, if the voltage (V1 ) fed to the transistor is low (for example, 50 V or less), the discharger is not necessary. Therefore, because the power loss by the junction capacitance (C_0Ss) between the drain and the source of the transistor is radiated as heat from the resistance (Rd), the thermal runaway of the transistor can be prevented.

In the upper output unit (61 a) shown in FIG. 6A, two modules having the same configuration (M1 ) shown in FIG. 4A are connected in parallel. That is, the drains (a) of transistors included in the modules are connected together and the sources (b) of the transistors are connected together. Likewise, in the lower output unit (63a), two modules having the same configuration (M2) shown in FIG. 4B are connected in parallel. In such a parallel configuration, when the transistors of the output unit are turned on, the current flowing each transistor becomes 1/2 of the entire current and the power loss caused by the transistor on-resistance (R_ds) is reduced to 1/2. In the embodiment shown in FIG. 6A, each output unit has 2 modules. However, if the number of modules increases, power loss can be further reduced and efficiency can be increased, but the physical size of the power supply will increase. If the number of modules decreases, the opposite situation will happen. Therefore, the number of modules can be adjusted depending on the power rating or the intended application.

The current feedback unit (65a) senses the current flowing through (-) terminal (-V0 of the high voltage power, and feeds it back to the PWM control circuit 31 as shown in FIG. 3A. As explained in FIG. 3A, since the transformer (T₂) electrically isolates the power (V₂) of the circuit for switching and the power (VO for output, oscillation and noise caused by the high frequency operation can be prevented.

The feedback unit (65a, S2) includes the current coupling transformer (T₂), and the polarity of the coil is shown in the figure. The resistance (R₇) converts the current induced in the 2^nd coil of the transformer (T₂) into a voltage signal. Irrespective of on/off switching of the switching transistor (Q0, current flows through the (+) terminal of the high voltage power (V0, the 1^st coil of the transformer (T₃) and the (-) terminal (-V0- Thus, forward bias is applied to the diode (D ) and the current flows. The capacitor (C₆) is used to remove noise and the variable resistor (VRO is used to adjust the electrical potential level of the output signal (SENSE). The voltage signal (SENSE) adjusted by the variable resistor (VRO is fed back to the PWM control circuit 31.

The feedback unit (65a) senses the output current and generates the sensed signal (SENSE) that controls the switching transistor (Q0- The transformer (T₂) electrically isolates the switching circuit unit and the inverter output unit. The (-) terminal of the feedback unit (65a) is connected to the (-) terminal (-V₂) of the switching power and is electrically isolated from the high voltage power (VO that adjusts the output level of the inverter. Therefore, oscillation and noise generated in the inverter output by the high frequency operation of the switching transistor (QO can be prevented.

The output rectifying unit (67a) of the push-pull switching power supply will be described. The 1^st coil of the output transformer (T₃) is connected with the output terminal of the inverter, and the 2^nd coil thereof is connected with the output rectifying unit (67a). The output transformer (T₃) receives the square wave of the high voltage level from the inverter and reduces the signal to a certain level of voltage depending on the winding ratio. The rectifying unit rectifies the voltage and provides DC power.

The output side of the transformer (T₃) includes the rectifying element and the capacitor for filtering. The transformer adjusts the output voltage depending on the winding ratio, and the transistors are elements for rectification and the capacitors are elements for filtering.

The output rectifying unit (67a) includes the output modules and the capacitor (CoO for filtering connected to both terminals of the output port. The configuration of each output module (M11 ) included in the output rectifying unit (67a) is shown in FIG. 5B, which includes an upper module (M11 a, 671 ) and a lower module (M11 b, 672). The upper module (M11 a) and the lower module (M11 b) are connected to the 2^nd coil of the output transformer (T₃) and perform rectification. If the switching transistor (Q0 shown in FIG. 3A is turned on, the transistor (QiO of the upper module (M11a) is turned on. If the switching transistor (Q0 is turned off, the transistor (Q₁2) of the lower module (M11 b) is turned on. The output capacitor (CoO filters out small ripples and provides smooth DC power.

The upper module (M11 a) includes a snubber circuit in addition to the transistor (Qn)- The RC element including the resistance (R_s0 and the capacitance (C_s0 is the 1^st snubber circuit used to prevent transient over-voltage ringing caused by the leakage inductance of the 1^st coil of the transformer (T₃) and the gate capacitance (C_GS) of the transistor (Qn)- The RC element including the resistance (RdO and the capacitor (C_dO is the 2^nd snubber circuit used to prevent transient over-voltage ringing caused by the leakage inductance of the 1^st coil of the transformer (T₃) and the capacitance (C_oss) between the drain and the source of the transistor (Qn)- The gate resistance (R_g0 connected to the gate terminal of the transistor (QiO is added to match the rising time of the square wave transmitted from the power transformer (T₃) and that of the transistor (QiO- The lower module (M11 b) has substantially the same internal configuration, snubber circuit and gate resistance functions and parameters as the upper module (M11 a). However, in the upper module (M11 a), the gate terminal of the transistor (QiO is connected to the coil with the polarity indication (dot) of the transformer (T₃), while in the lower module (M11 b), the gate terminal of the transistor (Q₁₂) is connected to the coil without the polarity indication (dot) of the transformer (T₃). Therefore, the square wave power signal transmitted from the 1^st coil of the transformer (T₃) can flow by turns depending on the logic level.

In the push-pull SMPS circuit diagram shown in FIG. 6A, the high voltage power (V1 ) and the power (V2) for switching circuits are provided separately. In many cases, the push-pull power supply is used for low power. However, experiment shows that even if the two powers are configured as one power, the push-pull SMPS circuit operates normally. That is, one power is supplied to the switching circuit as well as the inverter.

FIG. 6B shows another configuration of the push-pull inverter (that is, configuration between transformers T_Ϊ and T₃) of the power supply circuit shown in FIG. 6A. As shown in FIG. 6A, when multiple modules (M1 , M2) are used in the output unit of the inverter, the current flowing each module (615 and 633 in the figure) of the upper output unit (61 b) and the lower output unit (63b) is sensed through the transformer (T₂) connected to the feedback unit (65b), instead of the entire operation current. Then, the current rating of the transformer (T₂) can be lowered and the size of the transformer (T₂) can be reduced.

In FIG. 6B, (a) terminals of three modules (613, 614, 615) of the upper output unit (61 b) are connected together to form one output terminal of the inverter, (b) terminals of the two modules (613, 614) are connected together to the (-) terminal (-V0 of the high voltage power. However, the (b) terminal of the module 615 is connected to the (-) terminal (-V0 of the high voltage power through the 1^st coil of the transformer (T₂).

(a) terminals of three modules 633 through 635 of the lower output unit (63b) are connected together to form another output terminal of the inverter, (b) terminals of the two modules 634 and 635 are connected together to the (-) terminal (-V0 of the high voltage power. However, the (b) terminal of the module 633 is connected to the (b) terminal of the module 615 of the upper output unit (61 b). M1 of FIG. 4A or M3 of FIG. 4C can be used as the modules of the upper output unit (61 b). M2 of FIG. 4B or M4 of FIG. 4D can be used as the modules of the lower output unit (63b). The overall functions of the circuit are the same as those described with respect to FIG. 6A.

FIG. 6C shows an embodiment of an output rectifying unit connected to the push-pull inverter shown in FIGS. 6A or 6B, which is another example different from the output rectifying unit shown in FIG. 6A, and includes multiple rectifying units (67C1 , 67C2, 67C3). Each rectifying unit uses one transformer and each transformer, if necessary, is connected to multiple rectifying modules (M11 , Refer to FIG. 5B.).

The transformer (T₃) is connected to two rectifying modules 671 and 672, and the output terminals of the modules are connected to the capacitors (Co-n, Co₁₂) for filtering. The output terminals (a) and (b) of the rectifying module (M11) are connected with their counterparts to form one output voltage (V_out0- The transformer (T ) is connected to one rectifying module 673 and the output port is connected with the capacitor (Co₂) for filtering. The output terminals (a) and (b) of the rectifying module (M11 ) form the output voltage port (V_out2)- As shown in the present embodiment, the number of output transformers and rectifying modules connected to each transformer can vary depending on the number of outputs of the power supply and the output power rating.

For low current/high voltage power, the transformer (T₅) can adopt the output rectifying unit (67c3) having the configuration shown in FIG. 5F. For low current, even if diodes are used as rectifying elements instead of transistors, power loss is low. Since an internal resistance between drain and source of the MOSFET transistor for high voltage is great, diodes connected in parallel are more suitable than the transistors in order to obtain high voltage (normally 200 V or higher) rectifying output. Therefore, the present embodiment is more suitable when high voltage and low current are required. In addition, FIG. 6D shows the rectifying module including diodes.

In the circuit of the present invention, the inverter for high power (low voltage and high current) can be implemented with the battery voltage used. In addition, the circuit can be applied to a DC motor driving device, saving energy consumption, increasing the switching frequency and enhancing the torque of the motor. Especially, if the circuit is applied to the air-conditioner compressor motor, the power consumption of an air-conditioner can be drastically reduced. The converter configured as described above can be used as a driving circuit of a power converting device that requires high power, and be useful for various inverter or converter circuits used in battery chargers and DC motor driving devices. The converter according to the present invention is suitable for a driving circuit of a power supply with low voltage/high power such as in notebook computers.

Industrial Applicability

As described above, since the SMPS according to the present invention provides V1 and V2, to a main power amplifier (output side of the power transformer) and a switching frequency oscillator (PWM control circuit), respectively, no oscillation happens even when a switching frequency increases and thus high efficiency can be obtained. Drastically increased switching frequency enables the compact transformer to be implemented in the converter and less coil turns helps to reduce energy loss that may be caused by the coil resistance. The existing method of generating a totem-pole signal causes more than 20% power loss, limiting the efficiency to at most 80%. However, according to the present invention, since the drive transformer transmits (+) pulse and (-) pulse separately to the 2^nd side thereof and performs amplification, the power loss is negligible. In addition, existing power supplies need a filter including an inductor and a capacitor in order to compensate for the unavailable power at the converter output terminal. On the contrary, according to the present invention, the SMPS only needs a low capacitance and compact capacitor that can be cost-effectively implemented because ripples generated at the output side are small.

Claims

What is claimed is:

1. A Switching Mode Power Supply (SMPS) comprising: a power output unit for outputting a 1^st power and a 2^nd power; a switching unit for switching the 2^nd power on/off according to a switching signal to output a square wave signal having the 2^nd power level and a frequency of the switching signal; an inverter for receiving the square wave signal having the 2^nd power level and amplifying it to a square wave signal having the 1^st power level; and an output rectifying unit for rectifying the square wave signal output from the inverter and outputting DC power.

2. The SMPS of claim 1 , wherein the switching unit comprises: a current feedback unit for detecting the output current of the inverter and feeding back the detected current to a switching controller; an output feedback unit for feeding back the output signal of the output rectifying unit to the switching controller; and the switching controller for adjusting the pulse phase of the switching signal according to an error signal generated as a result of comparison between the feedback output signal and a reference signal and the detected signal output from the current feedback unit in order to maintain the DC voltage output from the output rectifying unit constant.

3. A Switching Mode Power Supply (SMPS) comprising: a power output unit for outputting a 1 ^st power and a 2^nd power; a switching unit for switching the 2^nd power on/off according to a switching signal to output a square wave signal having the 2^nd power level and a frequency of the switching signal; and an inverter having a 1^st switching element which switches on when the voltage of the received square wave signal having the 2^nd power level is positive and outputs a positive voltage signal of the 1 ^st power level, and a 2^nd switching element which switches on when the voltage of the received square wave signal having the 2^nd power level is negative and outputs a negative voltage signal of the

1 i st po .,w. „e.r,. i leve il, for ou ιt«p.u.t.4t.:ing u the squ .are w „.a„.v„e- s „;igna .il ha„.v.:ing * the Λ 1 st power level.

4. The SMPS of claim 3, further comprising: an output rectifying unit for rectifying the square wave signal output from the inverter and outputting DC power.

5. The SMPS of claim 1 or 3, wherein the power output unit is an input rectifier that receives AC power and outputs the 1 ^st power having a high voltage level and the 2^nd power having a low voltage level.

6. The SMPS of claim 1 or 3, wherein the switching unit comprises: a switch which is turned on and off in response to the switching signal; and a transformer for receiving the square wave power through the 1 ^st coil connected between the 2^nd power and the switch in response to on/off of the switch and for outputting the square wave signal having the 2^nd power level to the 2^nd coil.

7. The SMPS of claim 6, wherein the 1 ^st coil of the transformer includes a primary coil and an auxiliary coil which substantially have the same thickness and number of turns but different polarity, and the primary coil and the auxiliary coil store energy alternately in response to on/off switching of the switching unit and provide the energy to the 2^nd coil

8. The SMPS of claim 1 or 3, wherein a 2^nd power output unit that generates the 2^nd power the power output unit includes to, the 2^nd power output unit comprising: a 1 ^st rectifying unit for receiving AC power and rectifying the AC power to DC power; a 2^nd switching unit for switching on and off with a predetermined frequency in response to the switching signal; a power transformer for receiving the DC power through the 1^st coil connected between the DC power and the 2^nd switching unit in response to on/off switching of the 2^nd switching unit and providing the power to the 2^nd coil; a 2^nd rectifying unit connected to the 2^nd coil of the power transformer, for converting AC power to DC power and outputting the 2^nd power; a detector for sensing the current flowing in the 1^st coil of the power transformer in response to on/off switching of the 2^nd switching unit and feeding the current back to the controller; and a controller for generating the switching signal according to the error signal generated as a result of comparing the 2^nd power fed back from the 2^nd rectifying unit with a reference signal, and the sensed signal output from the detector.

9. The SMPS of claim 8, wherein the detector comprises: a current-coupling transformer for converting the current flowing in the 1 ^st coil of the power transformer which is connected between one polarity of the input

DC power and the 2^nd switching unit in response to on/off switching of the 2^nd switching unit at a pre-defined ratio and providing the converted power to the 2^nd coil; and a signal generator for generating the sensed signal to be input to the controller, from the current induced in the 2^nd coil of the current-coupling transformer.

10. The SMPS of claim 8, wherein the 2^nd rectifying unit comprises: a transistor whose gate and source are connected to both ends of the 2^nd coil of the power transformer and whose drain functions as an output terminal; and a snubber unit having either a 1 ^st snubber circuit connected between the gate and the source of the transistor to prevent ringing caused by leakage inductance of the power transformer and gate capacitance of the transistor, or a 2^nd snubber circuit connected between the drain and the source of the transistor to prevent ringing caused by leakage inductance of the power transformer and capacitance between the drain and the source of the transistor.

1 1 . The SMPS of claim 8, wherein the 2^nd rectifying unit comprises: a diode for rectification connected to the 2^nd coil of the power transformer; and a snubber circuit connected to both ends of the diode or to both ends of the 2^nd coil of the power transformer, in order to prevent ringing caused by leakage inductance of the power transformer and junction capacitance of the diode.

12. The SMPS of claim 1 or 3, wherein a 1 ^st power output unit that generates the 1 ^st power the power output unit includes to, the 1 ^st power output unit comprising: at least two rectifying units for receiving AC power, rectifying the AC into

DC power and generating the 2^nd power, wherein the rectifying units have substantially the same internal configuration and output the same voltage, and (+) and (-) output terminals of one rectifying unit are commonly connected to (+) and (-) output terminals of other rectifiers respectively.

13. The SMPS of claim 12, wherein each rectifying unit is formed by a module with a predetermined power rating, having (+) and (-) output terminals and the (+) and (-) output terminals of the rectifying units are connected together to output a power with the 1 ^st power rating.

14. The SMPS of claim 3, wherein the inverter comprises aa transformer for receiving the square wave signal having the 2^nd power level; and two transistors for operating as switching elements, connected to the 2 nd coil of the transformer, wherein the drain of the 1 ^st transistor is connected to the (+) terminal of the 1 ^st power and the source of the 2^nd transistor is connected to the (-) terminal of the 1^st power, and the source of the 1^st transistor and the drain of the 2^nd transistor are commonly connected together to form an output terminal.

15. The SMPS of claim 14, wherein the 1 ^st transistor or the 2^nd transistor includes multiple transistor elements connected in parallel and current is distributed to each transistor element.

16. The SMPS of claim 14, wherein the transistor comprises: an electric discharger for discharging electric charge charged in capacitance between the drain and the source of the transistor; and a snubber unit for preventing ringing caused by leakage inductance of the 1 ^st coil of the transformer and the capacitance between the gate and the source of the transistor.

17. The SMPS of claim 16, wherein the snubber unit having a capacitor and a resistance connected to each other in series, is connected to a 2^nd coil of the transformer in parallel.

18. The SMPS of claim 16, wherein the electric discharger comprises: a capacitor for charging the electric charge generated by the capacitance between the drain and the source while the transistor is turned off; a resistance for discharging the electric charge stored in the capacitance while the transistor is turned on; and a diode for determining the direction of the current when the transistor is turned on or off.

19. The SMPS of claim 16, wherein the transistor further comprises: a gate resistance connected to the gate input terminal of the transistor for matching the rising time of the square wave signal transmitted by the power transformer and that of the transistor.

20. A Switching Mode Power Supply (SMPS) comprising: a power output unit for outputting a 1^st power and a 2^nd power; a switching unit for switching the 2^nd power on/off according to a switching signal to output a square wave signal having the 2^nd power level and a frequency of the switching signal; and an inverter having an upper output unit and a lower output unit that switch on/off alternately depending on the logic level of the square wave signal, for setting up a current path through (+) terminal of the 1^st power, the upper output unit and a middle tab terminal of the 1^st power which forms an output terminal sequentially or through the middle tab terminal of the 1^st power, the lower output unit and (-) terminal of the 1^st power, sequentially and for amplifying the received square wave signal having the 2^nd power level into a square wave signal having the 1^st power level.

21. The SMPS of claim 20, wherein each of the upper output unit and the lower output unit includes at least one transistor for switching, the drains of the transistors included in the upper output unit are connected together and to the (+) terminal of the 1^st power, the sources of the transistors are connected together, the sources of the transistors included in the lower output unit are connected together and to the (-) terminal of the 1^st power, the drains of the transistors are connected together, the drains of the transistors included in the lower output unit and the sources of the transistors included in the upper output unit are connected together to form an output terminal of the inverter.

22. A Switching Mode Power Supply (SMPS) comprising: a power output unit for outputting a 1^st power and a 2^nd power; a switching unit for switching the 2^nd power on/off according to a switching signal to output a square wave signal having the 2^nd power level and a frequency of the switching signal; and an inverter having a 1^st output unit through a 4^th output unit that switch on/off alternately according to the logic level of the square wave signal, for setting up a current path through (+) terminal of the 1^st power, the 1 ^st output unit, an output terminal, the 4^th output unit and (-) terminal of the 1^st power, sequentially, or through (+) terminal of the 1^st power, the 2^nd output unit, the output terminal, the 3^rd output unit and (-) terminal of the 1^st power sequentially, and for amplifying the received square wave signal having the 2^nd power level into a square wave signal having the 1^st power level.

23. The SMPS of claim 22, wherein each of the 1^st output unit through the 4^th output unit includes at least one transistor for switching, the drains of the transistors included in the 1^st output unit and the 2^nd output unit are commonly connected to the (+) terminal of the 1^st power, the sources of the transistors included in the 1^st output unit and the 2^nd output unit are connected together, the sources of the transistors included in the 1^st output unit are connected to the sources of the transistors included in the 3^rd output unit through the output terminal of the inverter, the sources of the transistors included in the 2^nd output unit and the 4^th output unit are connected together and to the (-) terminal of the 1^st power, the drains of the transistors included in the 3^rd output unit and the 4^th output unit are connected together, the drains of the transistors included in the 3^rd output unit are connected to the sources included in the 1^st output unit, and the drains of the transistors included in the 4^th output unit are connected to the sources of the 2^nd output unit.

24. An SMPS (Switching Mode Power Supply) comprising: a power output unit for outputting a 1 ^st power and a 2^nd power; a switching unit for switching the 2^nd power on/off according to a switching signal to output a square wave signal having the 2^nd power level and a frequency of the switching signal; and an inverter having an upper output unit and a lower output unit that switch on/off alternately according to the logic level of the square wave signal, for setting up a current path through (+) terminal of the 1^st power, the upper output unit and (-) terminal of the 1 ^st power, sequentially, or through (+) terminal of the 1^st power, the lower output unit and (-) terminal of the 1^st power, sequentially, and for amplifying the received square wave signal having the 2^nd power level into a square wave signal having the 1^st power level.

25. The SMPS of claim 24, wherein the upper output unit has at least one module including a transistor, the drains of the transistors included in the modules of the upper output unit are connected together and to an up terminal of a 1 ^st coil of an output transformer, the sources of the transistors included in the upper output unit are connected together and to the (-) terminal of the 1^st power, the lower output unit has at least one module including a transistor, the drains of the transistors included in modules of the lower output unit are connected together and to a down terminal of the 1^st coil of the output transformer, the sources of the transistors included in the lower output unit connected together and to the (-) terminal of the 1^st power, when the transistors included in the upper output unit are turned on simultaneously according to the logic level of the input square wave signal, current flows from the (+) terminal of the 1^st power to the (-) terminal of the 1^st power through the upper output unit, or when the transistors included in the lower output unit are turned on simultaneously, current flows from the (+) terminal of the 1^st power to the (-) terminal of the 1^st power through the lower output unit, and thus the square wave signal having the 1^st power level is output to the output port.

26. The SMPS of claim 24, wherein the 1^st power and the 2^nd power are the same.

27. The SMPS of claim 20, 22 or 24, wherein each output unit of the inverter includes multiple switching elements and the current path is set up by simultaneous on/off switching of the switching elements included in the output units so that current flowing through each output unit is distributed to each switching element.

28. The SMPS of claim 20, 22 or 24, wherein the switching unit comprises: a current feedback unit for detecting the output current of the inverter; a switching controller for adjusting the pulse phase of the switching signal according to the detected signal output from the current feedback unit in order to maintain the DC voltage of the final output regular.

29. The SMPS of claim 20, 22 or 24, wherein each output unit of the inverter includes multiple switching elements, and the inverter further comprises; a current feedback unit for detecting the current flowing along the current path set up by some of the multiple switching elements included in each output unit; and a switching controller for adjusting the pulse phase of the switching signal according to the detected signal output from the current feedback unit in order to maintain the DC voltage of the final output regular.

30. The SMPS of claim 20, 22 or 24, wherein a current-coupling transformer is positioned on the path of the current flowing to an output terminal of the inverter, current induced in a 2^nd coil of the transformer is converted into a voltage signa . and the pulse phase of the switching signal is adjusted based on the converted signal and the DC voltage of the final output is maintained regular.

31. The SMPS of claim 20, 22 or 24, wherein each output unit of the inverter comprises: a transistor for switching; an electric discharger for discharging electric charge charged in capacitance between the drain and the source of the transistor; and a snubber unit for preventing ringing caused by leakage inductance of a transformer and capacitance between the gate and the source of each transistor.

32. The SMPS of claim 31 , wherein the electric discharger comprises: a capacitor for charging the electric charge generated by the capacitance between the drain and the source while the transistor is turned off; a resistance for discharging the electric charge stored in the capacitance while the transistor is turned on; and a diode for determining the direction of the current when the transistor is turned on or off.

33. The SMPS of claim 31 , wherein each transistor further comprises: a gate resistance connected to the gate input terminal of the transistor for matching the rising time of the square wave signal transmitted by the power transformer and that of the transistor.

34. The SMPS of claim 20, 22 or 24, further comprising; an output rectifying unit for rectifying the square wave signal output from the inverter and outputting DC power.

35. The SMPS of claim 34, wherein the output rectifying unit includes the upper module and the lower module that are turned on/off alternately in response to the phase of the square wave signal transmitted through a transformer from the inverter, each of the upper module and the lower module comprising: a transistor whose gate and source are connected to both ends of the 2^nd coil of the transformer and having the drain as an output terminal; and a snubber unit having either a 1^st snubber circuit connected between the gate and the source of the transistor to prevent ringing caused by leakage inductance of the transformer and gate capacitance of the transistor, or a 2^nd snubber circuit connected between the drain and the source of the transistor to prevent ringing caused by leakage inductance of the transformer and capacitance between the drain and the source of the transistor.

36. The SMPS of claim 34, wherein the output rectifying unit includes the upper module and the lower module that are turned on/off alternately in response to the phase of the square wave signal transmitted through a transformer from the inverter, each of the upper module and the lower module comprising: a diode for rectification connected to the 2^nd coil of the transformer; and a snubber circuit connected to both ends of the diode or both ends of the

2^nd coil of the power transformer, in order to prevent ringing caused by leakage inductance of the transformer and junction capacitance of the diode.

37. A rectifier comprising: at least two rectifying units, each rectifying unit comprising: an AC input unit for receiving AC power, clamping excessive input voltage to the safe level voltage and blocking excessive current of the input power; a current path setup unit for determining the path of current according to the phase of the input AC power; and an output unit that charges current flowing along the path determined by the current path setup unit and generates DC voltage,

Wherein the rectifying units have substantially the same internal configurations and generate the same voltage, and (+) and (-) output terminals of each rectifying unit are commonly connected to the (+) and (-) output terminals of other rectifying units respectively.

38. The SMPS of claim 37, wherein each rectifying unit includes a module having a predetermined rating and (+) and (-) terminals of each module are connected together to generate a power having a required rating:

39. The rectifier of claim 37, wherein the output unit of each rectifying unit further includes a pi (U ) - type filter having a capacitor and an inductor in order to remove high frequency harmonic noises.