WO2002023757A1

WO2002023757A1 - Switchable power divider

Info

Publication number: WO2002023757A1
Application number: PCT/KR2001/001548
Authority: WO
Inventors: Rack-June Back; Jung-Hak Ahn; Jong-In Ryu; Chang-Hwan Kim
Original assignee: Ace Technology
Priority date: 2000-09-14
Filing date: 2001-09-14
Publication date: 2002-03-21
Also published as: KR100384970B1; KR20020021306A

Abstract

A switchable power divider which ensures the impedance matching characteristics regardless of the change in the number of signal dividing paths. The switchable power divider receives an input signal through an input port (30) and outputs the received signal to at least one of a plurality of output ports (82, 84, 86). The switchable power divider includes a dividing node (60); an impedance matching unit (40) disposed between the input port (30) and the dividing node (60); and a plurality of distributing paths (72, 74, 76) each selectively connecting the dividing node (60) to respective one of the plurality of output ports (82, 84, 86). An effective characteristic impedance of the impedance matching unit changes according to the number of output ports connected to the dividing node.

Description

SWITCHABLE POWER DIVIDER

Technical Field

The present invention relates to a power divider of a RF or a microwave frequency bandwidth and, more particularly, to a switchable power divider of which number of signal

dividing paths is variable.

Background Art

Mobile communication systems are expanding services to include data communication services in addition to the traditional voice-oriented services. Thus, higher frequency bands and a wider bandwidth are being used for the communications than before so as to facilitate to transmit large amounts of data in real time. In this regard, a conventional single-channel power amplifier and a power combiner used for amplifying

transmit signals at a RF end of a transmitter are being replaced by a multiple channel power amplifier and a switchable power divider/combiner. Typically, the switchable power divider, which is used at an input stage of a power amplifier controlling the transmit power

of a base station in the mobile communication, divides the transmit signal according to the

number of power amplifiers so that the power amplifiers amplify the transmit signal. In other words, the switchable power divider/combiner carries out the functions of dividing and combining of signals while providing a redundant signal path against an abnormality

of any power amplifier. In a Wilkinson type divider having fixed signal paths, the characteristic impedance

of impedance matching lines are determined based on the number of signal paths to be divided. For example, the characteristic impedances of the impedance matching lines are determined to be V^"2Z₀ in case of 2-way dividing mode and 3Z₀in case of 3-way dividing mode, where Z₀is the common characteristic impedance, 50 ohm[Ω]. However, in the case that the number of divided signal paths is variable rather than being fixed, the average of

the optimum values for different operation modes have been chosen as the characteristic

impedances of the impedance matching lines. Alternatively, a combination of a single path transmission line and the average-matched transmission lines have been used as well. FIG. 1 illustrates an example of the average-matched 3-way switchable power divider. A signal received through an input port 2 is divided by a desired number of dividing paths and output though one or more of the output ports PO1, PO2, and PO3. The number of dividing paths is determined by the number of power amplifiers being operated in the system. Switching control signals for controlling the switching operation

of the switches S21 through S26 are provided by a controller not shown in the Figure. For

example, in case of 2-way operation, the switches S21, S22, S23, and S24 are turned on while the switches S25 and S26 are turned off and the input signal is divided into two paths

and output through the output ports PO1 and PO2. Meanwhile, isolation resistors Rl, R2, and R3 and terminators 14, 16, and 18 are provided after the output ports PO1, PO2,

and PO3. Additionally, each of the switch pairs S21 and S22, S23 and S24, and S25 and

S26 operate simultaneously responding to a respectively common switching control signal. As mentioned above, however, the characteristic impedance Z_m of each of the

impedance matching lines 4, 6, or 8 shown in FIG. 1 is generally determined to be the average, Z₀/2( 2-h/^"3Z₀) (=78.7Ω), of ^"2^ (=70.7Ω) and V^"3Z (=86.6Ω) which are

optimal impedances for 2-way and 3-way dividing operation modes, respectively. While the average matching may provide satisfactory reflection loss requirements in 2-way or 3- way operation mode, it may be difficult to use the divider for 1-way operation mode since

the reflection loss is increased. To avoid such a problem, some devices employ a

combination of a single path transmission line and the average-matched transmission lines alternatively as mentioned above, which, however, cannot accomplish the perfect matching condition for all the operation modes either.

As mentioned above, the conventional switchable power combiner/divider shows imperfect impedance matching depending on the number of divided/combined signal paths. Further, the conventional switchable power combiner/divider employs mechanical switches, which increases the manufacturing cost of the system.

Disclosure of the Invention

To solve the problems above, the object of the present invention is to provide a switchable power divider in which the impedance matching is efficiently fulfilled regardless of the number of divided signal paths.

The switchable power divider for achieving the above object receives an input

signal through an input port and outputs the input signal through at least one of a plurality

of output ports. The switchable power divider comprises a dividing node; an impedance matching unit disposed between the input port and the dividing node; and a plurality of distributing paths each for selectively coupling the dividing node to respective one of the plurality of output ports. An effective characteristic impedance of the impedance matching unit varies depending on a number of the output ports coupled to the dividing node.

In a preferred embodiment, the impedance matching unit includes a first through a third matching lines. The first matching line has a first end connected to the input port and a second end connected to the dividing node. The second matching line selectively

connects a first position of the first matching line to ground. First switching means is connected to the second matching line so that the first position of the first matching line is selectively connected to ground through the second matching line. Second switching means is connected to the third matching line so that the second position of the first matching line is selectively connected to ground through the third matching line.

In an embodiment of the impedance matching unit, the first and the second switching means may be implemented by use of single pole single throw (SPST) switches respectively employing a pin diode. In an example of the first switching means according to such an embodiment, a first capacitor has a first terminal connected to ground. A first

inductor is connected between a second terminal of the first capacitor and a first end of the second matching line. A diode has an anode connected to a second end of the second matching line and a cathode connected to the first position of the first matching line. A second inductor is connected between a third position of the first matching line and

ground. Here, a biasing signal is provided to a connection between the first capacitor and

the first inductor. The first switching means preferably includes a second and a third capacitors. The second capacitor is connected between the input port and the first end of the first matching line and the third capacitor is connected between the second end of the first matching line and the dividing node.

Brief Description of the Drawings

The above objectives and advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which:

FIG. 1 illustrates an example of a conventional 3-way switchable power divider;

FIG. 2 illustrates an embodiment of a 3-way switchable power divider of the present invention;

FIG. 3 illustrates an implementation of an impedance matching unit shown in FIG.

2;

FIG. 4A is an equivalent circuit diagram of a first impedance matching circuit shown in FIG. 3; and

FIG. 4B is an equivalent circuit diagram of a second impedance matching circuit shown in FIG. 3.

Embodiments

FIG. 2 illustrates an embodiment of a 3-way switchable power divider of the present invention. The 3-way switchable power divider shown in the drawing includes an

input port PI and three output ports PO1, PO2, and PO3, so as to receive an input signal through the input port and output the input signal to at least one of the output ports POl,

PO2, and PO3. More specifically, the switchable power divider includes an impedance matching unit disposed between the input port 30 and a dividing node 60, and three distributing transmission lines 72, 74, and 76 disposed between the dividing node 60 and respective one of the output ports POl, PO2, and PO3. Switches S31, S41, and S51 are

provided between the dividing node 60 and respective one of the distributing transmission lines 72, 74, and 76 to selectively activate respective distributing transmission lines 72, 74, and 76. On the other hand, isolation resistors Rl, R2, and R3 and terminating lines 92, 94, and 96 are provided after the output ports POl, PO2, and PO3. The impedance matching unit 40 includes a first matching line 42 disposed between

the input port 30 and the dividing node 60, a first impedance matching circuit 44 connected between a first position of the first matching line 42 and ground, and a second impedance matching circuit 50 connected between a second position of the first matching line 42 and ground. Here, the second position may be identical with the first position. The first impedance matching circuit 44 includes a second matching line 46, and a first switch 48

connected to the second matching line 46 to selectively connect the first position of the first matching line 42 to ground through the second matching line 46. Similarly, the second impedance matching circuit 48 includes a third matching line 52, and a second switch 54

connected to the third matching line 52 to selectively connect the second position of the

first matching line 42 to ground through the third matching line 52.

In a preferred embodiment, the first matching line 42, distributing transmission lines

72, 74, and 76, and terminating lines 92, 94, and 96 have characteristic impedances(Z₀) of 50 ohms. Meanwhile, the second matching line has a characteristic impedance (Zml) of

I 2 / 2 ^an^ ^tne third matching line has a characteristic impedance (Zm2) of jz ² / 3 ■

Here, the numerals, 2 and 3, in the denominators means the number of signal dividing

paths. The switchable power divider of FIG. 2 operates as follows. The switchable power divider divides the input signal by the number of power amplifiers to be used in the system to output the divided signals through one, two, or three of the output ports POl, PO2, and PO3.

First, we consider the case that the switchable power divider operates in 1-way mode. In such a case, the first and the second switches 48 and 52 in the impedance

matching unit 40 are turned off and only the first matching line 42 operates in the impedance matching unit 40. Meanwhile, in three output paths, the switches S31 and S32

are turned on but the switches S41 through S52 are turned off. Thus, the input signal received through the input port 30 is output through the first output port 82 only.

In the case that the switchable power divider operates in 2-way mode, the first switch 48 is turned on but the second switch 52 is turned off in the impedance matching

unit 40. Thus, a signal path connecting the first matching line 42 to ground through the second matching line 46 is further provided. Meanwhile, in three output paths, the

switches S31 through S42 are turned on but the switches S51 and S52 are turned off.

Accordingly, the input signal received through the input port 30 is output through the first and the second output ports 82 and 84. At this time, due to the characteristic impedance (Zml) of the second matching line 46, the effective characteristic impedance of the impedance matching unit 40 differs from the impedance Zo of the first matching line 42, and thus the impedance matching performance of the impedance matching unit 40 is optimized for the operation mode.

In the case that the switchable power divider operates in 3-way mode, the first switch 48 is turned off but the second switch 52 is turned on in the impedance matching unit 40. Thus, a signal path connecting the first matching line 42 to ground through the

third matching line 52 is further provided. Meanwhile, all the switches S31 through S52 in three output paths are turned on. Accordingly, the input signal received through the input port 30 is output through the first though the third output ports 82 through 86. At this time, due to the characteristic impedance (Zm2) of the third matching line 52, the effective characteristic impedance of the impedance matching unit 40 differs from those in the 1-way or 2-way operation mode, and thus the impedance matching performance of the impedance matching unit 40 is optimized for the operation mode. Even though a value of

the characteristic impedance (Zm2) of the third matching line 52 was exemplified above,

the value may be chosen to another value depending on the applications.

FIG. 3 illustrates an implementation of an impedance matching unit shown in FIG. 2, FIGS. 4A and 4B are equivalent circuit diagrams of the first and the second impedance

matching circuits 44 and 50 shown in FIG. 3.

The first impedance matching circuit 44 includes the second matching line 46 and

the first switch 48 as mentioned above. The first switch 48 includes a first capacitor Cl, a first inductor Ll, a pin diode 100, a second inductor L2, and a second and a third

capacitors C2 and C3. The first capacitor Cl has a first terminal connected to ground. The first inductor Ll is connected between a second terminal of the first capacitor Cl and

a first end of the second matching line 46. The diode 100 has an anode connected to a second end of the second matching line 46, and a cathode connected to the first position of the first matching line 42. The second inductor L2 is connected to a third position of the first matching line 42 and ground. A first biasing signal BIAS1 is provided to a connection 102 of the first capacitor Cl and the first inductor Ll. The second capacitor C2 is disposed between the input port 30 and a first end of the first matching line 42, and the third capacitor C3 is disposed between the a second end of the first matching line 42 and the dividing node 60.

Meanwhile, the second impedance matching circuit 44 includes the third matching line 52 and the second switch 54 as mentioned above. The second switch 54 includes a fourth capacitor C4, a third inductor L3, and a pin diode 110. The second switch 54 shares the second inductor L2 and a second and a third capacitors C2 and C3 with the first switch 48. The fourth capacitor C4 has a first terminal connected to ground. The third inductor

L3 is connected between a second terminal of the fourth capacitor C4 and a first end of the third matching line 52. The diode 110 has an anode connected to a second end of the third matching line 52, and a cathode connected to the second position of the first matching line 42. A second biasing signal BIAS2 is provided to a connection 112 of the fourth capacitor

C4 and third first inductor L3. Now, the operation of the first switch 48 is described, which is similar for the second switch 54. When the first biasing signal is at a low level, the diode 100 is reverse-

biased and thus the second matching line 42 is disconnected from the first matching line 40. That is, first switch 48 is turned off at this time. On the other hand, when the first biasing signal is at a high level, the diode is forward-biased and turned on to form a signal path for an alternating current (AC) signal between the first and the second matching lines 40 and 42. Accordingly, some portion of the input signal received through the input port 30 may flow to ground through the diode 100, the second matching line 42, a first inductor Ll, and a first capacitor Cl. In other words, since the first switch 48 is turned on, a signal

path connecting the first matching line 40 to ground is formed through the second matching line 42. A direct current (DC) power provided through the diode 100 flows out through the second inductor L2. The first capacitor Cl prevents a parasitic high frequency signal flowing though a power line from flowing into the first matching line 42. The

second and the third capacitors prevent DC power from flowing out through the input port 30 or the dividing node 60.

As can be guessed from FIGS 3 through 4B, all the components including the input ports 30, the output ports 82 through 86, and the transmission lines 42, 46, 52, 72, 74, and 76 can be installed on a single printed circuit board.

Although the present invention has been described in detail above, it should be understood that the foregoing description is illustrative and not restrictive. For example, the first or the third inductors Ll or L3 may be omitted in the apparatus of FIGS. 4 A and

4B. One terminal of the first capacitor Cl can be connected to the connection of the first inductor Ll and the second matching line 46. Similarly, one terminal of the fourth

capacitor C4 can be connected to the connection of the third inductor L3 and the third matching line 52. Even though the details of the operations of the switches S31 through S52 was not presented above, such switches may be operated in response to respective control signals from a system controller not shown in the drawings. In such a case, the first and the second biasing signals BIAS1 and BIAS2 may be provided by the system

controller. The switches may be manipulated manually as well. Even though the switching power divider was described in terms of a 3-way divider above, it is obvious that the present invention may be generalized to N-way switchable power divider based on the inventive idea described in the claims appended to this specification.

Thus, those of ordinary skill in the art will appreciate that many obvious modifications can be made to the invention without departing from its spirit or essential characteristics. Thus, it should be apparent that the invention can be modified in arrangement and detail without departing from such principles. We claim all modifications and variation coming within the spirit and scope of the following claims.

Industrial Applicability

As described above, the switchable power divider according to the present invention maintains optimum impedance matching characteristics even when the number

of signal dividing paths is changed. Thus, the performance of the switchable power divider is enhanced while the insertion loss is minimized. Particularly, the manufacturing cost of the divider is not so high since the switching operation for changing the characteristic impedance is carried out by a pin diode switch rather than a mechanical switch.

Claims

What is claimed is:

1. A switchable power divider for receiving an input signal through an input port and outputting the input signal through at least one of a plurality of output ports, comprising: a dividing node;

an impedance matching unit disposed between said input port and said dividing node; and

a plurality of distributing paths each for selectively coupling said dividing node to respective one of said plurality of output ports;

wherein an effective characteristic impedance of said impedance matching unit varies depending on a number of said output ports coupled to said dividing node.

2. The switchable power divider as claimed in claim 1, wherein said impedance matching unit comprises:

a first matching line having a first end connected to said input port and a second end connected to said dividing node;

a second matching line for selectively connecting a first position of said first matching line to ground; and

a third matching line for selectively connecting a second position of said

first matching line to ground.

3. The switchable power divider as claimed in claim 2, wherein said impedance

matching unit further comprises: first switching means connected to said second matching line so as to selectively connect the first position of said first matching line to ground through said

second matching line; and second switching means connected to said third matching line so as to selectively connect the second position of said first matching line to ground through said

third matching line.

4. The switchable power divider as claimed in claim 3, wherein said first

switching means comprises: a first capacitor having a first terminal connected to ground; a first inductor connected between a second terminal of said first capacitor and a first end of said second matching line;

a diode having an anode connected to a second end of said second matching

line and a cathode connected to the first position of said first matching line; and a second inductor connected between a third position of said first matching

line and ground;

wherein a biasing signal is provided to a connection between said first capacitor and

said first inductor.

5. The switchable power divider as claimed in claim 4, wherein said first

switching means further comprises: a second capacitor connected between said input port and the first end of

said first matching line; and a third capacitor connected between the second end of said first matching line and said dividing node.