WO2002019535A1 - Mise en place efficace de materiel d"un algorithme de compression - Google Patents

Mise en place efficace de materiel d"un algorithme de compression Download PDF

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Publication number
WO2002019535A1
WO2002019535A1 PCT/EP2001/009567 EP0109567W WO0219535A1 WO 2002019535 A1 WO2002019535 A1 WO 2002019535A1 EP 0109567 W EP0109567 W EP 0109567W WO 0219535 A1 WO0219535 A1 WO 0219535A1
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Prior art keywords
logic
cam
data
bit
output
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PCT/EP2001/009567
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English (en)
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WO2002019535A9 (fr
Inventor
Mark Buer
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Koninklijke Philips Electronics N.V.
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Priority to JP2002523721A priority Critical patent/JP2004507858A/ja
Priority to EP01958083A priority patent/EP1316154A1/fr
Publication of WO2002019535A1 publication Critical patent/WO2002019535A1/fr
Publication of WO2002019535A9 publication Critical patent/WO2002019535A9/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/3084—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction using adaptive string matching, e.g. the Lempel-Ziv method

Definitions

  • the present invention concerns data compression and decompression. More particularly, this invention relates to efficient hardware implementation of a compression algorithm.
  • Data compression can be used when storing or transmitting data in which there exists redundancy. Such compression allows the effective size of data to be reduced without information loss. The density of information is increased allowing for faster transmission times and requiring less storage resources.
  • Jacob Ziv and Abraham Lempel proposed two adaptive data compression schemes which construct a dictionary of codes representing unique strings of previous data symbols. These algorithms have been implemented in a number of variations. See for example, the implementations in USPN 5,339, 076, USPN 5,455,576, USPN 5,469,161, USPN 532,693, USPN 5,532,694, USPN 642,112, USPN 5,771,010, USPN 5,818,873, USPN 5,828,324, USPN 5,877,714 and USPN 5,936,560.
  • logic circuitry performs a matching algorithm function.
  • a memory produces a match signal that indicates which memory cells contain data that matches input address data to the memory.
  • a first logic AND function performs a logic AND between a current value of the match signal currently produced by the memory for the input address data with a prior value of the match signal produced by an immediately prior input address data.
  • a buffer holds index data.
  • a second logic AND function compares output of the first logic AND function with the index data. Output of the second logic AND function is returned to the buffer as new index data.
  • Index logic generates an offset based on the index data stored in the buffer.
  • a send byte function asserts a send byte signal when the match signal is zero and when the output of the second logic AND function is zero.
  • a length counter is incremented for every cycle in which the send byte signal is not asserted.
  • an offset ready logic generates an offset ready signal when the output of the second logic AND function has only one bit set to logic one. Also, substitution logic substitutes all logic ones for the index logic as input to the second logic AND function on a cycle immediately after the send byte signal is asserted.
  • the memory is implemented as a content addressable memory (CAM) in which data is not shifted.
  • CAM content addressable memory
  • a first shift function performs a one bit shift of the prior value before the prior value is received by the first logic AND function.
  • a second shift function performs a one bit shift of the index data before the index data is received by the second logic AND function.
  • the memory can be implemented using a FIFO CAM.
  • the CAM includes an address input for receiving CAM address signals.
  • the FIFO CAM also includes a plurality of CAM cells tiled together.
  • Each CAM cell includes a cell address input for receiving the CAM address signals.
  • a data input receives data to be stored in the CAM cell.
  • Storage logic stores the data received at the data input.
  • a data output presents as output the data stored in the storage logic.
  • Match logic compares the data stored in the CAM cell with the CAM address signals.
  • the match logic produces a match signal that indicates when the data stored in the CAM cell matches the CAM address signals.
  • the CAM cells are tiled together by connecting the data output for one CAM cell to the data input for another CAM cell.
  • the storage units are implemented using a plurality of flip-flops.
  • the match logic includes a plurality of logic XNOR gates and a logic
  • Each XNOR gate receives as input a bit of the data stored in the CAM cell, and a bit of the CAM address signals.
  • the logic NAND gate performs a logic NAND function on output from all of the plurality of logic XNOR gates.
  • the CAM cell can additionally include a validity input for receiving a validity bit that indicates whether the data to be stored in the CAM cell is valid. The validity bit is stored in the CAM cell and is presented as output along with the associated data.
  • the present inventions allows for an efficient hardware implementation of a loss-less compression algorithm that is compatible with the ANSI X3.241-1994 specification (known as Stacker LZSTM)
  • Figure 1 is a block interface for a compression engine in accordance with a preferred embodiment of the present invention.
  • Figure 2 shows implementation of a bus interface for the compression engine shown in Figure 1 in accordance with a preferred embodiment of the present invention.
  • Figure 3 shows the structure for a CAM cell in accordance with a preferred embodiment of the present invention.
  • Figure 4 shows CAM cells tiled together in accordance with a preferred embodiment of the present invention.
  • Figure 5 is a block diagram that shows the input/output interface to a CAM in accordance with a preferred embodiment of the present invention.
  • Figure 6 shows a hardware implementation of a compression matching algorithm in accordance with a preferred embodiment of the present invention.
  • Figure 7 illustrates compression data flow through the compression matching algorithm shown in Figure 6 in accordance with a preferred embodiment of the present invention.
  • Figure 8 shows decompression data flow in accordance with a preferred embodiment of the present invention.
  • Figure 9 gives an example of compressed data in accordance with a preferred embodiment of the present invention.
  • Figure 10 shows the structure for a CAM cell in accordance with an alternative preferred embodiment of the present invention.
  • Figure 11 shows a hardware implementation of a compression matching algorithm in accordance with an alternative preferred embodiment of the present invention.
  • Figure 1 is a block interface for a compression engine 10.
  • the interface includes a one bit clock (CLK) input 11, a one bit reset (RST_N) input 12, a one bit compress input 13, a one bit write input 14, a four bit last (LAST[3:0]) input 15, a thirty-two bit data input (DI) 16, a one bit read input 17, a ten-bit address (A) input 18, a one bit match select (MSEL) input 10, a one bit input ready (IRDY) output 21, a one bit output ready (ORDY) output 22, a four bit (BE) output 23, a thirty-two bit data output (DO) 24 and a one-bit busy output 25.
  • CLK one bit clock
  • RST_N reset
  • MSEL one bit match select
  • IRDY input ready
  • ORDY one bit output ready
  • BE four bit
  • DO thirty-two bit data output
  • Compression engine 10 is reset through reset (RST_N) input 12 to clear the history information from frame to frame.
  • the last word of data is signaled (per byte) through control signals four bit last (LAST[3:0]) input 15.
  • the output from compression engine 10 will continue to process and deliver data until the BUSY signal on one-bit busy output 25 is negated.
  • Compression engine 10 is a self-throttled compression engine capable of compressing or decompressing a byte of data (8 bits) per clock cycle.
  • compression engine 10 utilizes a simple synchronous interface 30 to a bus 31 for input and output of compressed and decompressed data. This is shown in Figure 2.
  • Compression engine 10 throttles the input of data 35 and the output of data 34 through control signals 33.
  • Compression engine 10 processes data a byte per clock signal 32.
  • a clock signal 32 is used to synchronize timing of bus interface 30 and compression engine 10.
  • Compression engine 10 implements a loss-less compression algorithm that is compatible with the ANSI X3.241 -1994 specification (known as Stacker LZSTM) for frames less than or equal to 2048 bytes.
  • the compression of the binary data stream is accomplished by finding repetitive patterns in the data.
  • Compression engine 10 is an improved implementation in that compression engine 10 does not use a sliding window for data since an entire packet is contained in the history table.
  • compression engine 10 uses a sliding window for the implementation of ANSI X3.241-1994.
  • a content addressable memory (CAM) component of compression engine 10 must operate as a first-in- first-out memory (FLFO) where each byte in the CAM gets shifted down as it is loaded into the CAM block.
  • FLFO first-in- first-out memory
  • Compressed data is represented by data and string tokens.
  • the data tokens are used to represent actual data byte values.
  • the string tokens are used to designate repetitive patterns in the packet.
  • the data token is encoded as a "0" followed by the 8 bits of actual data.
  • the string token consists of " 11 " followed by a 7 bit offset into the history buffer (within the last 2048 bytes of data) and the length of the string pattern.
  • the string token consists of "10" followed by an 11 bit offset into the history buffer (within the last 2048 bytes of data) and the length of the string pattern.
  • the length of the string pattern is performed in blocks of 15 bytes, thus a string length of '1111' indicates a string pattern having a length of 15 bytes of data, a string length of l 1 indicates a string pattern having a length of 30 bytes of data and a string length of '111111110111' indicates a string pattern having a length of 37 bytes of data.
  • the string token is built based on the size of the offset and the size of the length fields. Since each data token requires one extra bit, the data may expand when operated on by the compression algorithm.
  • the maximum expansion ration is 9/8 or 12.5% expansion.
  • the maximum compression ratio is limited by the requirement to output at least four bits for every 15 bytes of data (30/1 for infinite long pattern of the same character).
  • the end marker is constructed as a special string token with an offset of 0x0 (extra zeros are added after the end marker to byte align the data).
  • a pipelined implementation is used to implement the ANSI X3.241 - 1994 specification.
  • the pipeline implementation allows for minimum storage of data and retains the highest throughput performance.
  • a sliding window is used for the history buffer in order for the algorithm to compress packets larger than the history buffer.
  • a two kilobyte sliding window is employed.
  • a redundant string is found by comparing the current byte with the sliding window of history information.
  • the history buffer contains the last 2048 bytes of processed information (every byte that is processed appears in the history buffer after the comparison even when a match occurs). If the byte does not match any location in the history buffer, then the byte is passed to the output as a data token.
  • a content addressable memory is an ideal device for storage of the history buffer data.
  • the CAM For optimal performance when implementing a sliding window architecture, the CAM must have the characteristics of a FIFO such that as each byte is loaded, the entire CAM is shifted down in a single clock period.
  • FIG. 3 shows the structure for a CAM cell 51.
  • CAM cell 51 contains eight bits of register storage implemented by flip flops (FF) 52.
  • the register storage receives input D[7:0] and outputs Q[7:0].
  • a comparator implemented using logic XNOR gates 53 and a logic NAND gate 54 indicates whether there is a match between Q[7:0] and the CAM address CA[7:0].
  • a valid input bit (VI) is stored in a flip-flop 55 to produce a valid output bit (VO) that indicates when the location specified by D[7:0] contains valid information.
  • Logic NOR gate 56 produces an output (MATCH) signal which is registered through flip- flop 57 to enhance the speed at which CAM cell 51 can operate.
  • CAM cells are tiled together to construct the entire
  • CAM block which serves as a history buffer. This is represented in Figure 4 by CAM cell 61, a CAM cell 62 and a CAM cell 63 tiled together as shown.
  • the LOAD and CAM address CA [7:0] signals are common across the entire array of tiled CAM cells.
  • the reset (RST_N) signal is used to clear the entire array (valid bits) in a single clock by flushing the history buffer. Since the history buffer is 2048 bytes long, there are 2048 CAM cells.
  • a byte of data DI[7:0] enters CAM cell 61 along with a validity in (VI) signal that indicates whether the byte of data is valid.
  • VI validity in
  • FIG. 5 is a block diagram that shows the input/output interface to a CAM 71.
  • Input to CAM 71 is a LOAD signal, a Write signal, a data in byte DI [7 :0] , a CAM address CA [7:0], and an eleven bit address A[10:0].
  • CAM 71 produces a one byte data out DO [7:0] and an indication of a match (MATCH [2047:0]) for each of the 2048 CAM cells.
  • the eleven bit address A [10:0] provides direct read/write access to each CAM register (cell). This is provided for test purposes and allows the same storage elements to be used for the decompression of the data.
  • the direct memory access to the CAM can be used to read out the correct byte in the data stream by setting the read address to the depth of the pipeline without the requirement for extra buffering.
  • CAM 71 The size of CAM 71 is considerable. Implemented as shown in Figures 3, 4 and 5, the gate count for CAM 71 is approximately 212,000 gates. The size can be considerably reduced by constructing a custom lay out cell to implement CAM 71 (much like a compiled memory). This also improves the speed at which CAM 71 is able to operate.
  • the registered match values (as represented by flip-flop 57 in Figure 3) delays the output data within the pipeline by a clock period. This may be removed in slower speed applications to reduce the gate count of the implementation.
  • Figure 6 shows a hardware implementation of a compression matching algorithm.
  • a one byte latch (BYTE) 82 holds incoming data to be inserted into CAM 71.
  • a logic OR gate 87 performs a logic OR function on the 2048 MATCH bits to produce a single bit to indicate whether any match has occurred.
  • a value of "1" is placed as an input 81 to the address A[10:0] of CAM 71.
  • a register 83 holds the 2048-bit match value for the previous clock cycle.
  • a logic AND gates 84 performs a bit by bit logic AND between the
  • Logic AND gates 85 performs a bit by bit logic AND of the 2048-bit output value logic AND gate 84 with the 2048-bit out of logic OR gates 86.
  • the output of logic AND gates 85 is stored in register 88.
  • Logic OR gates 86 performs a logic OR of the values stored in register 88 with the one bit value stored in a flip- flop 89 to produce a 2048 bit output. When the one bit value stored in flip-flop 89 is logic 1, logic OR gates 86 produces an output signal of 2048 logic ones.
  • a logic OR gate 91 performs a logic OR on the 2048 bit output of logic AND gates 85.
  • a logic NAND gate 95 performs a logic NAND function between the one-bit output of logic OR gate 87 and the one-bit output of logic OR gate 91 to produce a SEND BYTE signal.
  • the matching algorithm looks for "adjacent" matches to determine the redundant string.
  • the formation of the string is not saved per se as a string. Only the adjacent matches are tracked as the string found in the history buffer.
  • the adjacent matches are constructed by looking for transitions from the previous match vector to the current state of the match vector.
  • the offset which is output by an index block 96, can be determined directly from the last adjacent match that is found. Therefore, the offset is known as soon as one and only one adjacent match is detected.
  • a "one" function 90 detects when one and only one adjacent match is detected and stores an inrlir.afinn in lin-flrm Q? TTHn-flrvn 09 crp.naratpis an nffcp.t rp.arlv f ⁇ FFRTYV siomal function 96 that operates as a priority encoder. Index 96 produces an eleven bit offset ([10:0] and an Off7bit signal that indicates when only seven bits (i.e., a seven bit offset) of the eleven bit offset are to be used.
  • Length counter 94 performs an increment based on the signal from logic NAND gate 95.
  • the eight bit length (LEN[7:0]) output by length counter 94 is determined by the number of consecutive matching bytes that are found.
  • the length of the string is normally delivered to an output buffer in increments of four bits.
  • the delivery of the encoded length four bits at a time ensures that the length can be of infinite size.
  • the performance is also enhanced since the length of the string (all but the final 4 bits) can be delivered to the output buffer as the string match is incrementing.
  • the length ready (LENRDY) signal indicates when a length is ready.
  • the LEN8BIT output indicates length is 8-bit length.
  • the LEN2BIT output indicates the length is 2 bits. The default is four bits. The reason for use of 8-bit lengths is described below.
  • Input buffer 100 transfers data eight bits at a time to byte latch 82 (shown in Figure 6). The individual bytes are extracted from input buffer 100 and pipelined into the datapath of matching algorithm 101. Thirty-two bit data output is buffered by an output buffer 102. Output buffer
  • 102 is used to gather the compressed data stream information (data tokens and string tokens) and align them to a word boundary.
  • the output OFFRDY is driven active at the end of the string (if not already active) to force the output of length.
  • the LENRDY output is also asserted at the end of a string to ensure that the last bits of the encoded length are read.
  • the length may take a number of clocks to transfer to output buffer 102 due to the fact that the offset may not resolve until the end of the matching string.
  • the effect is minimized by increasing the bit width of the length output to the output buffer.
  • bit width (rather than 4 bit width) the worst case is that 1024 bytes of data have been collected and the string is terminated at that point. It will take one clock to transfer the offset and 35
  • the first two bytes of every string is pipelined to output buffer 102 through CAM 71 since the source pattern requires at least two bytes for a string match.
  • a byte is sent to output buffer from DO [7:0] lines of CAM 71 each time the SEND BYTE signal goes active, except for the first byte on a zero to one transition of SEND BYTE. This indicates that the end of string is reached and the string token is finished.
  • Input buffer 100 transfers data eight bits at a time to byte latch 82 (shown in Figure 6). The individual bytes are extracted from input buffer 100 and pipelined into the data path of matching algorithm 101.
  • the output buffer (also 32 bits) is used to gather the compressed data stream information (data tokens and string tokens) and align them to a word boundary.
  • Decompression of compressed data is a much simpler task than compression.
  • the CAM 71 can be reused for the decompression of the data.
  • Input buffer 100 is utilized to maintain a byte aligned data stream while striping off the data and string tokens.
  • Figure 8 shows decompression data flow.
  • the string tokens are parsed to extract an offset field 117 and length fields.
  • Offset field 117 is extracted as an entire field while length 114 is extracted four bits at a time. Each length field is decoded by a decode 113 and result loaded into a length counter 114 that is used to determine the length of the string in multiples of 4 bits. The offset value (minus one) is used to address the CAM to extract the proper byte. Each decompressed byte (DO [7:0]) is delivered to output buffer 102 (shown in Figure 7) and placed in CAM 71 for subsequent use as history information.
  • a multiplexer (MUX) 112 selects either byte 111 or DO [7:0] based on whether length counter 114 indicates that length is zero (i.e., a data byte is being processed) or length is greater than zero (i.e., a string token is being processed).
  • Length counter 114 decrements for each byte that is processed as part of the string until zero is reached.
  • Length counter 114 has a one-bit output value that indicates when the length is greater than 0.
  • a logic OR gate 115 performs a logic OR on this value with a WRITE signal before forwarding it to the LOAD input of CAM 71.
  • a data string is defined as per ANSI X3.241-1994 as the following 16 byte character string "A B A A A A A A A C A B A B A B A”.
  • the hex string equivalent is "41 4241 41 41 41 41 43 41 4241 4241 42 41".
  • the resulting compressed string is generated with a pipeline delay of 2 cycles as "20 90 88 38 IC 21 E2 5C 15 80".
  • Figure 9 shows the compressed value.
  • Top row 41 shows the hex values.
  • Row 42 shows the binary bit encoding of the hex value.
  • the input stream is parsed to strip the bytes and string tokens out of the stream.
  • Each data token is converted to a byte by removing the leading zero.
  • the byte is then provided directly to the output and loaded into the CAM.
  • the string tokens are decoded and used to expand the data from the history buffer (CAM contents).
  • the expansion of the data is accomplished by applying the offset (minus one) as the address (A) to the CAM block.
  • the resulting data out (DO) is then loaded into CAM 71 and presented as an output byte. The process is continued until the length of the string token has been decremented to zero.
  • bit 141 is a
  • next eight bits 142 are a data value "41" which is placed in CAM 71 and utilized as one byte of data out.
  • CAM 71 is storing the following hex value "41" (starting with location 0 in CAM 71).
  • a bit 143 is a "0" indicating that the next eight bits are uncompressed data.
  • Next eight bits 144 are a data value "42" which is placed in CAM 71 and utilized as one byte of data out.
  • CAM 71 is storing the following hex values " 42 41" (starting with location 0 in CAM 71).
  • a bit 145 is a "0" indicating that the next eight bits are uncompressed data.
  • Next eight bits 146 are a data value "41" which is placed in CAM 71 and utilized as one byte of data out.
  • CAM 71 is storing the following hex values "41 4241" (starting with location 0 in CAM 71).
  • a two-bit string 147 indicates that a string offset and length follow. Since the value of the two bits are "11" this indicates that the offset is described in seven bits (i.e., has a value less than or equal to 127). If the offset had been greater than 127, eleven bits would have been used and the value of two-bit string 147 would have been "10".
  • a seven bit offset 148 indicates the offset is equal to "1". This offset less 1 (OFFSET - 1) is placed on the address (A[10:0]) input of CAM 71.
  • the address of 0 (OFFSET - 1) results in the value "41" being output from CAM 71.
  • This value is utilized as the one byte of data out (DO[7:0]) and placed back in CAM 71.
  • CAM 71 is storing the following hex values "41 41 42 41". The length is decremented to 4.
  • the address of 0 (OFFSET - 1) results in the value "41" being output from CAM 71.
  • This value is utilized as the one byte of data out (DO[7:0]) and placed back in CAM 71.
  • CAM 71 is storing the following hex values "41 41 41 4241” .
  • the length is decremented to 3.
  • the address of 0 (OFFSET - 1) results in the value "41” being output from CAM 71. This value is utilized as the one byte of data out (DO[7:0]) and placed back in CAM 71. As aresult, CAM 71 is storing the following hex values "41 41 41 41 42 41”. The length is decremented to 2.
  • the address of 0 (OFFSET - 1 ) results in the value "41” being output from CAM 71. This value is utilized as the one byte of data out (DO[7:0]) and placed back in CAM 71. As a result, CAM 71 is storing the following hex values "41 41 41 41 41 4241". The length is decremented to 1.
  • a bit 150 is a "0" indicating that the next eight bits are uncompressed data.
  • Next eight bits 151 are a data value "43” which is placed in CAM 71 and utilized as one byte of data out. As a result, CAM 71 is storing the following hex values "43 41 41 41 41 41 41
  • a two-bit string 152 indicates that a string offset and length follow. Since the value of the two bits are "11" this indicates that the offset is described in seven bits (i.e., has a value less than or equal to 127).
  • a seven bit offset 153 indicates the offset is equal to "9". This offset less 1 (OFFSET - 1) is placed on the address (A[10:0]) input of CAM 71.
  • the address of 8 (OFFSET - 1) results in the value "41” being output from CAM 71. This value is utilized as the one byte of data out (DO[7:0]) and placed back in CAM 71. As a result, CAM 71 is storing the following hex values "41 43 41 41 41 41 41 42 41". The length is decremented to 2.
  • the length is decremented to 1.
  • a two-bit string 155 indicates that a string offset and length follow. Since the value of the two bits are "11" this indicates that the offset is described in seven bits (i.e., has a value less than or equal to 127).
  • a seven bit offset 156 indicates the offset is equal to "2". This offset less 1 (OFFSET - 1) is placed on the address (A[10:0]) input of CAM 71.
  • the address of 1 results in the value "42" being output from CAM 71.
  • This value is utilized as the one byte of data out (DO[7:0]) and placed back in CAM 71.
  • CAM 71 is storing the following hex values "42 41 42 41 43 41 41 41 41 41 42 41 ".
  • the length is decremented to 3.
  • the compression algorithm can be simplified to a non-windowed algorithm by restricting the packet size to be smaller than the history buffer (2048 bytes). By restricting the packet size the history buffer does not need to "slide" with the packet data to contain the last 2048 bytes of information.
  • a standard CAM structure is used to implement the algorithm since the data will never wrap around the history buffer. Because the data does not wrap around the history buffer (CAM), there is no need to keep track of start and end pointers for the history table. Additionally, there is no need to continue to shift the match output connections to ensure adjacency for the character comparison in the string matching. There still is one disadvantage to utilizing a standard CAM structure even in a non- windowed environment.
  • bit shift for the calculation of the string match must now be done external to the CAM.
  • the bit shift was implicit since the CAM shifted the data as each byte was loaded.
  • Figure 10 shows an example structure for a CAM cell 51 for this alternative embodiment of the present invention.
  • An eight-bit memory array 121 stores the value for the memory cell.
  • a comparator 121 compares this with the CAM address CA[7:0].
  • a logic NAND gate performs a logic AND on the output of comparator 121 and a valid bit. The result is stored in a flip-flop 121.
  • the output of flip-flop 121 is a one-bit match signal which indicates whether there is a match of valid data from CA [7:0] to data stored in eight-bit memory array 121.
  • the standard CAM cell shown in Figure 10 does not chain data together. It is simply a memory array with each element being compared to the CAM address (CA). The cells are tiled together and a standard memory read/write access is available. Typically the CAM compare is an exclusive access to a read or a write to the CAM memory array and valid bit.
  • the MATCH output may or may not be registered inside of the CAM. The registering of the MATCH output is simply a pipeline delay and timing enhancement.
  • Figure 11 shows a hardware implementation of a compression matching algorithm for the alternative preferred embodiment.
  • a one byte latch (BYTE) 182 holds incoming data to be inserted into a CAM 171.
  • a logic OR gate 187 performs a logic OR function on the 2048 MATCH bits to produce a single bit to indicate whether any match has occurred.
  • a register 183 holds the 2048-bit match value for the previous clock cycle.
  • a logic AND gates 184 performs a bit by bit logic AND between the 2048-bit match value for the previous clock cycle with the 2048-bit match value for the present clock cycle to produce a 2048 bit output.
  • An "1-1" function 201 performs a one bit shift of the stored match value in register 183 (no gates required, simply a wiring shift).
  • Logic AND gates 185 performs a bit by bit logic AND of the 2048-bit output value logic AND gate 184 with the 2048-bit out of logic OR gates 186. The output of logic AND gates 185 is stored in register 188.
  • Logic OR gates 186 performs a logic OR of the values stored in register 188 with the one bit value stored in a flip-flop 189 to produce a 2048 bit output.
  • An "1-1" function 202 performs a one bit shift of the stored match value in register 188 before it is forwarded to logic OR gates 186.
  • a logic OR gate 191 performs a logic OR on the 2048 bit output of logic AND . gates 185.
  • a logic NAND gate 195 performs a logic NAND function between the one-bit output of logic OR gate 187 and the one-bit output of logic OR gate 191 to produce a SEND BYTE signal.
  • the matching algorithm looks for "adjacent" matches to determine the redundant string.
  • the formation of the string is not saved per se as a string. Only the adjacent matches are tracked as the string found in the history buffer.
  • the adjacent matches are constructed by looking for transitions from the previous match vector to the current state of the match vector.
  • One function 190 detects when one and only one adjacent match is detected and stores an indication in flip-flop 192.
  • Flip-flop 192 generates an OFFRDY signal 193.
  • the offset from an index 196 can be delivered to the data stream prior to the entire string match being found.
  • the delivery of the offset early enhances the overall performance of the block since the offset is usually determined in advance of the string match completing (especially for short strings).
  • Length counter 194 performs an increment based on the signal from logic NAND gate 195.
  • the eight bit length (LEN[7:0]) output by length counter 194 is determined by the number of consecutive matching bytes that are found.
  • the length of the string can be delivered to an output buffer in increments of four bits.
  • the delivery of the encoded length four bits at a time ensures that the length can be of infinite size.
  • the performance is also enhanced since the length of the string (all but the final 4 bits) can be delivered to the output buffer as the string match is incrementing.
  • the LENRDY indicates when a length is ready.
  • the LEN8BIT output indicates length is 8-bit length.
  • the LEN2BIT output indicates the length is 2 bits.
  • the offset cannot be guaranteed to resolve to one and only one string match until halfway through CAM 171 (1024 bytes).
  • Length counter 194 must therefore be able to hold a count up to 1024 until the offset is resolved (OFFRDY is asserted).
  • the length function will output 8 bits at a time until it decrements the stored length to less than a count of 16. Once the length is less than 16 and the offset is resolved, then the length function will output 4 bits at a time until the end of the string match.
  • a string length block 203 contains the total length of the input data stream in bytes. String length block 203 is used to address the next CAM location for writing the byte of data into CAM 171. String length block 203 is also used to generate the offset value since the CAM data is not shifting in this architecture. Sub block 199 receives the output from index 196 and output of the string length 203 and produces an eleven bit offset ([10:0]. A comparator 200 compares this value with the number "128" to produce an Off7bit signal that indicates when only a seven bit offset is to be used. The output data byte must be registered to ensure that the data output pipeline lines up with the matching pipeline.
  • the offset must be subtracted from the current string length to calculate the position within CAM 171.
  • a data string is defined as per ANSI X3.241-1994 as the following 16 byte character string "A B A A A A A A C A B A B A”.
  • the hex string equivalent is "41 42 41 41 41 41 41 43 41 42 41 42 41”.
  • the resulting compressed string is generated with a pipeline delay of 2 cycles as "20 90 88 38 IC 21 E2 5C 15 80".
  • the input stream is parsed to strip the bytes and string tokens out of the stream.
  • Each data token is converted to a byte by removing the leading zero.
  • the byte is then provided directly to the output and loaded into the CAM.
  • the string tokens are decoded and used to expand the data from the history buffer (CAM contents).
  • the expansion of the data is accomplished by applying the offset (minus one) as the address (A) to the CAM block.
  • the resulting data out (DO) is then loaded into CAM 71 and presented as an output byte. The process is continued until the length of the string token has been decremented to zero.
  • the offset remains constant as the length is decremented when extracting the string from the history buffer.
  • the address equation must be updated for each expansion step to ensure that the new string length is taken into consideration thus the address (A) is incremented with each byte.
  • bit 141 is a "0" indicating that the next eight bits are uncompressed data.
  • Next eight bits 142 are a data value "41" which is placed in CAM 171 and utilized as one byte of data out.
  • CAM 171 is storing the following hex value "41" (starting with location 0 in CAM ⁇ 171).
  • the string length is incremented to equal 1.
  • Bit 143 is a "0" indicating that the next eight bits are uncompressed data.
  • CAM 171 is storing the following hex values "41 42" (starting with location 0 in CAM 171). String length is incremented to equal 2.
  • Bit 145 is a "0" indicating that the next eight bits are uncompressed data.
  • CAM 171 is storing the following hex values "41 4241" (starting with location 0 in CAM 171). String length is incremented to equal 3.
  • Two-bit string 147 indicates that a string offset and length follow. Since the value of the two bits are "11" this indicates that the offset is described in seven bits (i.e., has a value less than or equal to 127). If the offset had been greater than 127, eleven bits would have been used and the value of two-bit string 147 would have been "10".
  • Seven bit offset 148 indicates the offset is equal to "1".
  • String length, minus offset minus 1 (OFFSET - 1) is placed on the address (A[10:0]) input of CAM 171.
  • the address of 0 (OFFSET - 1) results in the value "41" being output from CAM 171.
  • This value is utilized as the one byte of data out DO[7:0]) and placed back in CAM 171.
  • CAM 171 is storing the following hex values "41 42 41 41" (starting with location 0 in CAM 171). The length is decremented to 4. The string length is incremented to equal 4.
  • the address of 0 (OFFSET - 1) results in the value "41” being output from CAM 171.
  • This value is utilized as the one byte of data out (DO[7:0]) and placed back in CAM 171.
  • CAM 171 is storing the following hex values "41 4241 41 41”.
  • the length is decremented to 3.
  • the string length is incremented to equal 5.
  • the address of 0 (OFFSET - 1) results in the value "41” being output from CAM 171.
  • This value is utilized as the one byte of data out (DO[7:0]) and placed back in CAM 171.
  • CAM 171 is storing the following hex values "41 42 41 41 41”.
  • the length is decremented to 2.
  • the string length is incremented to equal 6.
  • the address of 0 (OFFSET - 1) results in the value "41” being output from CAM 171.
  • This value is utilized as the one byte of data out (DO[7:0]) and placed back in CAM 171.
  • CAM 171 is storing the following hex values "41 42 41 41 41 41”.
  • the length is decremented to 1.
  • the string length is incremented to equal 7.
  • the address of 0 (OFFSET - 1) results in the value "41” being output from CAM 171.
  • This value is utilized as the one byte of data out (DO[7:0]) and placed back in CAM 171.
  • CAM 171 is storing the following hex values "41 42 41 41 41 41 41”.
  • the length is decremented to 0.
  • the string length is incremented to equal 8.
  • Bit 150 is a "0" indicating that the next eight bits are uncompressed data.
  • CAM 171 is storing the following hex values "41 4241 41 41 41 41 43”.
  • the string length is incremented to equal 9.
  • Two-bit string 152 indicates that a string offset and length follow. Since the value of the two bits are "11" this indicates that the offset is described in seven bits (i.e., has a value less than or equal to 127).
  • Seven bit offset 153 indicates the offset is equal to "9". This offset less 1 (OFFSET - 1) is placed on the address (A[10:0]) input of CAM 171.
  • the address of 8 results in the value "41” being output from CAM 171.
  • This value is utilized as the one byte of data out (DO[7:0]) and placed back in CAM 171.
  • CAM 171 is storing the following hex values "41 42 41 41 41 41 41 43 41".
  • the length is decremented to 2.
  • the string length is incremented to equal 10.
  • the address of 8 results in the value "42" being output from CAM 171.
  • This value is utilized as the one byte of data out (DO[7:0]) and placed back in CAM 171.
  • CAM 171 is storing the following hex values "41 42 41 41 41 41 41 43 41 42".
  • the length is decremented to 1.
  • the string length is incremented to equal 11.
  • the address of 8 results in the value "41 " being output from CAM 171.
  • This value is utilized as the one byte of data out (DO[7:0]) and placed back in CAM 171.
  • CAM 171 is storing the following hex values "41 42 41 41 41 41 41 43 41 42 41".
  • the length is decremented to 0.
  • the string length is incremented to equal 12.
  • Two-bit string 155 indicates that a string offset and length follow. Since the value of the two bits are "11" this indicates that the offset is described in seven bits (i.e., has a value less than or equal to 127). Seven bit offset 156 indicates the offset is equal to "2". This offset less 1
  • the address of 1 results in the value "42" being output from CAM 171.
  • This value is utilized as the one byte of data out (DO[7:0]) and placed back in CAM 171.
  • CAM 171 is storing the following hex values "41 42 41 41 41 41 41 43 41 42 41 42".
  • the length is decremented to 3.
  • the string length is incremented to equal 13.
  • the address of 1 results in the value "41” being output from CAM 171.
  • This value is utilized as the one byte of data out (DO[7:0]) and placed back in CAM 171.
  • CAM 171 is storing the following hex values "41 4241 41 41 41 41 43 41 4241 42 41".
  • the length is decremented to 2.
  • the string length is incremented to equal 14.
  • the address of 1 results in the value "42" being output from CAM 171.
  • This value is utilized as the one byte of data out (DO[7:0]) and placed back in CAM 171.
  • CAM 171 is storing the following hex values "41 42 41 41 41 41 41 43 41 42 41 42".
  • the length is decremented to 1.
  • the string length is incremented to equal 15.
  • the address of 1 results in the value "41 " being output from CAM 171.
  • This value is utilized as the one byte of data out (DO[7:0]) and placed back in CAM 171.
  • CAM 171 is storing the following hex values "41 42 41 41 41 41 41 43 41 42 41 4241”.
  • the length is decremented to 0.
  • the string length is incremented to equal 16.
  • Eight bit string 158 is an end marker indicating the end of the data stream.
  • the non-windowed architecture in Figures 10 and 11 has a nice feature of not requiring any more memory than CAM 171 for uncompressed data.
  • the data can be completely loaded into the CAM 171 prior to compression.
  • the data can be bursted into CAM 171 prior to compression of the stream of data (freeing up bus bandwidth).
  • the output stream is returned in the normal throttled manner.
  • Decompression is the opposite function from compression.
  • the input stream is feed into the block in a throttled manner while the output is collected in the CAM 171.
  • the uncompressed data can then be bursted out of the CAM 171.
  • the larger amount of data (uncompressed) in both cases is transferred as a burst packet.
  • the compressed stream in both cases is throttled to the input. Thus the overall required bus bandwidth and demand is reduced.
  • the content addressable memories described above require customized blocks for high performance/density implementations.
  • the utilization of static RAM for the history buffer in combination with an external comparison can still yield acceptable performance with the advantage of a compact non-custom solution.
  • This type of "CAM" implementation can be quite efficient especially for small packets.
  • the in-place algorithm for compression can be implemented very easily by tracking the number of bytes that are valid in a string length counter.
  • the use of a string length counter removes the requirement for storing valid bits in the memory (reduction of size) as the validity of each byte is determined by the depth of the string length.
  • the length counter is also used to determine how deep in the memory must be accessed for each pass of the algorithm (process one byte per pass).
  • a standard CAM in a windowed environment requires the use of a circular queue buffer (to make it look like a FIFO) in order to track the start of the history buffer within the CAM as the data wrapped.
  • a circular queue buffer makes the adjacent calculation extremely difficult (i.e., there is a need to multiplex the match lines to determine adjacent match).
  • the data never wraps around the CAM making it more efficient for this architecture.
  • CHAR(i) MATCH(i) and Prev(MATCH(i-l)) and (Prev(CHAR(i-l)) or Prev(SEND BYTE))
  • Prev() is the value just after the register (flip-flop output).

Abstract

Un circuit logique réalise une fonction d"algorithme de correspondance. Une mémoire engendre un signal de correspondance indiquant que les cellules de mémoire contiennent des données qui font correspondre les données d"adresse d"entrée à la mémoire. Une première fonction logique ET effectue un ET logique entre une valeur du moment du signal de correspondance produit par la mémoire pour les données d"adresse d"entrée et une valeur antérieure dudit signal produit par une donnée d"adresse d"entrée immédiatement antérieure. Un tampon maintient des données d"index. Une seconde fonction logique ET compare la sortie de la première fonction logique ET avec les données d"index. La sortie de la seconde fonction logique ET est retournée au tampon comme nouvelles données d"index. Une logique d"index génère un décalage basé sur les données d"index stockées dans le tampon. Une fonction d"envoi d"octets attribue un signal d"envoi d"octets, lorsque le signal de correspondance et la sortie de la seconde fonction logique ET sont à zéro. Un compteur de longueur est incrémenté à chaque cycle, durant lequel le signal d"envoi d"octets n"est pas attribué.
PCT/EP2001/009567 2000-08-29 2001-08-17 Mise en place efficace de materiel d"un algorithme de compression WO2002019535A1 (fr)

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