WO2002015388A2

WO2002015388A2 - Amplifier circuits and methods to provide smooth transition of amplifier outputs during powering sequences

Info

Publication number: WO2002015388A2
Application number: PCT/US2001/041681
Authority: WO
Inventors: Christopher F. Edwards; J. William Maney, Jr.
Original assignee: Maxim Integrated Products, Inc.
Priority date: 2000-08-11
Filing date: 2001-08-10
Publication date: 2002-02-21
Also published as: WO2002015388A3

Abstract

The present invention is an apparatus and method to control an output from an amplifier circuit during a powering sequence. A current control circuit is coupled to the amplifier circuit to provide smooth transition at the output during the powering sequence, including the power-up interval and the power-down interval, during which the amplifier is muted. This results in the establishment and the decay of the amplifier mid-supply bias point during the power-up and power-down sequences, respectively, at rates that do not have significant frequency components in the audible range, eliminating the static-like click or pop on power-up and power-down, yet still providing short power-up and power-down times.

Description

AMPLIFIER CIRCUITS AND METHODS TO PROVIDE SMOOTH TRANSITION OF AMPLIFIER OUTPUTS DURING POWERING SEQUENCES

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to amplifier circuits driving single-ended loads.

2. Background Information

When an amplifier circuit is used to drive a single- ended load such as a speaker or a headphone through a coupling capacitor, as illustrated in Figure 1, there is usually a sudden audible noise (e.g. a static-like pop or click) at power-up due to the sudden rate of change of the amplifier output, causing a current pulse through the speaker or headphone as the coupling capacitor Ccouple suddenly begins to charge to its steady state operating condition, namely the voltage Vbias. Normally, this is reduced by making capacitor C_bi_as large but practical start-up times eventually limit it. On power-down, several things can happen, depending on the type of amplifier used. When the amplifier circuit is a rail-to-rail output amplifier, there is a parasitic diode connecting the output to the supply voltage. On power-down, the output voltage drops with the supply voltage. When the supply voltage reaches ground, the output remains in a high impedance state at one diode drop above the supply rail, and the output will then slowly discharge toward zero volts. This drop in the supply rail can also cause a transient spike at the output, therefore also creating an audible sound. The severity of the audible sound depends on the rate at which the supply voltage collapses. When the amplifier does not have a rail-to-rail output, on power-down the amplifier remains in a high impedance state at its mid-range bias point (typically approximately half of the power supply voltage) , and then typically slowly discharges toward -ground through a bleed resistor Rbleed with a substantial time constant determined by the size of the coupling capacitor Ccouple and the bleed resistor Rbleed. The output is not audible at this time, since the bleed resistor is used to slowly (typically the time constant can be anywhere from several seconds to minutes) discharge the output voltage when the amplifier output goes to a high impedance. If the coupling capacitor fully discharges before power is reapplied, an audible sound will be created on power-up as with a rail-to-rail amplifier. However, if power is re-applied before the output voltage is fully discharged, as illustrated in Figure 2, an even louder audible spike will result as the amplifier initially forces the amplifier output voltage toward ground at the start of its power-on ramp, and then back upward to its normal mid- supply bias point as the power supply rail reaches its normal power on voltage. This forces the speaker voltage Vspeaker first negative, then positive as shown in Figure 3, creating the unwanted audible noise.

SUMMARY OF THE INVENTION

The present invention is an apparatus and method to control an output from an amplifier circuit during a powering sequence. A current control circuit is coupled to the amplifier circuit to provide smooth transition at the output during the powering sequence, including the power-up interval and the power-down interval, during which the amplifier is muted. This results in the establishment and the decay of the amplifier mid-supply bias point during the power-up and power-down sequences, respectively, at rates that do not have significant frequency components in the audible range, eliminating the static-like click or pop on power-up and power-down. This is accomplished without unreasonably long delays.

BRIEF DESCRIPTION OF THE DRAWINGS^'

The features and advantages of the present invention will become apparent from the following detailed description of the present invention in which:

Figure 1 is a diagram of a prior art amplifier circuit as used to drive a single-ended load such as a speaker or a headphone through a coupling capacitor.

Figure 2 is a curve illustrating the output spike of an amplifier of Figure 1 that is powered up before the coupling capacitor has fully discharged.

Figure 3 is curve illustrating the speaker input resulting from the output spike of Figure 2.

Figure 4 is a block diagram illustrating one exemplary embodiment of the present invention

Figure 5 is a block diagram of an exemplary current controlled regulator according to one embodiment of the present invention.

Figures 6a, 6b and 6c present representative curves showing the voltage at node VI and the bias capacitor charging current Ivb versus bias voltage Vbias, and the smooth amplifier output voltage, respectively, during power- up for one embodiment of the present invention.

Figures 7a, 7b and 7c present representative curves showing the voltage at node V2 and the bias capacitor discharge current Ivb versus bias voltage Vbias, and the amplifier output voltage, respectively, during the power-down sequence . Figure 8 presents an exemplary circuit for the current " controlled regulator of Figures 4 and 5.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention is an apparatus and method to control an output from an amplifier circuit during a powering sequence. A current control circuit is coupled to the amplifier circuit to provide smooth transition at the amplifier output during the powering sequence. The powering sequence includes a power-up interval and a power-down interval .

In accordance with the present invention, initially on power-up, the amplifier output current into the coupling capacitor for a single-ended load will mimic the current used to charge an element to the desired bias voltage (Vbias) setting the DC offset in the amplifier output, typically by a controlled ramp or a time constant. Therefore, if the current for initially charging the Vbias element is appropriately limited, the current into the single-ended load will also be appropriately limited. Specifically, if the startup and the shutdown pulses are spread into a ramp up and ramp down over a long period of time, for example, 200 ms, the "pop" will not be audible, and will not be heard at the output of the single-ended load.

Now referring to Figure 4, a block diagram illustrating one exemplary embodiment of the present invention may be seen. As in a prior art system such as illustrated in Figure 1, the input signal is capacitively coupled by Cin to the inverting input of an amplifier A through a resistor Rin, with the gain of the amplifier being determined by the ratio of the feedback resistor Rfb and the input resistor Rin. The output of the amplifier A is coupled through a coupling capacitor Ccouple to the speaker. The average mid-range output of the amplifier A is set by a bias signal, typically a bias voltage Vbias, to the positive input of the amplifier A by an appropriate bias voltage Vbias on the bias capacitor Cbias. Unlike the prior art, however, the bias,, in the example the bias voltage Vbias, is determined by a current provided by a current controlled regulator. In operation, when power is first applied to the amplifier A, the amplifier gain is initially substantially reduced. In the exemplary diagram of Figure 4, a muting switch SWm is closed to couple the amplifier output directly back to its inverting input. This couples the amplifier in a unity gain feedback configuration so that the output of the amplifier will be merely equal to the bias voltage Vbias, independent of the input signal . While such a muting switch is convenient for the stated purpose, other techniques for eliminating and/or at least very substantially reducing the signal content from the output of the amplifier A may also be used if desired. In any event, with little or no signal coupling to the amplifier output, the current controlled regulator provides a charging current to the bias capacitor Cbias in a manner and at a rate to establish the normal bias voltage for the amplifier while maintaining the output of the speaker substantially free of any audible noise. This may; be done by charging the bias capacitor to provide a voltage waveform on the bias capacitor that is substantially free of frequency components in the audible range. This, in turn, may be done by charging the bias capacitor Cbias using a voltage waveform which is free of sudden voltage changes, and thus substantially free of harmonic components of any substantial amplitude, particularly for the higher harmonics, and over a time period adequate to hold any substantial lower harmonics to below the audible frequency range.

Now referring to Figure 5, a block diagram of an exemplary current controlled regulator may be seen. The circuit, connected to the bias capacitor Cbias, comprises amplifiers Al and A2 , switches SWl and SW2 and resistors Rl, R2, R3, R5 and R6. Amplifier Al has an inverting input and two non-inverting inputs, one of which is coupled to a reference voltage Vref . The amplifier acts as a differential amplifier controlled by the inverting input and the lower of the two non-inverting inputs. Amplifier A2 acts as a conventional differential amplifier.

Switches SWl and SW2 preferably operate in a non- overlapping manner, switch SWl being closed for power-up and normal operation, and switch SW2 being closed during power- down, usually until the power to the circuit is terminated. When switch SWl is closed (SW2 open) , the bias capacitor Cbias is charged through resistor R3 by the output VI of amplifier Al . When switch SW2 is closed (SWl open), the bias capacitor Cbias is discharged through resistor R3 by the output V2 of amplifier A2. In the analysis to follow, it is assumed that resistors Rl and R2 are equal, and that resistors R5 and R6 are equal, though this is not a requirement, and in one embodiment, resistors Rl and R2 have somewhat different values.

With amplifier Al acting as described and for the assumed resistor values, for power-up, regardless of the state of charge, if any, of the bias capacitor Cbias: POWER-UP -.

SWl: closed SW2 : open

When Vbias < Vref Vi = 2Vbias

Ivb = (2Vbias - Vbias) /R3 = Vbias/R3 When Vbias Vref Vi = 2 ref Ivb = (2Vref - Vbias) /R3

POWER-DOWN: SWl: open

SW2: closed

When Vbias > Vref

Vi = 2Vref

V2 = 2Vbias - VI = 2 (Vbias Vref )

Ivb = - (2Vref - Vbias) /R3

When Vbias < Vref

V,. = 2Vbias

V2 = 0

Ivb = -Vbias/R3

These conditions are generally illustrated in Figures 6a and 6b, and 7a and 7b, which will be subsequently described in detail.

Now referring to Figure 8, an exemplary circuit for the current controlled regulator of Figures 4 and 5 may be seen. In this circuit, n-channel devices are identified by a number preceded by an "MN" designation, and p-channel devices are identified by a number preceded by an "MP" designation. Biases are provided by conventional current sources II and 12, details of which are not shown. The current II is mirrored by transistor MN1 to transistors MN6 and MN7. The current 12 is mirrored by transistor MP4 to transistors MP5 and MP22. Switches SWl and SW2 are comprised of transistors MN40 and MP40, and transistors MN41 and MP41, respectively. Inverter XI provides a complementary control signal so that both switches can be controlled by a single UP / DOWN signal Capacitors Cl and C2 provide circuit stability.

Consider first the initiation of the power-up sequence when the bias capacitor Cbias is fully discharged (Vbias =

0) . When the control signal UP / DOWN first goes high, switch

SWl is turned on and switch SW2 is off. UP / DOWN high turns off transistor MP10. However the current mirrored to transistor MN6 will be mirrored by transistor MP8 to transistor MP9, thus providing a minimum current into node VI. Because Vbias is substantially zero, transistor MPl is turned off. As a result of the current into node VI, the gate of transistor MP2 is at a slightly higher voltage than the gate of transistor MP3, resulting in greater current through transistor MP3 than transistor MP2. This higher current in transistor MP3 current is mirrored through transistor MN2 to transistor MN3 and node 1. Since the current in transistor MP2 is less than the current in transistor MN3 , node 1 is pulled low, so that transistor MN4 is turned off and no current is mirrored by transistor MP6 to transistor MP7. Still the minimum current into node VI begins to charge capacitor Cbias.

As capacitor Cbias charges (Vbias increases) , transistors MPl, MP2 and MP3 provide the input stage of amplifier Al . The gate of transistor MP2 is the negative amplifier input coupled between resistors Rl and R2 (see Figure 5 also) . The gates of transistors MPl and MP3 are the two positive inputs, the gate of transistor MPl being coupled to the reference voltage Vref and the gate of transistor MP3 being coupled to Vbias. Between the two transistors MPl and MP3 , the transistor with the lower voltage on its gate will determine the level of current through that side of the differential amplifier.

The exemplary circuit of Figure 8 for amplifier Al will source current into node VI, but is not capable of sinking current from the node. Thus for very low values of Vbias, the minimum current described provides the initial charging current, after which Al takes over to provide the additional charging current called for by the voltage Vbias generally in accordance with the relationships previously set forth herein. This avoids the situation predicted by the equation that at Vbias = 0V there is no charging current and the circuit would not start up. Now consider the initiation of the power-down sequence, initiated for example when the bias capacitor Cbias is charged to its normal mid-range operating voltage (Vbias = 2Vref in the exemplary embodiment) . When the control signal

UP / DOWN goes low, switch SWl is turned off and switch SW2 is on. UP / DOWN low turns on transistor MP10, pulling the gates of transistors MP8 and MP9 high so that the minimum current previously described with respect to amplifier Al is no longer mirrored to the output of amplifier Al (node VI) . However, the current mirrored to transistor MN7 provides a minimum discharge current to node V2. This discharge current has no functional effect when UP / DOWN is high (switch SW2 open) .

The input stage of amplifier A2 is comprised of transistors MP20 and MP21, the gate of transistor MP20 being the positive differential input and the gate of transistor MP21 being the negative differential input. The current in transistor MP21 is mirrored by transistor MN21 to transistor MN20, with any difference in currents in transistors MP20 and MN20 controlling the voltage of the gate of transistor MN24 to control the rate of discharge of the capacitor Cbias in accordance with the relationships previously set forth. The initial discharge current is determined by the minimum discharge current of transistor MN7, after which differential amplifier A2 provides the additional discharge current in accordance with the previous relationships. In addition, since in this embodiment A2 can only sink current, it avoids the possibility, suggested by those relationships, of a runaway condition if Vbias > 2 V_ref due to noise or some other perturbation.

Now referring to Figures 6a and 6b, curves showing the voltage at node VI and the current Ivb, respectively, during power-up plotted from the equations previously given may be seen. It will be noted from the equations that when the bias voltage Vbias equals zero, Ivb equals Vbias/R3 , which also would be zero. However, the minimum current during power-up assures that the bias capacitor Cbias begins to charge at a minimum predetermined rate, with the output of amplifier Al then providing the basically triangular waveform for Ivb shown in Figure 6b. Since, for the first half of the charging, namely the charging of the bias capacitor Cbias to Vref, the charging current Ivb is proportional to the bias voltage Vbias, yielding an exponentially increasing bias voltage Vbias for the first half of the bias capacitor charging cycle. During the second half of the bias capacitor charging cycle, the bias capacitor charging current Ivb is proportional to the amount of charging of the bias capacitor left to be done. This results in a bias capacitor charging rate in the form of a decreasing exponential, driving the voltage Vbias on the bias capacitor Cbias directly to 2Vref in the exemplary embodiment. Consequently, the bias voltage Vbias begins at a minimum rate, increases exponentially, and then decreases exponentially, until the circuit establishes the final mid-range bias voltage. Because of the relative smoothness of this form of the bias voltage Vbias versus time, harmonics of the basic wave shape are relatively low. The speaker sees a very minimal step (due to the minimum rate) , then a slow ramp up and then down. Since the step size depends on the minimal current, the current is made as small as possible, but must be large enough to overcome leakage .

Figures 7a and 7b are curves showing the voltage at node V2 and the bias capacitor discharge current Ivb versus bias voltage Vbias during the power-down sequence. This sequence is just the reverse of the sequence just described for power- up, again the minimum discharge current Ivb initiating the discharge of the bias capacitor Cbias . Thus, the invention described herein effectively controls the current available to charge the coupling capacitor Ccouple (Figure 4) so that the output voltage of the amplifier is shaped such that the signal appearing at the load (speaker, headphones, etc.) is inaudible. During the power-down cycle, when the amplifier output is actively pulled to ground, the coupling capacitor is effectively discharged in exactly the same way, but in an opposite sense as on power-up. These cycles may be designed to last much less than a second, yet still ensure that no audible transients are coupled to the load and that subsequent power- up likewise will be inaudible due to the fast coupling capacitor discharge in comparison to the slow bleed resistor discharge of prior art coupling capacitors hereinbefore described. During the power-up and power-down cycles, the amplifier gain may be substantially reduced, such as by way of example, by placing the amplifier in a unity gain feedback configuration as hereinbefore described, which effectively decouples the input signal from the amplifier input. (It should be noted that as used herein, the phrase "substantially reducing the gain of the amplifier" is used in the general sense to include reductions in the gain of the amplifier, typically by an order of magnitude or more, as well as by effectively disconnecting the input signal from the amplifier, such as by way of placing the amplifier in the unity gain feedback configuration.) While the current controlled regulator described herein provides a shaped voltage drive to an amplifier's non-inverting input by supplying triangular shaped charging/discharging currents to its bias capacitor, other circuits and other shaped charging/discharging currents may readily be used as desired. However preferably the alternative circuits will provide smoothly varying charging and discharging currents, and more preferably, smoothly varying charging and discharging currents starting near or at zero, smoothly increasing (though not necessarily linearly) and then smoothly decreasing to zero when the desired state of charge or discharge is achieved. Other techniques which could be used include having the charging current depend on time rather than voltage, However the generally triangular shaped waveform of the charging and discharging currents as disclosed herein allow the use of a time period for the waveform of less than a second, and in one embodiment approximately 500 milliseconds, yet has a frequency content which is well below the audio band and, thus, does not create an audible sound during the power-up and power-down cycles.

For such circuits to function during power-down, there must be an auxiliary source of power available for sufficient time to allow the coupling capacitor Ccouple to fully discharge. In some applications, a stand-by power source may be available for this purpose. In other applications, the circuit may switch to a low current state to allow the use of a Schottky diode/hold capacitor combination to provide a short term stand-by supply to power the circuit for the short time required to discharge the coupling capacitor, after which the amplifier may be shut off. In that regard, since the gain of the amplifier is substantially reduced, preferably by placing the amplifier in a unity gain feedback configuration during power-down, the power required by the amplifier (and the current controlled regulator) during power-down might be sufficiently low so as to be adequately sustained by a storage capacitor of reasonable size charged through a Schottky diode during the power-up period, depending on the class of the amplifier and the size of the load.

Thus while specific embodiments of the present invention have been disclosed and described in detail herein, it will be obvious to those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope thereof .

Claims

CLAIMSWhat is claimed:

1. A method of powering up an amplifier, the amplifier for receiving an input signal and being capacitively coupled to a load for providing an audible output responsive to the input signal, the amplifier having a normal operating gain and having a bias input to provide a predetermined nonzero average amplifier output, comprising: applying power to the amplifier while holding the operating gain of the amplifier to substantially below its normal operating gain; increasing the bias input to the amplifier to provide the predetermined nonzero average amplifier output, the bias input being increased in a manner so that the output of the load is substantially free of audible noise; and, increasing the operating gain of the amplifier to the normal operating gain.

2. The method of claim 1 wherein the operating gain of the amplifier is reduced to substantially below the normal operating gain by placing the amplifier in a unity gain feedback configuration.

3. The method of claim 1 wherein the bias input is increased to provide the predetermined nonzero average amplifier output by initially increasing the bias input approximately exponentially to a fraction of the predetermined nonzero average amplifier output, and then reducing the increasing bias input to exponentially approach the predetermined nonzero average amplifier output.

4. The method of claim 3 wherein the bias voltage is initially increased from zero at a predetermined minimum rate .

5. The method of claim 1 wherein the bias input is increased to provide the predetermined nonzero average amplifier output within approximately one second.

6. The method of claim 1 wherein the bias input is increased to provide the predetermined nonzero average amplifier output within approximately 500 milliseconds.

7. The method of claim 1 further including a method of powering down the amplifier comprising: reducing the operating gain of the amplifier to substantially below the normal operating gain; and, maintaining power to the amplifier while decreasing the bias input until the output of the amplifier is substantially zero, the bias input being decreased in a manner so that the output of the load is substantially free of audible noise.

8. The method of claim 7 wherein the operating gain of the amplifier is reduced to substantially below the normal operating gain by placing the amplifier in a unity gain feedback configuration.

9. The method of claim 7 wherein the bias input is decreased by initially decreasing the bias input approximately exponentially to a fraction of the predetermined nonzero average amplifier output, and then decreasing the bias input to exponentially approach zero.

10. The method of claim 9 wherein the bias voltage is initially decreased from the bias input to the amplifier to provide the predetermined nonzero average amplifier output at a predetermined minimum rate.

11. The method of claim 7 wherein the bias input is decreased to substantially zero within approximately one second.

12. The method of claim 7 wherein the bias input is decreased to substantially zero within approximately 500 milliseconds .

13. A method of powering down an amplifier., the amplifier for receiving an input signal and being capacitively coupled to a load for providing an audible output responsive to the input signal, the amplifier having a normal operating gain and having a bias input to provide a predetermined nonzero average amplifier output, comprising: reducing the operating gain of the amplifier to substantially below the normal operating gain; and, maintaining power to the amplifier while decreasing the bias input until the output of the amplifier is substantially zero, the bias input being decreased in a manner so that the output of the load is substantially free of audible noise.

14. The method of claim 13 wherein the operating gain of the amplifier is reduced to substantially below the normal operating gain by placing the amplifier in a unity gain feedback configuration.

15. The method of claim 13 wherein the bias input is decreased by initially decreasing the bias input approximately exponentially to a fraction of the predetermined nonzero average amplifier output, and then decreasing the bias input to exponentially approach zero.

16. The method of claim 15 wherein the bias voltage is initially decreased from the bias input to the amplifier to provide the predetermined nonzero average amplifier output at a predetermined minimum rate .

17. The method of claim 13 wherein the bias input is decreased to substantially zero within approximately one second.

18. The method of claim 13 wherein the bias input is decreased to substantially zero within approximately 500 milliseconds .

19. Apparatus for providing a bias voltage to an input of an output amplifier, the output amplifier having a normal operating gain and having a bias input to provide a predetermined nonzero average output, the output amplifier for receiving an input signal and having its output capacitively coupled to a load for providing an audible output responsive to a difference between the input signal and the bias voltage, comprising: a capacitor coupled to the bias input; a resistor coupled to the capacitor through which current to charge and discharge the capacitor will flow; a first feedback amplifier for amplifying the difference between a fraction of its output and the lower of a reference voltage and the voltage on the capacitor; a second feedback amplifier amplifying the difference between the output of the first feedback amplifier and the voltage on the capacitor; a first switch coupling the output of the first feedback amplifier to the resistor during power-up; a second switch coupling the output of the second feedback amplifier to the resistor during power-down; and, circuitry for substantially reducing the normal operating gain of the output amplifier during power-up and power-down.

20. The apparatus of claim 19 wherein the first feedback amplifier has a gain of approximately 2.

21. The apparatus of claim 20 wherein the second feedback amplifier has a gain of approximately 2.

22. The apparatus of claim 19 wherein the first and second feedback amplifiers each have a gain of approximately 2.

23. The apparatus of claim 19 wherein the circuitry for substantially reducing the normal operating gain of the output amplifier during power-up and power-down comprises muting circuitry.

24. The apparatus of claim 23 wherein the muting circuitry comprises circuitry putting the output amplifier in a unity gain feedback configuration.

25. The apparatus of claim 19 wherein the first and second switches are bilateral MOS switches.

26. The apparatus of claim 19 wherein the first feedback amplifier is capable of sourcing current and the second feedback amplifier is capable of sinking current, and further comprising a minimum current source and a minimum current sink, the minimum current source being coupled to provide a minimum current to the output of the first feedback amplifier when the first switch is closed, the minimum current sink being coupled to drain a minimum current from the output of the second feedback amplifier when the second switch is closed.

27. The apparatus of claim 19 wherein the ^'fraction is approximately 0.5.

28. Apparatus for providing a bias voltage to an input of an output amplifier, the output amplifier having a normal operating gain and having a bias input to provide a predetermined nonzero average output, the output amplifier receiving an input signal and having its output capacitively coupled to a load providing an audible output responsive to a difference between the input signal and the bias voltage, comprising: a capacitor coupled to the bias input; a resistor coupled to the capacitor through which current to charge the capacitor will flow; a feedback amplifier for amplifying the difference between a fraction of its output and the lower of a reference voltage and the voltage on the capacitor; and, circuitry for substantially reducing the normal operating gain of the output amplifier during power-up and power-down.

29. The apparatus of claim 28 wherein the feedback amplifier has a gain of approximately 2.

30. The apparatus of claim 28 wherein the circuitry for substantially reducing the normal operating gain of the output amplifier during power-up comprises muting circuitry.

31. The apparatus of claim 30 wherein the muting circuitry comprises circuitry putting the output amplifier in a unity gain feedback configuration.

32. The apparatus of claim 28 wherein the first feedback amplifier is capable of sourcing current, and further comprising a minimum current source coupled to provide a minimum current to the output of the feedback amplifier.

33. The apparatus of claim 28 wherein the fraction is approximately 0.5.