WO2002010915A1 - Procedes et dispositif d'emulation de logiciel - Google Patents

Procedes et dispositif d'emulation de logiciel Download PDF

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Publication number
WO2002010915A1
WO2002010915A1 PCT/US2001/019061 US0119061W WO0210915A1 WO 2002010915 A1 WO2002010915 A1 WO 2002010915A1 US 0119061 W US0119061 W US 0119061W WO 0210915 A1 WO0210915 A1 WO 0210915A1
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WO
WIPO (PCT)
Prior art keywords
code
operable
opcodes
modifying
opcode
Prior art date
Application number
PCT/US2001/019061
Other languages
English (en)
Inventor
Walter E. Earleson
Mary L. Kesse
Eric W. Ohlson
Original Assignee
Caterpillar Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Caterpillar Inc. filed Critical Caterpillar Inc.
Priority to AU2001268406A priority Critical patent/AU2001268406A1/en
Priority to DE10196446T priority patent/DE10196446T1/de
Publication of WO2002010915A1 publication Critical patent/WO2002010915A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code

Definitions

  • the present invention relates to emulation systems designed to run a particular instruction set designed for one type of processor on another type of processor that runs a different instruction set.
  • processors are designed to run a particular set of software instructions.
  • the instruction set for the processor usually defines the various types of operations that the processor can perform with data.
  • Emulation programs have been used to functionally implement the operation of the old instruction set with the new instruction set. Many techniques to do this rely on a lookup or jump table.
  • Figure 1 is a flow chart of one technique 10 using a jump table for emulating a first instruction set or code (“guest code” or “emulated code”) using a second instruction set or code (“native code” or “host code”) .
  • a processor (not shown) reads a first opcode of the guest code (usually a single line of code) .
  • the processor sets the pointer to a portion, e. g. , a routine, of the native code that performs a nearly identical function to the opcode of the guest code.
  • the processor "jumps" to the address indicated by the pointer, and in block 18 executes the native code at that address .
  • an opcode 11 may denote a "read” operation in the guest code.
  • the read operation may be performed by a routine located at address 101010.
  • the jump table would be used to calculate and output an address of 101010 whenever the guest opcode is 11 (block 14) .
  • the processor using native code, could then act on the 101010 address, by "jumping" (block 16) to a location that contains the routine that performs a similar function to the opcode of the guest code, and executing the read operation as it normally does (block 18) .
  • the jump table calculates a new pointer address as a function of the guest opcode that has been read. This often involves multiplying, e . g. , shifting left, and adding an offset value to the guest opcode. These operations take a relatively large amount of time.
  • a variety of software programs are extremely sensitive to the time at which various operations of the instruction sets are executed. For example an engine control system has precise requirements for when to command fuel delivery and ignition. If a processor running an -engine control system were to use an emulation program that employs the above and other techniques, the additional time needed to calculate the new pointer is often enough to affect the performance of the engine in an undesirable manner.
  • the present invention provides apparatuses and methods for emulating a first code having a plurality of opcodes.
  • a first code is modified into a second code, with each portion of the second code corresponding to an opcode of the first code and also corresponding to a respective address of a third code.
  • a respective portion of the second code corresponding to an opcode of the first code is read and at least a portion of a routine in the third code at the respective address is executed, the routine operable to perform a similar function to the respective opcode of the first code.
  • Figure 1 is a flow chart of one technique for emulating a first instruction set or code using a i second instruction set or code.
  • Figure 2 is a flow chart of one technique according to one embodiment of the invention for emulating a first instruction set or code using a second instruction set or code.
  • Figure 3 is a block diagram of an apparatus according to one embodiment of the invention.
  • FIG. 2 is a flow chart 50 of a technique according to one embodiment of the invention for emulating a first instruction set or code (“guest code”) using a different instruction set or code (“native code”) .
  • guest code a first instruction set or code
  • native code a different instruction set or code
  • the guest code is read, loaded, or otherwise accessed.
  • the guest code is modified, e . g. , converted, translated, realigned, reorganized, or rearranged, into a second or intermediate code.
  • Each opcode of the guest code is modified into a form that may be used by the processor to execute, in native code, e . g. , a third code, a routine that performs a similar function to the respective opcode of the guest code.
  • the guest code may be modified' into an address of the native code that contains the respective routine.
  • all of the first code is modified into the intermediate code, including the data and empty space portions of the first code.
  • the native code routine that performs the respective function of the guest code may be, and typically is, different from the guest code.
  • the routine may use new or different opcodes to perform the respective function, and may be the fewer, the same, or more numbers of lines/code than the respective opcode of the guest code.
  • predetermined digits supplement or are added to the guest code to create the intermediate code. For example if the guest code for a "read" operation is 1111, and the routine in the native code for a "read” operation is located at 11110000, four zeros would be tacked onto the guest code, creating an intermediate code of 11110000.
  • Such a similarity between the guest and native codes may not exist .
  • This also may allow the native code to closely track the order of the guest code. This reordering may be done by appropriate manipulation of the native code by ways known to those skilled in the art .
  • the intermediate code may not have any mathematical relationship at all to the guest code.
  • the intermediate code should however, be able to be used by the processor to run the respective routine in the native code. As mentioned above, this may include the intermediate code being used as an address or pointer to the respective routine in the native code.
  • Block 52 and 54 are typically performed prior to the "run-time" of the processor that executes the native code, such as during an initialization or power-up sequence.
  • "Run- time” may be considered to be the time when the processor is receiving inputs and transmitting outputs to/from external sources, i.e., its operational time, e . g. , blocks 56-60, discussed below.
  • the amount of time necessary to modify the guest code into the intermediate code does not affect the speed of the processor to execute code during normal operations.
  • the operations of blocks 52 and 54 may be performed on the entire guest code prior to "run-time” .
  • only portions of the guest code are modified prior to "run-time” .
  • the remaining portions may be modified at some other time, e .g. , during "run-time", such as during a time when the processor is otherwise relatively idle or when the modification does not affect the performance of the processor.
  • portions of the guest code may not be used, and therefore modification of those portions may not be needed.
  • the processor reads the intermediate code, e . g. , the first line.
  • the processor jumps to the routine in the native code corresponding to the intermediate code read in block 56.
  • the intermediate code is already in a form that corresponds to the address of a routine that performs a similar function to the respective opcode of the guest code.
  • a new pointer does not need to be calculated during the jump process, and the associated delay with that calculation is not present.
  • a pointer may still be used by ways known to those skilled in the art to "point" to the respective routines in the native code, but the pointer is set to the read intermediate code, and recalculation is not needed.
  • the intermediate code may be any of a variety of forms known to those skilled in the art that allows the processor to access the respective routine in native code that performs the same or similar function to the guest code read in block 52.
  • the intermediate code may be the actual address of the respective routine, or it may be an opcode of the native code that performs the same or similar function to the guest code read in block 52.
  • the first code typically includes data and/or empty space in addition to opcodes, and thus the intermediate code may also.
  • the processor executes the routine, in native code, that performs a similar function to the respective opcode of the guest code.
  • the processor then typically reads the next line of the intermediate code.
  • Software implementing the flowchart of Figure 1 may be created by ways known to those skilled in the art, and stored on/in a machine-readable medium.
  • the machine-readable medium may include magnetic tapes, floppy disks, hard drives, memory, such as ROM or RAM, CD-ROMs, or any of a variety of other storage mediums known to those skilled in the art .
  • FIG. 3 is a block diagram of an apparatus, such as a processor 80, according to one embodiment of the invention.
  • An application program 82 consists of a series of commands designed for the instruction set, e . g. , guest code 84, of the processor to be emulated (not shown) .
  • a modifying circuit 86 reads the guest code and modifies, e.g., translates or converts, the guest code into a modified code, e.g, the intermediate code 88.
  • the intermediate code 88 corresponds to an address in the native code, e . g. , a third code, that performs a similar function to the respective guest code instruction, e . g. , opcode.
  • the application program 82 typically causes single instructions 90 of the intermediate code 88 to be issued for execution by a processor 80 that uses native code.
  • a jump table 92 receives the instruction 90 and sets a pointer to a routine 94 in the native code 96 that performs a similar function to the instruction 90.
  • routine 94 corresponding to the instruction 90 is shown as being two instructions, the routine 94 could also be greater or fewer instructions.
  • the processor 80 or other execution circuit known to those skilled in the art then executes the routine 94, in native code, using any of a variety of appropriate execution circuits 98 known to those skilled in the art.
  • the processor 80 may also access data and empty space of the intermediate code 88 by ways known to those skilled in the art, and use the data during the execution of the native code 96.
  • circuit includes both hardware and software, with software being, in effect, a temporary circuit. Similarly, items depicted in software may be implemented in hardware, and vice versa.
  • the methods and apparatus of the present invention may be used to emulate, for example, the Motorola processor MC68CC11 ("HCll”) with a processor using the Motorola CPU 32 instruction set, such as the Motorola processor MC68HC336 ("HC336”) .
  • HCll Motorola processor MC68CC11
  • HC336 Motorola processor MC68HC336
  • electronic devices that have software written for the older HCll processor such as engine controllers, fuel injector controllers, or machine controllers, may be replaced with newer processors running HC336 software. This may extend the life of the devices using HC11- based control platform, as parts for the HCll processor become unavailable, making the HCll-based control platform unrepairable.
  • the methods and apparatuses of the present invention may also be equally applicable to other types of processors known to those skilled in the art, such as those used in video games, for example.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

L'invention concerne des dispositifs et procédés d'émulation d'un premier code (84) comprenant plusieurs codes d'opération, ces procédés consistant à modifier un premier code (84) en un second code (88), chaque portion de ce second code (88) correspondant à un code d'opération du premier code (84) et correspondant également à une adresse d'un troisième code (96), à lire une portion du second code (88) correspondant à un code opérationnel du premier code (84) et à exécuter au moins une portion d'une routine du troisième code (96) située au niveau d'une adresse respective, cette routine fonctionnant pour exécuter une fonction semblable audit code d'opération du premier code.
PCT/US2001/019061 2000-07-31 2001-06-14 Procedes et dispositif d'emulation de logiciel WO2002010915A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU2001268406A AU2001268406A1 (en) 2000-07-31 2001-06-14 Methods and apparatus for emulating software
DE10196446T DE10196446T1 (de) 2000-07-31 2001-06-14 Verfahren und Vorrichtung für Emulationssoftware

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US62870700A 2000-07-31 2000-07-31
US09/628,707 2000-07-31

Publications (1)

Publication Number Publication Date
WO2002010915A1 true WO2002010915A1 (fr) 2002-02-07

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AU (1) AU2001268406A1 (fr)
DE (1) DE10196446T1 (fr)
WO (1) WO2002010915A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4638423A (en) * 1985-03-06 1987-01-20 Motorola, Inc. Emulating computer
EP0927929A2 (fr) * 1998-01-05 1999-07-07 TRW Inc. Emulation vectorielle directe de jeu d'instructions d' héritage
US6039765A (en) * 1997-12-15 2000-03-21 Motorola, Inc. Computer instruction which generates multiple results of different data types to improve software emulation

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4638423A (en) * 1985-03-06 1987-01-20 Motorola, Inc. Emulating computer
US6039765A (en) * 1997-12-15 2000-03-21 Motorola, Inc. Computer instruction which generates multiple results of different data types to improve software emulation
EP0927929A2 (fr) * 1998-01-05 1999-07-07 TRW Inc. Emulation vectorielle directe de jeu d'instructions d' héritage

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ROGERS: "Emulation instruction", IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, vol. 25, no. 11A, April 1983 (1983-04-01), pages 5576 - 5577, XP002112146, ISSN: 0018-8689 *

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DE10196446T1 (de) 2003-08-28
AU2001268406A1 (en) 2002-02-13

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