WO2002008886A2 - Systeme, procede et article de fabrication permettant de commander l'utilisation des ressources - Google Patents

Systeme, procede et article de fabrication permettant de commander l'utilisation des ressources Download PDF

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Publication number
WO2002008886A2
WO2002008886A2 PCT/GB2001/003243 GB0103243W WO0208886A2 WO 2002008886 A2 WO2002008886 A2 WO 2002008886A2 GB 0103243 W GB0103243 W GB 0103243W WO 0208886 A2 WO0208886 A2 WO 0208886A2
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Prior art keywords
programmable gate
field programmable
gate arrays
ofthe
recited
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PCT/GB2001/003243
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English (en)
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WO2002008886A3 (fr
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Alex Wilson
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Celoxica Limited
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Priority to AU2001270874A priority Critical patent/AU2001270874A1/en
Publication of WO2002008886A2 publication Critical patent/WO2002008886A2/fr
Publication of WO2002008886A3 publication Critical patent/WO2002008886A3/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration

Definitions

  • the present invention relates to resource sharing and more particularly to a resource management device and process for allowing multiple field programmable gate arrays to concurrently access resources.
  • a software-controlled processor is usually slower than hardware dedicated to that function.
  • a way of overcoming this problem is to use a special software-controlled processor such as a RISC processor which can be made to function more quickly for limited purposes by having, its parameters (for instance size, instruction set etc.) tailored to the desired functionality.
  • a typical board has two FPGAs.
  • the board can be designed in such a way that both FPGAs are connected to each physical device on the board. Thus each is individually able to drive all of the devices on the board.
  • two main problems arise when trying to access a resource from both FPGAs:
  • the first is related to external memory and arises because the prior art programming languages, such as HandelC, that are designed to enable the compilation of programs into synchronous hardware are not able to tristate the control and address lines to external RAMs.
  • HandelC programming languages
  • each RAM bank (and the FLASH memory - which shares address pins with one of the RAM banks) can only be accessed from one FPGA.
  • a system, method and article of manufacture are provided for managing the resources of a system.
  • the resources comprise any resource that is shared between multiple logic devices such as shared memory banks and shared Input/Output or other peripherals such as audio hardware.
  • a communications driver is utilized to allow at least two field programmable gate arrays to send messages to each other.
  • Each message between the field programmable gate arrays (FPGAs) includes an identification code, where a first portion of the identification code identifies a type of the message, and where a second portion of the identification code identifies a request for a resource.
  • the identification code is processed.
  • a macro procedure is called based on the type of message and the identification of the request for the resource. The macro procedure receives and processes the message.
  • the field programmable gate arrays are allowed to access external memory. Also preferably, arbitration is provided for preventing conflicts between the field programmable gate arrays when the field programmable gate arrays access the same resource.
  • shared resources can be locked from other processes while communications are in progress. This can include communications between the FPGAs and/or communication between an FPGA and the resource.
  • an application on one of the field programmable gate arrays is allowed to send a command to another of the filed programmable gate arrays.
  • one or more of the field programmable gate arrays is reconfigured so that it can access the resource.
  • the invention extends to a computer program comprising program code means for executing the method.
  • Figure 1 is a schematic diagram of a hardware implementation of one embodiment of the present invention.
  • Figure 2 is a flow chart of a process for managing the resources of a system according to one embodiment of the present invention
  • Figure 3 is a diagrammatic overview of a board of the resource management device according to an illustrative embodiment of the present invention
  • Figure 4 depicts a JTAG chain for the board of Figure 3;
  • Figure 5 shows a structure of a Parallel Port Data Transmission System according to an embodiment of the present invention
  • FIG. 6 is a flowchart that shows the typical series of procedure calls when receiving data
  • Figure 7 is a flow diagram depicting the typical series of procedure calls when transmitting data
  • Figure 8 is a flow diagram illustrating several processes running in parallel.
  • FIG. 9 is a block diagram of an FPGA device according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • a preferred embodiment of a system in accordance with the present invention is preferably practiced in the context of a personal computer such as an IBM compatible personal computer, Apple Macintosh computer or UNIX based workstation.
  • a representative hardware environment is depicted in Figure 1, which illustrates a typical hardware configuration of a workstation in accordance with a preferred embodiment having a central processing unit 110, such as a microprocessor, and a number of other units interconnected via a -system bus 112.
  • the workstation shown in Figure.1 includes a Random Access Memory (RAM) 114, Read Only Memory (ROM) 116, an I/O adapter 118 for connecting peripheral devices such as disk storage units 120 to the bus 112, a user interface adapter 122 for connecting a keyboard 124, a mouse 126, a speaker 128, a microphone 132, and/or other user interface devices such as a touch screen (not shown) to the bus 112, communication adapter 134 for connecting the workstation to a commumcation network (e.g., a data processing network) and a display adapter 136 for connecting the bus 112 to a display device 138.
  • a commumcation network e.g., a data processing network
  • display adapter 136 for connecting the bus 112 to a display device 138.
  • the workstation typically has resident thereon an operating system such as the Microsoft Windows NT or Windows/95 Operating System (OS), the IBM OS/2 operating system, the MAC OS, or UNIX operating system.
  • OS Microsoft Windows NT or Windows/95 Operating System
  • IBM OS/2 operating system the IBM OS/2 operating system
  • MAC OS the MAC OS
  • UNIX operating system the operating system
  • OOP Object oriented programming
  • OOP is a process of developing computer software using objects, including the steps of analyzing the problem, designing the system, and constructing the program.
  • An object is a software package that contains both data and a collection of related structures and procedures.
  • OOP Since it contains both data and a collection of structures and procedures, it can be visualized as a self-sufficient component that does not require other additional structures, procedures or data to perform its specific task. OOP, therefore, views a computer program as a collection of largely autonomous components, called objects, each of which is responsible for a specific task. This concept of packaging data, structures, and procedures together in one component or module is called encapsulation.
  • OOP components are reusable software modules which present an interface that conforms to an object model and which are accessed at run-time through a component integration architecture.
  • a component integration architecture is a set of architecture mechanisms which allow software modules in different process spaces to utilize each others capabilities or functions. This is generally done by assuming a common component object model on which to build the architecture. It is worthwhile to differentiate between an object and a class of objects at this point.
  • An object is a single instance of the class of objects, which is often just called a class.
  • a class of objects can be viewed as a blueprint, from which many objects can be formed.
  • OOP allows the programmer to create an object that is a part of another object.
  • the object representing a piston engine is said to have a composition- relationship with the object representing a piston.
  • a piston engine comprises a piston, valves and many other components; the fact that a piston is an element of a piston engine can be logically and semantically represented in OOP by two objects.
  • OOP also allows creation of an object that "depends from" another object. If there are two objects, one representing a piston engine and the other representing a piston engine wherein the piston is made of ceramic, then the relationship between the two objects is not that of composition. A ceramic piston engine does not make up a piston engine.
  • the object representing the ceramic piston engine is called a derived object, and it inherits all of the aspects of the object representing the piston engine and adds further limitation or detail to it.
  • the object representing the ceramic piston engine "depends from” the object representing the piston engine. The relationship between these objects is called inheritance.
  • the object or class representing the ceramic piston engine inherits all of the aspects of the objects representing the piston engine, it inherits the thermal characteristics of a standard piston defined in the piston engine class.
  • the ceramic piston engine object overrides these ceramic specific thermal characteristics, which are typically different from those associated with a metal piston. It skips over the original and uses new functions related to ceramic pistons.
  • Different kinds of piston engines have different characteristics, but may have the same underlying functions associated with it (e.g., how many pistons in the engine, ignition sequences, lubrication, etc.).
  • a programmer would call the same functions with the same names, but each type of piston engine may have different/overriding implementations of functions behind the same name. This ability to hide different implementations of a function behind the same name is called polymorphism and it greatly simplifies communication among objects.
  • composition-relationship With the concepts of composition-relationship, encapsulation, inheritance and polymorphism, an object can represent just about anything in the real world. In fact, one's logical perception of the reality is the only limit on determining the kinds of things that can become objects in object-oriented software. Some typical categories are as follows:
  • Objects can represent physical objects, such as automobiles in a traffic-flow simulation, electrical components in a circuit-design program, countries in an economics model, or aircraft in an air-traffic-control system.
  • Objects can represent elements of the computer-user environment such as windows, menus or graphics objects.
  • An object can represent an inventory, such as a personnel file or a table of the latitudes and longitudes of cities.
  • An object can represent user-defined data types such as time, angles, and complex numbers, or points on the plane.
  • OOP allows the software developer to design and implement a computer program that is a model of some aspects of reality, whether that reality is a physical entity, a process, a system, or a composition of matter. Since the object can represent anything, the software developer can create an object which can be used as a component in a larger software project in the future.
  • OOP enables software developers to build objects out of other, previously built objects.
  • C++ appears to be the most popular choice among many OOP programmers, but there is a host of other OOP languages, such as Smalltalk, Common Lisp Object System (CLOS), and Eiffel. Additionally, OOP capabilities are being added to more traditional popular computer programming languages such as Pascal.
  • Encapsulation enforces data abstraction through the organization of data into small, independent objects that can communicate with each other. Encapsulation protects the data in an object from accidental damage, but allows other objects to interact with that data by calling the object's member functions and structures.
  • Subclassing and inheritance make it possible to extend and modify objects through deriving new kinds of objects from the standard classes available in the system. Thus, new capabilities are created without having to start from scratch.
  • Polymorphism and multiple inheritance make it possible for different programmers to mix and match characteristics of many different classes and create specialized objects that can still work with related objects in predictable ways.
  • Class libraries are very flexible. As programs grow more complex, more programmers are forced to adopt basic solutions to basic problems over and over again.
  • a relatively new extension of the class library concept is to have a framework of class libraries. This framework is more complex and consists of significant collections of collaborating classes that capture both the small scale patterns and major mechanisms that implement the common requirements and design in a specific application domain. They were first developed to free application programmers from the chores involved in displaying menus, windows, dialog boxes, and other standard user interface elements for personal computers.
  • Frameworks also represent a change in the way programmers think about the interaction between the code they write and code written by others.
  • the programmer called libraries provided by the operating system to perform certain tasks, but basically the program executed down the page from start to finish, and the programmer was solely responsible for the flow of control. This was appropriate for printing out paychecks, calculating a mathematical table, or solving other problems with a program that executed in just one way.
  • a programmer writing a framework program not only relinquishes control to the user, (as is also true for event loop programs), but also relinquishes the detailed flow of control within the program to the framework. This approach allows the creation of more complex systems that work together in interesting ways, as opposed to isolated programs, having custom code, being created over and over again for similar problems.
  • a framework basically is a collection of cooperating classes that make up a reusable design solution for a given problem domain. It typically includes objects that provide default behavior (e.g., for menus.and windows), and programmers use it by inheriting some of that default behavior and overriding other behavior so that the framework calls application code at the appropriate times.
  • default behavior e.g., for menus.and windows
  • Class libraries are essentially collections of behaviors that you can call when you want those individual behaviors in your program.
  • a framework provides not only behavior but also the protocol or set of rules that govern the ways in which behaviors can be combined, including rules for what a programmer is supposed to provide versus what the framework provides.
  • • Call versus override With a class library, the code the programmer instantiates objects and calls their member functions. It's possible to instantiate and call objects in the same way with a framework (i.e., to treat the framework as a class library), but to take full advantage of a framework's reusable design, a programmer typically writes code that overrides and is called by the framework.
  • the framework manages the flow of control among its objects. Writing a program involves dividing responsibilities among the various pieces of software that are called by the framework rather than specifying how the different pieces should work together. • Implementation versus design. With class libraries, programmers reuse only implementations, whereas with frameworks, they- reuse design.
  • a framework embodies the way a family of related programs or pieces of software work. It represents a generic design solution that can be adapted to a variety of specific problems in a given domain. For example, a single framework can embody the way a user interface works, even though two different user interfaces created with the same framework might solve quite different interface problems .
  • a preferred embodiment of the invention utilizes HyperText Markup Language (HTML) to implement documents on the Internet together with a general-purpose secure communication protocol for a transport medium between the client and the Newco. HTTP or other protocols could be readily substituted for HTML without undue experimentation.
  • HTML HyperText Markup Language
  • RRC 1866 Hypertext Markup Language - 2.0
  • HTML Hypertext Transfer Protocol ⁇ HTTP/1.1 : HTTP Working Group Internet Draft
  • HTML documents are SGML documents with generic semantics that are appropriate for representing information from a wide range of domains. HTML has been in use by the World-Wide Web global information initiative since 1990. HTML is an application of ISO Standard 8879; 1986 Information Processing Text and Office Systems; Standard Generalized Markup Language (SGML).
  • HTML has been the dominant technology used in development of Web-based splutions.
  • HTML has proven to be inadequate in the following areas:
  • Custom "widgets” e.g., real-time stock tickers, animated icons, etc.
  • client-side performance is improved.
  • Java supports the notion of client-side validation, offloading appropriate processing onto the client for improved performance.
  • Dynamic, real-time Web pages can be created. Using the above- mentioned custom UI components, dynamic Web pages can also be created.
  • Sun's Java language has emerged as an industry-recognized language for "programming the Internet.”
  • Sun defines Java as: "a simple, object-oriented, distributed, interpreted, robust, secure, architecture-neutral, portable, high- performance, multithreaded, dynamic, buzzword-compliant, general-purpose programming language.
  • Java supports programming for the Internet in the form of platform-independent Java applets.”
  • Java applets are small, specialized applications that comply with Sun's Java Application Programming Interface (API) allowing developers to add "interactive content" to Web documents (e.g., simple animations, page adornments, basic games, etc.). Applets execute within a Java-compatible browser (e.g., Netscape Navigator) by copying code from the server to client.
  • Java's core feature set is based on C++.
  • Sun's Java literature states that Java is basically, "C++ with extensions from Objective C for more dynamic method resolution.”
  • ActiveX includes tools for developing animation, 3-D virtual reality, video and other multimedia content.
  • the tools use Internet standards, work on multiple platforms, and are being supported by over 100 companies.
  • the group's building blocks are called ActiveX Controls, small, fast components that enable developers to embed parts of software in hypertext markup language (HTML) pages.
  • ActiveX Controls work with a variety of programming languages including Microsoft Visual C++, Borland Delphi, Microsoft Visual Basic programming system and, in the future, Microsoft's development tool for Java, code named "Jakarta.” ActiveX
  • Handel-C is a programming language. It enables a software or hardware engineer to target directly FPGAs (Field Programmable Gate Array) in a similar fashion to classical microprocessor cross-compiler development tools, without recourse to a Hardware Description Language. Thereby allowing the designer to directly realise the raw real-time computing capability of the FPGA.
  • Handel-C is a programming language designed to enable the compilation of programs into synchronous hardware; it is aimed at compiling high level algorithms directly into gate level hardware.
  • Handel-C syntax is based on that of conventional C so programmers familiar with conventional C will recognize almost all the constructs in the Handel-C language.
  • Handel-C includes parallel constructs that provide the means for the programmer to exploit this benefit in his applications.
  • the compiler compiles and optimizes Handel-C source code into a file suitable for simulation or a netlist which can be placed and routed on a real FPGA.
  • the simulator allows you to test your program without using real hardware. It can display the state of every variable (register) in your program at every clock cycle if required, the simulation steps and the number of cycles simulated being under program control. Optionally the source code that was executed at each clock cycle as well as the program state may be displayed in order to assist in the debugging of the source code.
  • An embodiment of the present invention provides a resource-sharing server for allowing multiple Field Programmable Gate Arrays (FPGAs) on a computer board to access all the available hardware concurrently.
  • FPGAs Field Programmable Gate Arrays
  • the board As one of the key features of the board according to an embodiment of the present invention is its ability to reconfigure itself both from Flash and over the Ethernet, it becomes apparent that there is a natural division of the roles of two FPGAs.
  • One (the server, or FPO) should have access- to the Flash and the Network and include the reconfiguration device driver.
  • the other (the client application or FP1) then has control over the LCD, touchscreen and the audio chip.
  • FIG. 2 is a flow chart of a process 200 for managing the resources of a system according to one embodiment of the present invention.
  • the resources comprise any resource that is shared between multiple logic devices such as shared memory banks and shared Input/Output or other peripherals such as audio hardware.
  • a communications driver is utilized to allow at least two FPGAs to send messages to each other.
  • an identification code is included with each message between the FPGAs, where a first portion of the identification code identifies a type of the message and a second portion of the identification code identifies a request for a resource.
  • the identification code is processed in operation 206.
  • a macro procedure is called in operation 208 and is based on the type of message and the identification of the request for the resource. The macro procedure receives and processes the message.
  • a server includes a bidirectional 16 bit communications driver for allowing the two FPGAs to talk to each other. Every message from one FPGA to the other is preceded by a 16 bit ID, the high eight bits of which identify the type of message (AUDIO, FLASH, • • RECONFIGURATION etc%) and the low identify the particular request for that hardware (FLASH_READ etc).
  • the id codes are processed in the header file fpOserver.h, and then an appropriate macro procedure is called for each type of message (e.g. for AUDIO AudioRequest is called) which then receives and processes the main body of the. communication.
  • the FPGAs are allowed to access external memory. Also preferably, arbitration is provided for preventing conflicts between the FPGAs when the FPGAs access the same resource. Further, the need to stop and reinitialize drivers and hardware when passing from one FPGA to the other is removed.
  • shared resources can be locked from other processes while communications are in progress. This can include communications between the FPGAs and or communication between an FPGA and the resource.
  • an application on one of the FPGAs is allowed to send a command to another of the FPGAs.
  • one or more of the FPGAs is reconfigured so that it can access the resource.
  • the server process requires a number of parameters to be passed to it. These are:
  • PID Used for locking shared resources (such as the FLASH) from other processes while communications are in progress.
  • uSoundOut Two channels mirroring the function of the audio driver. Data sent to uSoundOut will be played (assuming the correct code in FP1) out of the MMT2000 speakers, and data read from uSoundln is the input to the MMT2000 microphone.
  • the channels are implemented in such a way that when the sound driver blocks, the communication channel between FPGAs is not held ' up.
  • MP3Run A one bit variable controlling the MP3 GUI.
  • the server will activate or deactivate the MP3 GUI on receipt of commands from FPl.
  • the data transfer rate between the two FPGAs in either direction is preferably about 16 bits per 5 clock cycles (in the clock domain of the slowest FPGA), for communicating between FPGAs that may be running at different clock rates.
  • Handel-C macros which may be used in various implementations of the present invention are set forth in Table 1. It should be noted that other programming and hardware description languages can be utilized as well, such as VHDL.
  • Audiorequesth Audio Server AudioRequestQ Audio server for allowing sharing of sound hardware
  • Flashrequesth Data server FlashRequestO Server for allowing FPl access to the FLASH memory
  • MP3 server MP3Request0 Server to control the MP3 application and feed it MP3 bitstream data when requested.
  • Reconfigurerequesth Reconfiguration Reconfigurereq Allows FPl to request to be hardware uestO reconfigured, at an application exit.
  • Fpgacomms.h Communications FpgacommsQ Implements two unidirectional hardware 16 bit channels for communicating between the two FPGAs
  • FIG. 3 is a diagrammatic overview of a board 300 of the resource management device according to an illustrative embodiment of the present invention. It should be noted that the following description is set forth as an illustrative embodiment of the ' present invention and, therefore, the various embodiments of the present invention should not be limited by this description.
  • the board can include two Xilinx VirtexTM 2000e FPGAs 302, 304, an Intel StrongARM SAl 110 processor 306, a large amount of memory 308, 310 and a number of I/O ports 312. Its main features are listed below:
  • Two XCV 2000e FPGAs each with sole access to the following devices: Two banks (1 MB each) of SRAM (256Kx32 bits wide) Parallel port Serial port ATA port
  • the FPGAs share the following devices: VGA monitor port Eight LEDs
  • the FPGAs are connected to each other through a General Purpose I/O (GPIO) bus, a 32 bit SelectLink bus and a 32 bit Expansion bus with connectors that allow external devices to be connected to the FPGAs.
  • GPIO General Purpose I/O
  • SelectLink 32 bit SelectLink bus
  • Expansion bus with connectors that allow external devices to be connected to the FPGAs.
  • the FPGAs are mapped to the memory of the StrongARM processor, as variable latency I/O devices.
  • the Intel StrongARM SAl 110 processor has access to the following: 64Mbytes of SDRAM 16Mbytes of FLASH memory LCD port IRDA port
  • Serial port It shares the USB port and the shared SRAM with the FPGAs.
  • the board also has a Xilinx XC95288XL CPLD to implement a number of glue logic functions and to act as a shared RAM arbiter, variable rate clock generators and JTAG and MultiLinx SelectMAP support for FPGA configuration.
  • the FPGAs are mapped into the ARM's memory allowing them to be accessed from the ARM as through they were RAM devices.
  • the FPGAs also share two 1 MB banks of SRAM with the processor, allowing DMA transfers to be performed.
  • GPIO general purpose I/O
  • the board is fitted with 4 clocks, 2 fixed frequency and 2 PLLs.
  • the PLLs are programmable by the ARM processor.
  • the ARM is configured to boot into Angel, the ARM onboard debugging monitor, on power up and this can be connected to the ARM debugger on the host PC via a - serial link. This allows applications to be easily developed on the host and run on the board.
  • the board is fitted with an Intel SAl 110 Strong ARM processor. This has 64Mbytes of SDRAM connected to it locally and 16Mbytes of Intel StrataFL ASHTM from which the processor may boot.
  • the processor has direct connections to the FPGAs, which are mapped to its memory map as SRAM like variable latency I/O devices, and access to various I/O devices including USB, IRDA, and LCD screen connector and serial port. It also has access to 2MB of SRAM shared between the processor and the FPGAs.
  • the Flash RAM is very slow compared to the SRAM or SDRAM. It should only be used for booting from; it is recommended that code be copied from Flash RAM to SDRAM for execution. If the StrongARM is used to update the Flash RAM contents then the code must not be. nning from the Flash or the programming instructions in the Flash will get corrupted.
  • a standard 64MB SDRAM SODIMM is fitted to the board and this provides the bulk of the memory for the StrongARM. Depending upon the module fitted the SDRAM may not appear contiguous in memory.
  • RAM banks are shared with both FPGAs. This resource is arbitrated by the CPLD and may only be accessed once the CPLD has granted the ARM permission to do so. Requesting and receiving permission to access the RAMs is carried out through CPLD register 0x10. Refer to the CPLD section of this document for more information about accessing the CPLD and its internal registers from the ARM processor. See Appendix D.
  • the FPGAs are mapped to the ARM's memory and the StrongARM can access the FPGAs directly using the specified locations. These locations support variable length accesses so the FPGA is able to prevent the ARM from completing the access until the FPGA is ready to receive or transmit the data. To the StrongARM these will appear as static memory devices, with the FPGAs having access to the Data, Address and Chip Control signals of the RAMs.
  • the FPGAs are also connected to the GPIO block of the processor via the SAIO bus.
  • the GPIO pins map to the SAIO bus is shown in Table 4.
  • SAIO[0:10] connect to the FPGAs and SAIO[0:14] connect to connector CN25 on the board.
  • the FPGAs and ARM are also able to access 2MB of shared memory, allowing DMA transfers between the devices to be performed.
  • serial port is wired in such away that two ports are available with a special lead if handshaking isn't required.
  • Angel is the onboard debug monitor for the ARM processor. It communicates with the host PC over the serial port (a null modem serial cable will be required). The ARM is setup to automatically boot into Angel on startup - the startup code in the ARM's Flash RAM will need to be changed if this is not required.
  • Two Virtex 2000e FPGAs are fitted to the board. They may be programmed from a variety of sources, including at power up from the FLASH memory. Although both devices feature the same components they have different pin definitions; Handel-C header files for the two FPGAs are provided.
  • One of the devices has been assigned 'Master', the other 'Slave'. This is basically a means of identifying the FPGAs, with the Master having priority over the Slave when requests for the shared memory are processed by the CPLD.
  • the FPGA below the serial number is the Master.
  • One pin on each of the FPGAs is defined as the Master/Slave define pin. This pin is pulled to GND on the Master FPGA and held high on the Slave.
  • the pins are:
  • CLKA is fitted with a 50 MHz oscillator on dispatch and the CLKB socket is left to be fitted by the user should other or multiple frequencies to required.
  • a +5V oscillator module should be used for CLKB.
  • VCLK and MCLK Two on board PLLs, VCLK and MCLK, provide clock sources between 8MHz and 1 OOMHz (125MHz may well be possible). These are programmable by the ARM processor. VCLK may also be single stepped by the ARM.
  • This multitude of clock sources allows the FPGAs to be clocked at different rates, or to let one FPGA have multiple clock domains.
  • the clocks are connected to the FPGAs, as described in Table 9 and Appendices A and B:
  • the FPGAs may be programmed from a variety of sources: • Parallel III cable JTAG
  • the JTAG chain 400 for the board is shown in Figure 4.
  • MultiLinx JTAG The board has support for programming using MultiLinx.
  • CN3 is the only connector required for JTAG programming , with MultiLinx and is wired up as described in Table 11. (Note that not used signals may be connected up to the MultiLinx if required.)
  • JP3 must be fitted when using MulitLinx SelectMap to configure the FPGAs. This link prevents the CPLD from accessing the FPGA databus to prevent bus contention. This also prevents the ARM accessing the FPGA Flash memory and from attempting FPGA programming from power up. Connectors CN3 and CN4 should be used for Master FPGA programming and CN10 and CNl 1 for programming the Slave FPGA.. See Tables 12-13.
  • MultiLinx SelectMap was found to be a very tiresome method of programming the FPGAs due to the large number of flying leads involved and the fact that the lack of support for multi FPGA systems means that the leads have to connected to a different connector for configuring each of the FPGA.
  • the ARM is able to program each FPGA via the CPLD.
  • the FPGAs are set up to be configured in SelectMap mode. Please refer to the CPLD section of this document and Xilinx Datasheets on Virtex configuration for more details of how to access the programming pins of the FPGAs and the actual configuration process respectively.
  • Angel is supplied. This is a very slow process however as the file is transferred over a serial link. Data could also be acquired from a variety of other sources including
  • USB and IRDA or the onboard Flash RAMs should allow an FPGA to be configured in under 0.5 seconds.
  • One FPGA is able to configure the other through the CPLD in a manner similar to when the ARM is configuring the FPGAs.
  • the CPLD section of this document and the Xilinx data sheets for more information.
  • the board can be set to boot the FPGAs using configuration data stored in this memory on power up.
  • the following jumpers should be set if the board is required to boot from the Flash RAM:
  • the configuration data must be the configuration bit stream only, not the entire .bit file.
  • the .bit file contains header information which must first be stripped out and the bytes of the configuration stream as stored in the .bit file need to be mirrored - i.e. a configuration byte stored as 00110001 in the bit file needs to be applied to the FPGA configuration data pins are 10001100.
  • Flash memory 16 MB of Intel StrataFLASH TM Flash memory is available to the FPGAs. This is shared between the two FPGAs and the CLPD and is connected directly to them.
  • the Flash RAM is much slower than the SRAMs on the board, having a read cycle time of 120ns and a write cycle of around 80ns.
  • the FPGAs are able to read and write to the memory directly, while the ARM processor has access to it via the CPLD.
  • Macros for reading and writing simple commands to the Flash RAM's internal state machine are provided in the klib.h macro library (such as retrieving identification and status information for the RAM), but it is left up to the developer to enhance these to implement the more complex procedures such as block programming and locking.
  • the macros provided are intended to illustrate the basic mechanism for accessing the Flash RAM.
  • Each FPGA has two banks of local SRAM, arranged as 256K words x 32bits. They have an access time of 15ns.
  • Each FPGA has access two banks of shared SRAM, again arranged as 256K words x 32bits. These have a 16ns access time.
  • a series of quick switches are used to switch these RAMs between the FPGAs and these are controlled by the CPLD which acts as an arbiter.
  • the REQUEST pin To request access to a particular SRAM bank the REQUEST pin should be pulled low. The code should then wait until the GRANT signal is pulled low by the CPLD in response.
  • the RAMs should be defined in the same manner as the local RAMs. (See above.)
  • the FPGAs are mapped to the StrongARMs memory as variable latency I/O devices, and are treated as by the ARM as though they were 1024 entry by 32bit RAM devices.
  • the address, data and control signals associated with these RAMs are attached directly to the FPGAs. The manner in which the FPGAs interact with the ARM using these signals is left to the developer.
  • Some of the ARM's general purpose I/O pins are also connected to the FPGAs. These go through connector CN25 on the board, allowing external devices to be connected to them (see also ARM section). See Table 19.
  • Table 20 Listed in Table 20 are the pins used for setting the Flash Bus Master signal and FP_COMs. Refer to the CPLD section for greater detail on this.
  • FPGA I/O pins directly connect to the ATA port. These pins have 100 ⁇ series termination resistors which make the port- 5V IO tolerant. These pins may also be used as I/O if the ATA port isn't required. See Table 21.
  • a conventional 25pin D-type connector and a 26way box header are provided to access this port.
  • the I/O pins have 100 ⁇ series termination resistors which also make the port 5 V I/O tolerant. These pins may also be used as I/O if the parallel port isn't required. See Table 22. See also Appendix C.
  • a standard 9pin D-type connector with a RS232 level shifter is provided. This port may be directly connected to a PC with a Null Modem cable. A box header with 5 V tolerant I/O is also provided. These signals must NOT be connected to a standard RS232 interface without an external level shifter as the FPGAs may be damaged. See Table 23.
  • Each FPGA also connects to a 10 pin header (CN9/CN16).
  • the connections are shown in Table 24:
  • a standard 15pin High Density connector with an on-board 4bit DAC for each colour (Red, Green, Blue) is provided. This is connected to the FPGAs as set forth in Table 25:
  • a 50way Box header with 5V tolerant I/O is provided. 32 data bits ( ⁇ ' bus) are available and two clock signals.
  • the connector may be used to implement a SelectLink to another FPGA. +3 V3 and +5V power supplies are provided via fuses. See Table 27. Table 27
  • the FPGAs have shared access to the USB chip on the board. As in the case ofthe Flash RAM, the FPGA needs to notify the CPLD that it has taken control ofthe USB chip by setting the USBMaster pin low before accessing the chip. For more information on the USB chip refer to the USB section of this document.
  • the board is fitted with a Xilinx XC95288XL CPLD which provides a number of Glue Logic functions for shared RAM arbitration, interfacing between the ARM and FPGA and configuration ofthe FPGAs.
  • the later can be used to either configure the FPGAs from power up or when one FPGA re-configures the other (Refer to section 'Programming the FPGAs').
  • a full listing of ABEL code contained in the CPLD can be found in Appendix D.
  • the CPLD implements a controller to manage the shared RAM banks.
  • a Request - Grant system has been implemented to allow each SRAM bank to be accessed by one ofthe three devices.
  • a priority system is employed if more than one device requests the SRAM bank at the same time.
  • the FPGAs request access to the shared SRAM by pulling the corresponding REQUEST signals low and waiting for the CPLD to pull the GRANT signals low in response. Control is relinquished by setting the REQUEST signal high again.
  • the ARM processor is able to request access to the shared SRAM banks via some registers within the CPLD - refer to the next section.
  • the ARM can access a number of registers in the CPLD, as shown in Table 30:
  • 0x00 This is an address indirection register for register 1 which used for the data access.
  • the FPGAs can access the CPLD by setting a command on the FPCOM pins. Data is transferred on the FPGA (Flash RAM) databus. See Table 31.
  • the board has a SCAN Logic SL11H USB interface chip, capable of full speed 12Mbits/s transmission.
  • the chip is directly connected to the FPGAs and can be accessed by the ARM processor via the CLPD (refer to the CPLD section of this document for further information).
  • This board maybe powered from an external 12V DC power supply through the
  • the supply should be capable of providing at least 2.4A.
  • the klib.h library provides a number of macro procedures to allow easier access to the various devices on the board, including the shared memory, the Flash RAM, the CPLD and the LEDs.
  • Two other libraries are also presented, parallel_port.h and serial_port.h, which are generic Handel-C libraries for accessing the parallel and serial ports and communicating over these with external devices such as a host PC.
  • a request - grant mechanism is implemented to arbitrate the shared RAM between the two FPGAs and the ARM processor.
  • Four macros are provided to make the process of requesting and releasing the individual RAM banks easier.
  • KRequestMemoryBankl () ; KReleaseMemoryBankOQ; KReleaseMemoryBanklQ;
  • KRequestMemoryBank#() requires at least one clock cycle.
  • KReleaseMemoryBank#() takes one clock cycle.
  • the request and release functions for different banks may be called in 15 parallel with each other to gain access to or release both banks in the same cycle.
  • These macros are provided as a basis through which interfacing to the Flash RAM can be carried out.
  • the macros retrieve model and status information from the RAM to illustrate how the read/write cycle should work. Writing actual data to the Flash RAM is more complex and the implementation of this is left to the developer.
  • KSetFPGAFBM() sets the Flash Bus Master (FBM) signal and KReleaseFPGAFBM() releases it.
  • This macro is generally called by higher level macros such as KReadFlash() or KWriteFlash().
  • KReadFlashO returns the value ofthe location specified by address in the data parameter.
  • the procedures are limited by the timing characteristics ofthe Flash RAM device.
  • a read cycle takes at least 120ns, a write cycle 100ns.
  • the procedures have been set up for a Handel-C clock of 25MHz.
  • the macros read data from and write data to the address location specified in the address parameter. -01-
  • This macro requires one clock cycle.
  • the macro sets the Flash address bus to the value passed in the address parameter. This macro is used when a return value ofthe data at the specified location is not required, as may be the case when one FPGA is configuring the other with data from the Flash RAM since the configuration pins ofthe FPGAs are connected directly to the lower 8 data lines ofthe Flash RAM.
  • the macros return the requested values in the parameters passed to it.
  • KReadFlashStatusQ requires 10 cycles
  • KReadFlashID() requires 14 cycles.
  • the macros retrieve component and status information from the Flash RAM. This is done by performing a series of writes and reads to the internal Flash RAM state machine.
  • these macros are limited by the access time ofthe Flash RAM and the number of cycles required depends on rate the design is clocked at. These macros are designed to be used with a Handel-C clock rate of 25MHz or less.
  • KReadStatusQ returns an 8 bit word containing the bits ofthe CPLD's status register. (Refer to the CPLD section for more information)
  • These macros read the status register and write to the control register ofthe CPLD.
  • This macro requires three clock cycles, at a Handel-C clock rate of 25MHz or less.
  • This macro is provided to make the sending of FP_COMMANDs to the CPLD easier.
  • FP_COMMANDs are used when the reconfiguration of one FPGA from the other is desired (refer to the CPLD section for more information).
  • FP_SET_IDLE Sets CPLD to idle FP_READ_STATUS Read the status register ofthe CPLD FP_WRITE_CONTROL Write to the control register ofthe CPLD FP_CCLK_LOW Set the configuration clock low FP CCLK HIGH Set the configuration clock high
  • KSetFPCOM (FP_READ_STATUS); KSetFPCOM(FP_SET_IDLE);
  • the maskByte parameter is applied to the LEDs on the board, with a 1 indicating to turn a light on and a 0 to turn it off.
  • the MSB of maskByte corresponds to D12 and the LSB to D5 on the board.
  • the library parallel_port.h contains routines for accessing the parallel port. This implements a parallel port controller as an independent process, modeled closely on the parallel port interface found on an IBM PC.
  • the controller allows simultaneous access to the control, status and data ports (as defined on an IBM PC) ofthe parallel interface. These ports are accessed by reading and writing to channels into the controller process. The reads and writes to these channels are encapsulated in other macro procedures to provide an intuitive API.
  • FIG. 5 shows a " structure of a Parallel Port Data Transmission System 500 according to an embodiment ofthe present invention.
  • An implementation of ESL's parallel data transfer protocol has also been provided, allowing data transfer over the parallel port, to and from a host computer 502. This is implemented as a separate process which utilizes the parallel port controller layer to implement the protocol. Data can be transferred to and from the host by writing and reading from channels into this process. Again macro procedure abstractions are provided to make the API more intuitive.
  • a host side application for data transfer under Windows95/98 and NT is provided. Data transfer speeds of around 100 Kbytes/s can be achieved over this interface, limited by the speed ofthe parallel port.
  • the 17 used pins ofthe port have been split into data, control and status ports as defined in the IBM PC parallel port specification. See Table 33.
  • the parallel port controller process needs to be run in parallel with those part ofthe program wishing to access the parallel port. It is recommended that this is done using a par ⁇ statement in the main() procedure.
  • the controller procedure is:
  • the parameters are all channels through which the various ports can be accessed.
  • PpReadDataQ returns the value ofthe data pins in the argument byte.
  • PpReadControlQ returns the value ofthe control port pins in the argument byte.
  • This macro requires one clock cycle.
  • the 4 bit nibble is made up of [nSelect_in @ Init @ nAutofeed @ nStrobe], where nSelect_in is the MSB.
  • PpReadStatusQ returns the value ofthe status port register in the argument byte.
  • This macro requires one clock cycle.
  • the 6 bit word passed to the macros is made up of [pp_direction @ busy @ nAck @ PE @ Select @ nError], where pp_direction indicates the direction ofthe data pins (i.e. whether they are in send [1] or receive [0] mode). It is important that this bit is set correctly before trying to write or read data from the port using PpWriteData() or PpReadData().
  • the library parallel jport.h also contains routines for transferring data to and from a host PC using ESL's data transfer protocol.
  • the data transfer process, pp_coms() which implements the transfer protocol should to be run in parallel to the parallel port controller process, again preferably in the main par ⁇ statement.
  • a host side implementation ofthe protocol, ksendexe is provided also.
  • the following macros provide interfaces to the data transfer process:
  • This macro requires one clock cycle.
  • These two macros open and close the port for receiving or sending data. They initiate a handshaking procedure to start communications with the host computer.
  • SendPP yte, error - send a byte over the port
  • ReadPP yte, error - read a byte from the port
  • ReadPPQ returns the 8 bit data value read from the host in the byte parameter. Both macros will return an error code indicating the success or failure ofthe command.
  • SendPP and ReadPP will block the thread until a byte is transmitted or the timeout value is reached. If you need to do some processing while waiting for a communication use a 'prialt' statement to read from the global pp_recv_chan channel or write to the pp_send_chan channel.
  • Figure 6 is a flowchart that shows the typical series of procedure calls 600 when receiving data.
  • Figure 7 is a flow diagram depicting the typical series of procedure calls 700 when transmitting data.
  • the ksend.exe application is designed to transfer data to and from the board FPGAs over the parallel port. It implements the ESL data transfer protocol. It is designed to communicate with the pp_comsQ process running on the FPGA. This application is still in the development stage and may have a number of bugs in it.
  • Each FPGA has access to a RS232 port allowing it to be connected to a host PC.
  • a driver for transferring data to and from the FPGAs from over the serial port is 10 contained in the file serial_port.h.
  • This interface is
  • FIG. 8 is a flow diagram illustrating several processes 802, 804 running in parallel.
  • serial port controller process is
  • SpReadDataQ returns an n bit value corresponding to the transmitted byte in the argument.
  • the execution time depends to the protocol and the baud rate being used.
  • RTS/CTS flow control idefine HARDFLOW
  • the default settings are:
  • CLOCK_RATE is defined, this is generally found in the pin definition header for each ofthe FPGAs.
  • Shown here is an example Handel-C program that illustrates how to use the parallel and serial port routines found in the serial_port.h and parallel_port.h libraries.
  • the program implements a simple echo server on the serial and parallel ports.
  • the SetLEDsO function from the klib.h library is used to display the ASCII value received over the serial port on the LEDs in binary.
  • SpReadData serial_in_data
  • SpWriteData (serial_in_data) ; // write it back out ⁇ delay; // avoid combinational cycles ⁇ void main (void) ⁇ while (1) ⁇ par ⁇ EchoPPO; //Parallel port thread
  • the code can be compiled for either FPGA by simple defining or un-defining the MASTER macro - lines 1 to 5 More Information
  • a device encapsulates the Creative MP3 encoder engine in to an FPGA device.
  • Figure 9 is a block diagram of an FPGA device 900 according to an exemplary embodiment ofthe present invention.
  • the purpose ofthe device is to stream audio data directly from a CD 902 or CDRW into the FPGA, compress the data, and push the data to a USB host 904 which delivers it to the OASIS(Nomad 2) decoder.
  • the entire operation of this device is independent of a PC.
  • ESL Embedded Solutions Limited
  • the FGPA preferably contains the necessary logic for the following:
  • USB Host / Hub controller (2 USB ports) - 4MB SDRAM

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Abstract

L'invention concerne un système, un procédé et un article de fabrication conçus pour gérer les ressources d'un système. On utilise un pilote de communications de manière à permettre à au moins deux réseaux de portes programmables par l'utilisateur de s'envoyer des messages les uns aux autres. Chaque message placé entre les réseaux de portes programmables par l'utilisateur (FPGA) comprend un code d'identification, une première partie de ce code identifiant un type du message et une seconde partie du code identifiant une demande de ressources. On traite ce code d'identification. On fait appel à une macro procédure en fonction du type de message et de l'identification de la demande de ressources. La macro procédure reçoit et traite le message.
PCT/GB2001/003243 2000-07-20 2001-07-19 Systeme, procede et article de fabrication permettant de commander l'utilisation des ressources WO2002008886A2 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
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US7783973B2 (en) 2006-12-06 2010-08-24 International Business Machines Corporation Change approvals for computing systems

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EP0790706A2 (fr) * 1996-02-14 1997-08-20 Hewlett-Packard Company Système de mémoire
US5774731A (en) * 1995-03-22 1998-06-30 Hitachi, Ltd. Exclusive control method with each node controlling issue of an exclusive use request to a shared resource, a computer system therefor and a computer system with a circuit for detecting writing of an event flag into a shared main storage
US5802290A (en) * 1992-07-29 1998-09-01 Virtual Computer Corporation Computer network of distributed virtual computers which are EAC reconfigurable in response to instruction to be executed
US5884055A (en) * 1996-11-27 1999-03-16 Emc Corporation Method and apparatus including a shared resource and multiple processors running a common control program accessing the shared resource
WO2000026796A1 (fr) * 1998-10-30 2000-05-11 Cybex Computer Products Corporation Architecture d'ordinateur fractionnee

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US5774731A (en) * 1995-03-22 1998-06-30 Hitachi, Ltd. Exclusive control method with each node controlling issue of an exclusive use request to a shared resource, a computer system therefor and a computer system with a circuit for detecting writing of an event flag into a shared main storage
EP0790706A2 (fr) * 1996-02-14 1997-08-20 Hewlett-Packard Company Système de mémoire
US5884055A (en) * 1996-11-27 1999-03-16 Emc Corporation Method and apparatus including a shared resource and multiple processors running a common control program accessing the shared resource
WO2000026796A1 (fr) * 1998-10-30 2000-05-11 Cybex Computer Products Corporation Architecture d'ordinateur fractionnee

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US7783973B2 (en) 2006-12-06 2010-08-24 International Business Machines Corporation Change approvals for computing systems

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