WO2002007316A1

WO2002007316A1 - Voltage tolerant input/output circuit

Info

Publication number: WO2002007316A1
Application number: PCT/US2001/040757
Authority: WO
Inventors: Jamil Kawa; Rahul Nimaiyar; Puneet Sawhney; Anwar Awad
Original assignee: Artisan Components, Inc.
Priority date: 2000-07-14
Filing date: 2001-05-16
Publication date: 2002-01-24
Also published as: AU2001261849A1

Abstract

The present invention provides a voltage tolerant input/output circuit configured to ensure proper interface tolerance between various close voltages in deep sub-micron circuits without any DC leakage. The voltage tolerant input/output circuit includes (1) an arbiter circuit (210) logically configured to ensure that a gate of a P-driver of the voltage tolerant input/output circuit is biased at the higher of an input/output voltage (VPAD) and an input/output supply voltage (VDDIO) when the P-driver (272) is tri-stated, (2) a bias circuit (240) logically configured to biased a floating N-well of the P-driver to ensure that no parasitic diodes formed between any source or drain of a p-device of the voltage tolerant input/output circuit and the N-well of the P-driver (272) is forward biased, and (3) a driver circuit comprising the P-driver (272).

Description

VOLTAGE TOLERANT INPUT/OUTPUT CIRCUIT

Field of the Invention

The present invention relates to electronic circuits, and particularly relates to a voltage tolerant input/output circuit configured to ensure proper interface tolerance between various close voltages in deep sub-micron circuits without any leakage.

BACKGROUND OF THE INVENTION

In older generations of CMOS technologies, the standard value of the supply voltage powering the chip was 5 volts, +/- 10%. Under that setting, the standard design of the P- driver of the Input/Output (hereinafter I/O) involved coupling the N-well of the P-driver to VDD permanently in order to permanently ensure that the N-well potential was always higher than any other voltages in the circuit. This design prevented any unwanted DC leakage through the P-driver.

In conventional CMOS integrated circuits, large N-wells are formed on p-type substrates, and PMOS transistors are formed in these N-wells. Typically, all of the P-channel transistors of the P-driver are formed in a common N-well and have substrate or terminals that are electrically integral with or connected to the N-well

In sub-micron CMOS technologies, VDD supply voltages had to scale down with the sub-micron CMOS technologies. A VDD supply voltage of 3.3 volts became standard for I/O power. This created the problem of interfacing 3.3 volt I/Os to 5 volt supplied I/Os. The problem materialized when the P-driver was tri-stated . The P-driver is tri-stated when it is in a "tri-state" or "high impedance" mode. Tristate mode occurs when the low voltage CMOS core logic circuitry associated with the tristate P- driver is not driving a bus connected to the P-driver. Instead, the low-voltage CMOS core logic circuitry is either (1) receiving data from the bus at node VPAD or (2) is not involved in any transactions occurring on the bus. In this circumstance, it is desired for the P-driver to have a high input impedance for avoiding unnecessary current sinks and for reducing overall bus inductance and capacitance.

Standard circuitry, as shown in Figure 1, addressed this problem by doing the following:

(1) floating the N-well of the P-driver; and

(2) pulling the gate of the tri-stated P-driver to PAD voltage when the PAD voltage was 5 volts.

This standard solution worked well since the difference between 5 volts, +/- 10%, and 3.3 volts, +/- 10%, always exceeded Vtp, the forward conducting voltage of the P-driver, and, also equivalent to one diode drop.

In deep sub-micron CMOS technologies, VDD supply voltages continued to scale down, sometimes below the VDD supply voltages of the sub-micron CMOS technologies. VDD supply voltages of 2.5 volts and 1.8 volts became common. These low VDD supply voltages made the interface issue (the tolerance issue) between such VDD supply voltages more complicated.

The standard sub-micron circuit technique described above for having a 3.3 volt I O tolerate a 5 volt I/O fails when the new values for the I/O VDD supply voltages and the tolerated input voltages are 2.5 volts, +/- 10%, and 3.3 volts, +/- 10%, respectively. This is because for a VDD of 2.75 volts (2.5 volts +10%) and a tolerated voltage of 3 volts (3.3 volts -10%), the voltage difference between VDD and the tolerated voltage is less than Vtp. This results in excessive and unacceptable DC leakage through the P-driver.

Therefore, a voltage tolerant input/output circuit configured to ensure proper interface tolerance between various close voltages in deep sub-micron circuits without any DC leakage is needed.

SUMMARY OF THE INVENTION

The present invention provides a voltage tolerant input/output circuit configured to ensure proper interface tolerance between various close voltages in deep sub-micron circuits without any DC leakage.

The voltage tolerant input/output circuit includes (1) an arbiter circuit logically configured to ensure that a gate of a P-driver of the voltage tolerant input/output circuit is biased at the higher of an input/output voltage and an input/output supply voltage when the P- driver is tri-stated, (2) a bias circuit logically configured to biased a floating N-well of the P- driver to ensure that no parasitic diodes formed between any source or drain of a p-device of the voltage tolerant input/output circuit and the N-well of the P-driver is forward biased, and (3) a driver circuit comprising the P-driver.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a circuit diagram of a prior art voltage tolerant circuit for sub-micron

CMOS technologies.

Figure 2 is a circuit diagram of a voltage tolerant input/output circuit in accordance with an exemplary embodiment of the present invention.

Figure 3 is a trace diagram of the PAD voltage and the gate voltage of the tri-stated P- driver of the voltage tolerant input/output circuit in accordance with an exemplary embodiment of the present invention.

Figure 4 is a trace diagram of the current through the VDD supply voltage of the I/O of the tri-stated P-driver of the voltage tolerant input/output circuit in accordance with an exemplary embodiment of the present invention. Figure 5 is a trace diagram of the current through the P-driver of the tri-stated P-driver of the voltage tolerant input/output circuit in accordance with an exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Referring to Figure 2, a voltage tolerant input/output circuit 200 in accordance with an exemplary embodiment of the present invention is shown.

In an exemplary embodiment, voltage tolerant I/O circuit 200 is implemented with an all PMOS substrate logically coupled to a N-well. Configuration of the Voltage Tolerant Input/Output Circuit

In an exemplary embodiment, the voltage tolerant input/output circuit 200 includes the following components logically interconnected as shown in Figure 2: (1) an arbiter circuit 210; (2) a bias circuit 240; and

(3) a driver circuit 270. In an exemplary embodiment, arbiter circuit 210 includes the following components logically interconnected as shown in Figure 2:

(I) a first transistor 212 (e.g. PI); (2) a second transistor 214 (e.g. P2);

(3) a pass gate 216 (e.g. N2, P3);

(4) a third transistor 218 (e.g. P4);

(5) a fourth transistor 220 (e.g. P5);

(6) a fifth transistor 222 (e.g. P6); (7) a sixth transistor 224 (e.g. P7);

(8) an inverter 226 (e.g. INI);

(9) a predriver input 228;

(10) a PAD input 230; and

(II) a Vddio terminal 205. In an exemplary embodiment, transistors 212 and 222 and pass gate 216 are logically coupled to an I/O supply voltage Vddio via Vddio terminal 205 as shown in Figure 2. Li an exemplary embodiment, pass gate 216 is logically coupled to a predriver voltage Vpredriver via predriver input 228 as shown in Figure 2. In an exemplary embodiment, transistor 214 is logically coupled to a PAD voltage, VPAD, via PAD input 230 as shown in Figure 2. In an exemplary embodiment, bias circuit 240 includes the following components logically interconnected as shown in Figure 2:

(1) a seventh transistor 242 (e.g. P8);

(2) an eight transistor 244 (e.g. P9); (3) a ninth transistor 246 (e.g. Nl); and

(4) Vddio terminal 205. In an exemplary embodiment, transistors 242, 244, AND 246, are logically coupled to I/O supply voltage Vddio via Vddio terminal 205 as shown in Figure 2. In an exemplary embodiment, transistors 242 and 244 are logically coupled to PAD voltage, VPAD, via PAD input 230 as shown in Figure 2. In an exemplary embodiment, driver circuit 270 includes a tenth transistor 272, also known as a P-driver, logically interconnected with arbiter circuit 210 and bias circuit 240 as shown in Figure 2. In an exemplary embodiment, P-driver 272 is logically coupled to I O supply voltage Vddio as shown in Figure 2. In an exemplary embodiment, P-driver 272 is logically coupled to PAD voltage, VPAD, via PAD input 230 as shown in Figure 2. Also, P- driver 272 is logically coupled to transistors 218 and 220, inverter 226, and pass gate 216 as shown in Figure 2.

Operation of the Voltage Tolerant Input/Output Circuit

In an exemplary embodiment, voltage tolerant input/output circuit 200, via the logical configuration shown in Figure 2, ensures proper interface tolerance between various close voltages in deep sub-micron circuits without any DC leakage in an exemplary embodiment of the present invention. Voltage tolerant I/O circuit 200 solves the tolerance problem for any interface situation in deep sub-micron circuits whether the difference in the value of VPAD and Vddio exceeds Vtp or not. Voltage tolerant I O circuit 200 ensures that there is zero DC leakage across P-driver 272 and ensures that the N-well of P-driver 272 is always biased to the higher of the two voltages, Vddio and VPAD at all times. Arbiter Circuit In an exemplary embodiment, arbiter circuit 210, via the logical configuration shown in Figure 2, ensures that the gate of P-driver 272 is biased at the higher of VPAD and Vddio at all times when P-driver 272 is tri-stated. By ensuring this biasing, arbiter circuit 210 ensures that there is not DC leakage between VPAD and Vddio, regardless of the difference in magnitude between VPAD and Vddio.

In an exemplary embodiment, via the logical configuration shown in Figure 2, transistor 212 (e.g. PI) biases the gate of transistor 214 (e.g. P2) to a voltage equaling Vddio-Vtp. This biasing of transistor 214 ensures that transistor 214 and transistor 218 (e.g. P4) will pass the full magnitude of VPAD to the gate of P-driver 272, and, thus, shuts off any DC leakage path through P-driver 272.

In an exemplary embodiment, via the logical configuration shown in Figure 2, pass gate 216 (e.g. N2, P3) is biased to ensure that when the gate of P-driver 272 is at VPAD, that is when VPAD is greater than Vddio, there is no DC leakage from VPAD to core circuitry logically coupled to predriver input 228.

In an exemplary embodiment, via the logical configuration shown in Figure 2, transistor 220 (e.g. P5), transistor 222 (e.g. P6), and transistor 224 (e.g. P7) ensure that during the tri-stating of P-driver 272, the lowest voltage that the gate of P-driver 272 can see is Vddio. The lowest voltage that the gate of P-driver 272 can see being Vddio is needed in either of the following situations:

(1) VPAD is a low voltage level corresponding to a logic LOW value for VPAD; or

(2) VPAD equals Vddio.

Bias Circuit

In an exemplary embodiment, bias circuit 240, via the logical configuration shown in Figure 2, biases the floating N-well of P-driver 272, and, thus, ensures that no parasitic diodes formed between any source or drain of p-device (e.g. a p-transistor) and the N-well of P-driver 272 is forward biased. In an exemplary embodiment, via the logical configuration shown in Figure 2, transistor 246 (e.g. Nl) ensures that the N-well of P-driver 272 has a minimum bias of

Vddio-Vtn.

Vtn is the forward conducting voltage of transistor 246, and is also equivalent to one diode drop.

In an exemplary embodiment, via the logical configuration shown in Figure 2, transistor 244 (e.g. P9) pulls the N-well of P-driver 272 to VPAD if VPAD is greater than

Vddio. In an exemplary embodiment, via the logical configuration shown in Figure 2, transistor 242 (e.g. P8) pulls the N-well of P-driver 272 to Vddio if VPAD is LOW, as in the normal operations of an I O circuit logically coupled to voltage tolerant input/output circuit 200.

Driver Circuit In an exemplary embodiment, driver circuit 270, via the logical configuration shown in Figure 2, operates as P-driver 272. Generally

VPAD and Gate voltage of the Tri-stated P-driver of the Voltage Tolerant Input/Output Circuit Referring to Figure 3, the PAD voltage, VPAD, and the gate voltage of the tri-stated P-driver of the voltage tolerant input/output circuit in accordance with an exemplary embodiment of the present invention is shown in a trace diagram 300. Trace diagram 300 includes trace 310 of VPAD and trace 220 of the voltage at the gate of a tri-stated P-driver 272. Trace 220 shows how the voltage at the gate of tri-stated P-driver 272 varies as VPAD varies from 0 volts to 3 volts, as shown by trace 310. In an exemplary embodiment, Vddio is 2.75 volts. In Figure 3, the voltage at the gate of P-driver 272 is always high. The voltage at the gate of P-driver 272 being always high blocks any DC leakage from PAD terminal 230 to Vddio terminal 205.

Referring to Figure 4, the current through the VDD supply voltage, Vddio, of the I/O of the tri-stated P-driver of the voltage tolerant input/output circuit in accordance with an exemplary embodiment of the present invention is shown in a trace diagram 400. Trace diagram 400 includes trace 410 of the current through Vddio terminal 205. Trace 410 shows a zero leakage current through Vddio terminal 205 at all times except at switching transition times 412 and 414, when switching transients occur.

Referring to Figure 5, the current (leakage) through P-driver 272 of the tri-stated voltage tolerant input/output circuit in accordance with an exemplary embodiment of the present invention is shown in a trace diagram 500. Trace diagram 500 includes trace 510 of the current (leakage) through P-driver 272. Trace 510 shows that, except for a switching transient current at transition times 512 and 514, the current (leakage current) through P- driver 272 is zero. Summary

In sum, in an exemplary embodiment, voltage tolerant input/output circuit 200, via the logical configuration of arbiter circuit 210, bias circuit 240, and driver circuit 270, as shown in Figure 2, ensures proper interface tolerance between various close voltages in deep sub- micron circuits without any DC leakage in an exemplary embodiment of the present invention.

Conclusion

Having fully described a preferred embodiment of the invention and various alternatives, those skilled in the art will recognize, given the teachings herein, that numerous alternatives and equivalents exist which do not depart from the invention. It is therefore intended that the invention not be limited by the foregoing description, but only by the appended claims.

Claims

1. A voltage tolerant input/output circuit configured to ensure proper interface tolerance between various close voltages in deep sub-micron circuits without any DC leakage, comprising: an arbiter circuit logically configured to ensure that a gate of a P-driver of the voltage tolerant input/output circuit is biased at the higher of an input/output voltage and an input/output supply voltage when the P-driver is tri-stated; a bias circuit logically configured to bias a floating N-well of the P-driver to ensure that no parasitic diodes formed between any source or drain of a p-device of the voltage tolerant input/output circuit and the N-well of the P-driver is forward biased; and a driver circuit comprising the P-driver.

2. The circuit of claim 1 wherein the arbiter circuit is logically configured to ensure that there is no DC leakage current between the input/output voltage and the input/output supply voltage, regardless of the difference in magnitude between the input/output voltage and the input/output supply voltage.

3. The circuit of claim 1 wherein the arbiter circuit comprises: a first transistor of a first type; and a second transistor of a second type, wherein the first transistor of the first type is logically configured to bias the gate of the second transistor of the second type to a voltage equaling the difference between the input/output supply voltage and the forward conducting voltage of the P-driver, and, thus, ensures that second transistor 214 and the fourth transistor will pass the full magnitude of the input/output yoltage to the gate of the P-driver, and, thus, shuts off any DC leakage path through the P-driver .

4. The circuit of claim 1 wherein the bias circuit is logically configured to ensure that the N-well of the P-driver has a minimum bias equal to the difference between the input/output supply voltage and the fo<. ard conducting voltage of a n-type transistor.