WO2002006929A2 - Commande d'acces a de multiples memoires isolees dans un environnement d'execution isole - Google Patents

Commande d'acces a de multiples memoires isolees dans un environnement d'execution isole Download PDF

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Publication number
WO2002006929A2
WO2002006929A2 PCT/US2001/022027 US0122027W WO0206929A2 WO 2002006929 A2 WO2002006929 A2 WO 2002006929A2 US 0122027 W US0122027 W US 0122027W WO 0206929 A2 WO0206929 A2 WO 0206929A2
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WO
WIPO (PCT)
Prior art keywords
access
isolated
page
memory
processor
Prior art date
Application number
PCT/US2001/022027
Other languages
English (en)
Other versions
WO2002006929A3 (en
Inventor
Roger Golliver
James Ii Sutton
Derrick Lin
Shreekant Thakkar
Gilbert Neiger
Francis Mckeen
Howard Herbert
Kenneth Reneris
Carl Ellison
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/618,738 external-priority patent/US6678825B1/en
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to DE10196440T priority Critical patent/DE10196440B4/de
Priority to JP2002512776A priority patent/JP3982687B2/ja
Priority to AU2001271996A priority patent/AU2001271996A1/en
Priority to GB0303644A priority patent/GB2381626B/en
Publication of WO2002006929A2 publication Critical patent/WO2002006929A2/fr
Publication of WO2002006929A3 publication Critical patent/WO2002006929A3/en
Priority to HK03104417.4A priority patent/HK1052237B/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights
    • G06F12/1466—Key-lock mechanism
    • G06F12/1475—Key-lock mechanism in a virtual system, e.g. with translation means

Definitions

  • This invention relates to microprocessors.
  • the invention relates to processor security.
  • Threats caused by unscrupulous attacks may be in a number of forms.
  • An invasive remote-launched attack by hackers may disrupt the normal operation of a system connected to thousands or even millions of users.
  • a virus program may corrupt code and/or data of a single-user platform.
  • Figure 1A is a diagram illustrating an operating system according to one embodiment of the invention.
  • Figure IB is a diagram illustrating the accessibility of various elements in the operating system and the processor and a single contiguous isolated memory area according to one embodiment of the invention.
  • Figure 1C is a diagram, similar to Figure IB, illustrating the accessibility of various elements in the operating system and the processor, and particularly, multiple isolated memory areas and multiple non-isolated memory areas, according to one embodiment of the invention.
  • Figure ID is a flowchart illustrating a process to distribute pages of memory for isolated execution according to one embodiment of the invention.
  • Figure IE is a diagram illustrating a memory ownership page table and a process of converting a virtual address to a physical address according to one embodiment of the invention.
  • Figure IF is a diagram illustrating a computer system in which one embodiment of the invention can be practiced.
  • Figure 2A is a diagram illustrating the isolated execution circuit shown in Figure IF according to one embodiment of the invention.
  • Figure 2B is a diagram illustrating the access manager shown in Figure 2A according to one embodiment of the invention.
  • Figure 3 A is a diagram illustrating an access checking circuit according to one embodiment of the invention.
  • Figure 3B is a diagram illustrating the access checking circuit to manage logical processor operations according to another embodiment of the invention.
  • Figure 4 is a flowchart illustrating a process to generate an access grant signal for isolated execution according to one embodiment of the invention.
  • Figure 5 is a flowchart illustrating a process to manage process thread operations for isolated execution according to one embodiment of the invention.
  • FIG 6 is a diagram illustrating the isolated area access control in the memory controller hub (MCH) shown in Figure IF according to one embodiment of the invention.
  • Figure 7 is a diagram illustrating the MCH access checking circuit shown in Figure 6 according to one embodiment of the invention.
  • Figure 8 is a flowchart illustrating a process to generate an access grant signal for isolated execution for an MCH according to one embodiment of the invention.
  • the present invention is a method, apparatus and system to control memory accesses to multiple isolated memories in an isolated execution environment.
  • a page manager is used to distribute a plurality of pages to a plurality of different areas of a memory, respectively.
  • the memory is divided into non-isolated areas and isolated areas.
  • the page manager is located in an isolated area of memory.
  • a memory ownership page table describes each page of memory and is also located in an isolated area of memory.
  • the page manager assigns an isolated attribute to a page if the page is distributed to an isolated area of memory.
  • the page manager assigns a non-isolated attribute to a page if the page is distributed to a non-isolated area of memory.
  • the memory ownership page table records the attribute for each page.
  • a processor having a normal execution mode and an isolated execution mode generates an access transaction.
  • the access transaction is configured using a configuration storage that contains configuration settings.
  • the access transaction includes access information such as a physical address of the memory to be accessed.
  • the configuration settings provide information related to a page of memory involved in the access transaction.
  • the configuration settings include an attribute for the page that defines the page as isolated or non-isolated and an execution mode word that is asserted when the processor is configured in an isolated execution mode.
  • the execution mode word is a single bit indicating if the processor is in the isolated execution mode.
  • An access checking circuit coupled to the configuration storage checks the access transaction using at least one of the configuration settings and the access information.
  • the access checking circuit includes a TLB access checking circuit.
  • the TLB access checking circuit generates an access grant signal if the access transaction is valid. Particularly, if the attribute for the page is set to isolated and the execution mode word signal is asserted, the TLB access checking circuit generates an access grant signal to the isolated area of memory.
  • the isolated execution architecture includes logical and physical definitions of hardware and software components that interact directly or indirectly with an operating system of the computer system or platform.
  • An operating system and the processor may have several levels of hierarchy, referred to as rings, corresponding to various operational modes.
  • a ring is a logical division of hardware and software components that are designed to perform dedicated tasks within the operating system. The division is typically based on the degree or level of privilege, namely, the ability to make changes to the platform. For example, a ring-0 is the innermost ring, being at the highest level of the hierarchy. Ring-0 encompasses the most critical, privileged components. In addition, modules in Ring-0 can also access lesser privileged data, but not vice versa.
  • Ring-3 is the outermost ring, being at the lowest level of the hierarchy. Ring-3 typically encompasses users or applications level and has the least privilege. Ring-1 and ring-2 represent the intermediate rings with decreasing levels of security and/or protection.
  • FIG. 1A is a diagram illustrating a logical operating architecture 50 according to one embodiment of the invention.
  • the logical operating architecture 50 is an abstraction of the components of an operating system and the processor.
  • the logical operating architecture 50 includes ring-0 10, ring-1 20, ring-2 30, ring-3 40, and a processor nub loader 52.
  • the processor nub loader 52 is an instance of an processor executive (PE) handler.
  • the PE handler is used to handle and/or manage a processor executive (PE) as will be discussed later.
  • the logical operating architecture 50 has two modes of operation: normal execution mode and isolated execution mode. Each ring in the logical operating architecture 50 can operate in both modes.
  • the processor nub loader 52 operates only in the isolated execution mode.
  • the Ring-0 10 includes two portions: a normal execution Ring-0 11 and an isolated execution Ring-0 15.
  • the normal execution Ring-0 11 includes software modules that are critical for the operating system, usually referred to as kernel. These software modules include primary operating system (e.g., kernel) 12, software drivers 13, and hardware drivers 14.
  • the isolated execution Ring-0 15 includes an operating system (OS) nub 16 and a processor nub 18.
  • the OS nub 16 and the processor nub 18 are instances of an OS executive (OSE) and processor executive (PE), respectively.
  • the OSE and the PE are part of executive entities that operate in a protected environment associated with an isolated area and the isolated execution mode.
  • the processor nub loader 52 is a protected bootstrap loader code held within a chipset in the system and is responsible for loading the processor nub 18 from the processor or chipset into an isolated area as will be explained later.
  • ring-1 20, ring-2 30, and ring-3 40 include normal execution ring-1 21, ring-2 31, ring-3 41, and isolated execution ring-1 25, ring-2 35, and ring-3 45, respectively.
  • normal execution ring-3 includes N applications 42 ⁇ to 42 N and isolated execution ring-3 includes K applets 46 ⁇ to 46 ⁇ .
  • isolated execution architecture is the creation of an isolated region in the system memoiy, referred to as an isolated area, which is protected by both the processor and chipset in the computer system.
  • the isolated region may also be in cache memory, protected by a translation look aside buffer (TLB) access check.
  • TLB translation look aside buffer
  • the isolated region may be subdivided into multiple isolated memory areas, as will be discussed. Access to this isolated region is permitted only from a front side bus (FSB) of the processor, using special bus (e.g., memory read and write) cycles, referred to as isolated read and write cycles.
  • the special bus cycles are also used for snooping.
  • the isolated read and write cycles are issued by the processor executing in an isolated execution mode.
  • the isolated execution mode is initialized using a privileged instruction in the processor, combined with the processor nub loader 52.
  • the processor nub loader 52 verifies and loads a ring-0 nub software module (e.g., processor nub 18) into the isolated area.
  • the processor nub 18 provides hardware-related services for the isolated execution.
  • One task of the processor nub 18 is to verify and load the ring-0 OS nub 16 into the isolated area, and to generate the root of a key hierarchy unique to a combination of the platform, the processor nub 18, and the operating system nub 16.
  • the processor nub 18 provides the initial set-up and low-level management of the isolated area including verification, loading, and logging of the operating system nub 16, and the management of a symmetric key used to protect the operating system nub's secrets.
  • the processor nub 18 may also provide application programming interface (API) abstractions to low-level security services provided by other hardware.
  • API application programming interface
  • the operating system nub 16 provides links to services in the primary OS 12 (e.g., the unprotected segments of the operating system), provides page management within the isolated area, and has the responsibility for loading ring-3 application modules 45, including applets 46 ⁇ to 46 ⁇ , into protected pages allocated in the isolated area.
  • the operating system nub 16 may also load ring-0 supporting modules.
  • the primary OS 12 manages pages that are outside of the isolated area.
  • the operating system nub 16 may choose to support paging of data between the isolated area and ordinary (e.g., non-isolated) memory.
  • the operating system nub 16 is also responsible for encrypting and hashing the isolated area pages before evicting the page to the ordinary memory, and for checking the page contents upon restoration of the page.
  • the isolated mode applets 46 ⁇ to 46 ⁇ and their data are tamper- resistant and monitor-resistant from all software attacks from other applets, as well as from non-isolated-space applications (e.g., 42 1 to 42 N ), dynamic link libraries (DLLs), drivers and even the primary operating system 12. Only the processor nub 18 or the operating system nub 16 can interfere with or monitor the applet's execution.
  • Figure IB is a diagram illustrating accessibility of various elements in the operating system 10 and the processor according to one embodiment of the invention. For illustration purposes, only elements of ring-0 10 and ring-3 40 are shown. The various elements in the logical operating architecture 50 access an accessible physical memory 60 according to their ring hierarchy and the execution mode.
  • the accessible physical memory 60 includes an isolated area 70 and a non-isolated area 80.
  • the isolated area 70 includes applet pages 72 and nub pages 74.
  • the non- isolated area 80 includes application pages 82 and operating system pages 84.
  • the isolated area 70 is accessible only to elements of the operating system and processor operating in isolated execution mode.
  • the non-isolated area 80 is accessible to all elements of the ring-0 operating system and processor.
  • the normal execution ring-0 11 including the primary OS 12, the software drivers 13, and the hardware drivers 14, can access both the OS pages 84 and the application pages 82.
  • the normal execution ring-3, including applications 421 to 42 N can access only to the application pages 82.
  • Both the normal execution ring-0 11 and ring-3 41 cannot access the isolated area 70.
  • the isolated execution ring-0 15, including the OS nub 16 and the processor nub 18, can access both the isolated area 70, including the applet pages 72 and the nub pages 74, and the non-isolated area 80, including the application pages 82 and the OS pages 84.
  • the isolated execution ring-3 45, including applets 46 ⁇ to 46 ⁇ can access only to the application pages 82 and the applet pages 72.
  • the applets 46 j to 46 ⁇ reside in the isolated area 70.
  • Figure 1C is a diagram, similar to Figure IB, illustrating the accessibility of various elements in the operating system and the processor, in which, the isolated memory area 70 is divided into multiple isolated memory areas 71 and the non-isolated memory area 80 is divided into multiple non-isolated memory areas 83, according to one embodiment of the invention. For illustration purposes, only elements of ring-0 10 and ring-3 40 are shown.
  • the various elements in the logical operating architecture 50 access an accessible physical memory 60 according to their ring hierarchy and the execution mode.
  • the accessible physical memory 60 includes the multiple isolated areas 71 and the multiple non-isolated areas 83.
  • the multiple isolated areas 71 include applet pages 72 and operating system (OS) nub pages 74.
  • One of the multiple isolated areas 71 also includes the processor nub 18 (i.e. the processor executive (PE)), embodied in processor nub pages 73.
  • the multiple non-isolated areas 83 include application pages 82 and operating system (OS) pages 84.
  • the multiple isolated areas 71 are accessible only to elements of the operating system and processor operating in isolated execution mode.
  • the non-isolated areas 83 are accessible to all elements of the ring-0 operating system and processor.
  • the isolated memory area 70 is divided up into a plurality of multiple isolated memoiy areas 71 allowing for increased platform functionality in using isolated memory, as opposed to the single block of isolated memory area 70 shown in Figure IB.
  • the OS nub 16 i.e. the OS executive (OSE)
  • OS nub pages 74 contains a page manager 75 and a memory ownership page table 77.
  • the OS nub controls the page manager 75.
  • the page manager 75 is responsible for distributing pages to multiple isolated memory areas 71, such as OS nub pages 74 and applet pages 72, and to the non- isolated memory areas 83, such as OS pages 84 and application pages 82.
  • the page manager 75 also manages and maintains the memory ownership page table 77.
  • the memory ownership page table 77 describes each page and is used to help configure access transactions by a processor and further to verify that the access transaction is valid.
  • the normal execution ring-0 11 including the primary OS 12, the software drivers 13, and the hardware drivers 14, can access both the OS pages 84 and the application pages 82.
  • the normal execution ring-3, including applications 421 to 42N, can access only the application pages 82. Both the normal execution ring-0 11 and ring-3 41, however, cannot access the multiple isolated memory areas 71.
  • the isolated execution ring-0 15, including the OS nub 16 and the processor nub 18, can access both the multiple isolated memory areas 71, including the applet pages 72 and the OS nub pages 74, and the multiple non-isolated memory areas 83, including the application pages 82 and the OS pages 84.
  • the isolated execution ring-3 45, including applets 46 ⁇ to 46 ⁇ can access only the application pages 82 and the applet pages 72.
  • the applets 46 ⁇ to 46 ⁇ reside in the multiple isolated memory areas 71.
  • Figure ID is a flowchart illustrating a process 86 to distribute pages of memory for isolated execution according to one embodiment of the invention.
  • the process 86 distributes pages of memory to different areas of accessibly physical memory 60, respectively (block 87).
  • the pages are distributed to both isolated areas 71 and non-isolated areas 83.
  • the size of the pages is fixed.
  • each page may be 4 MB or 4 KB.
  • the process 86 assigns an attribute to each page (block 88).
  • the process 86 assigns an isolated attribute to a page if the page is distributed to an isolated area of memory, or, the process 86 assigns a non-isolated attribute to a page if the page is distributed to a non-isolated area of memory.
  • the process 86 is then terminated.
  • Figure IE is a diagram illustrating the memory ownership page table 77 and a process of converting a virtual address to a physical address according to one embodiment of the invention.
  • the page manager 75 manages the memory ownership page table 77.
  • the memory ownership page table 77 includes a plurality of page table entries 93.
  • Each page table entry 93 includes the following components: the base of the page 95 and an attribute 96 (isolated or non-isolated) for the page. Only the page manager 75 can change the attribute 96 assigned to a page.
  • Each page 98 includes a plurality of physical addresses 99.
  • the page manager 75 flushes the memory ownership page table 77 or invalidates a page table entry 93 when the isolated and non-isolated memory areas change.
  • the page manager 75 then reassigns and initializes the isolated and non-isolated memory areas.
  • a virtual address 212 includes a page table component 91 and an offset 92. The process of converting the virtual address 212 to a physical address 99 will be discussed later.
  • FIG. IF is a diagram illustrating a computer system 100 in which one embodiment of the invention can be practiced.
  • the computer system 100 includes a processor 110, a host bus 120, a memory controller hub (MCH) 130, a system memory 140, an input/output controller hub (ICH) 150, a non-volatile memory, or system flash, 160, a mass storage device 170, input/output devices 175, a token bus 180, a motherboard (MB) token 182, a reader 184, and a token 186.
  • the MCH 130 may be integrated into a chipset that integrates multiple functionalities such as the isolated execution mode, host- to-peripheral bus interface, memory control.
  • the ICH 150 may also be integrated into a chipset together or separate from the MCH 130 to perform I/O functions.
  • peripheral buses such as Peripheral Component Interconnect (PCI), accelerated graphics port (AGP), Industry Standard Architecture (ISA) bus, and Universal Serial Bus (USB), etc.
  • PCI Peripheral Component Interconnect
  • AGP accelerated graphics port
  • ISA Industry Standard Architecture
  • USB Universal Serial Bus
  • the processor 110 represents a central processing unit of any type of architecture, such as complex instruction set computers (CISC), reduced instruction set computers (RISC), very long instruction word (VLIW), or hybrid architecture.
  • the processor 110 is compatible with an Intel Architecture (IA) processor, such as the PentiumTM series, the IA-32TM and the IA-64TM.
  • the processor 110 includes a normal execution mode 112 and an isolated execution circuit 115.
  • the normal execution mode 112 is the mode in which the processor 110 operates in a non-protected environment, or a normal environment without the security features provided by the isolated execution mode.
  • the isolated execution circuit 115 provides a mechanism to allow the processor 110 to operate in an isolated execution mode.
  • the isolated execution circuit 115 provides hardware and software support for the isolated execution mode. This support includes configuration for isolated execution, definition of an isolated area or isolated areas, definition (e.g., decoding and execution) of isolated instructions, generation of isolated access bus cycles, and generation of isolated mode interrupts.
  • the computer system 100 can be a single processor system, such as a desktop computer, which has only one main central processing unit, e.g. processor 110.
  • the computer system 100 can include multiple processors, e.g. processors 110, 110a, 110b, etc., as shown in Figure ID.
  • the computer system 100 can be a multi-processor computer system having any number of processors.
  • the multi-processor computer system 100 can operate as part of a server or workstation environment. The basic description and operation of processor 110 will be discussed in detail below.
  • processor 110 applies to the other processors 110a and 110b, shown in Figure ID, as well as any number of other processors that may be utilized in the multi-processor computer system 100 according to one embodiment of the present invention.
  • the processor 110 may also have multiple logical processors.
  • a logical processor sometimes referred to as a thread, is a functional unit within a physical processor having an architectural state and physical resources allocated according to some partitioning policy. Within the context of the present invention, the terms "thread” and "logical processor" are used to mean the same thing.
  • a multi-threaded processor is a processor having multiple threads or multiple logical processors.
  • a multi-processor system (e.g., the system comprising the processors 110, 110a, and 110b) may have multiple multi-threaded processors.
  • the host bus 120 provides interface signals to allow the processor 110 or processors 110, 110a, and 110b to communicate with other processors or devices, e.g., the MCH 130.
  • the host bus 120 provides an isolated access bus mode with corresponding interface signals for memory read and write cycles when the processor 110 is configured in the isolated execution mode.
  • the isolated access bus mode is asserted on memory accesses initiated while the processor 110 is in the isolated execution mode.
  • the isolated access bus mode is also asserted on instruction pre-fetch and cache write-back cycles if the address is within the isolated area address range and the processor 110 is initialized in the isolated execution mode.
  • the processor 110 responds to snoop cycles to a cached address within the isolated area address range if the isolated access bus cycle is asserted and the processor 110 is initialized into the isolated execution mode.
  • the MCH 130 provides control and configuration of memory and input/output devices such as the system memory 140 and the ICH 150.
  • the MCH 130 provides interface circuits to recognize and service isolated access assertions on memory reference bus cycles, including isolated memory read and write cycles.
  • the MCH 130 has memory range registers (e.g., base and length registers) to represent the isolated area, or isolated areas, in the system memory 140. Once configured, the MCH 130 aborts any access to an isolated area that does not have the isolated access bus mode asserted.
  • the system memory 140 stores system code and data.
  • the system memory 140 is typically implemented with dynamic random access memory (DRAM) or static random access memory (SRAM).
  • the system memory 140 includes the accessible physical memory 60 (shown in Figures IB and 1C).
  • the accessible physical memory includes a loaded operating system 142, the isolated area 70 ( Figure IB) or isolated areas 71 ( Figure 1C), and an isolated control and status space 148.
  • the loaded operating system 142 is the portion of the operating system that is loaded into the system memory 140.
  • the loaded OS 142 is typically loaded from a mass storage device via some boot code in a boot storage such as a boot read only memory (ROM).
  • ROM boot read only memory
  • the isolated area 70 ( Figure IB) or isolated areas 71 ( Figure 1C), is the memory area that is defined by the processor 110 when operating in the isolated execution mode. Access to the isolated area(s) is restricted and is enforced by the processor 110 and/or the MCH 130 or other chipset that integrates the isolated area functionalities.
  • the isolated control and status space 148 is an input/output (I/O)-like, independent address space defined by the processor 110 and/or the MCH 130.
  • the isolated control and status space 148 contains mainly the isolated execution control and status registers.
  • the isolated control and status space 148 does not overlap any existing address space and is accessed using the isolated bus cycles.
  • the system memory 140 may also include other programs or data which are not shown.
  • the ICH 150 represents a known single point in the system having the isolated execution functionality. For clarity, only one ICH 150 is shown. The system 100 may have many ICH's similar to the ICH 150. When there are multiple ICH's, a designated ICH is selected to control the isolated area configuration and status. In one embodiment, this selection is performed by an external strapping pin. As is known by one skilled in the art, other methods of selecting can be used, including using programmable configuring registers. The ICH 150 has a number of functionalities that are designed to support the isolated execution mode in addition to the traditional I/O functions.
  • the ICH 150 includes an isolated bus cycle interface 152, the processor nub loader 52 (shown in Figure 1A), a digest memory 154, a cryptographic key storage 155, an isolated execution logical processing manager 156, and a token bus interface 159.
  • the isolated bus cycle interface 152 includes circuitry to interface to the isolated bus cycle signals to recognize and service isolated bus cycles, such as the isolated read and write bus cycles.
  • the processor nub loader 52 includes a processor nub loader code and its digest (e.g., hash) value.
  • the processor nub loader 52 is invoked by execution of an appropriated isolated instruction (e.g., Iso-Init) and is transferred to the isolated area 70, or one of the isolated areas 71.
  • the processor nub loader 52 copies the processor nub 18 from the system flash (e.g., the processor nub code 18 in non-volatile memory 160) into the isolated area 70, verifies and logs its integrity, and manages a symmetric key used to protect the processor nub's secrets.
  • the processor nub loader 52 is implemented in read only memory (ROM).
  • ROM read only memory
  • the processor nub loader 52 is unchanging, tamper-resistant and non-substitutable.
  • the digest memory 154 typically implemented in RAM, stores the digest (e.g., hash) values of the loaded processor nub 18, the operating system nub 16, and any other critical modules (e.g., ring-0 modules) loaded into the isolated execution space.
  • the cryptographic key storage 155 holds a symmetric encryption/decryption key that is unique for the platform of the system 100.
  • the cryptographic key storage 155 includes internal fuses that are programmed at manufacturing. Alternatively, the cryptographic key storage 155 may also be created with a random number generator and a strap of a pin.
  • the isolated execution logical processing manager 156 manages the operation of logical processors operating in isolated execution mode. In one embodiment, the isolated execution logical processing manager 156 includes a logical processor count register that tracks the number of logical processors participating in the isolated execution mode.
  • the token bus interface 159 interfaces to the token bus 180.
  • a combination of the processor nub loader digest, the processor nub digest, the operating system nub digest, and optionally additional digests represents the overall isolated execution digest, referred to as isolated digest.
  • the isolated digest is a fingerprint identifying the ring-0 code controlling the isolated execution configuration and operation.
  • the isolated digest is used to attest or prove the state of the current isolated execution.
  • the non- volatile memory 160 stores non-volatile information. Typically, the nonvolatile memory 160 is implemented in flash memory. The non- volatile memory 160 includes the processor nub 18.
  • the processor nub 18 provides the initial set-up and low-level management of the isolated area(s) (in the system memory 140), including verification, loading, and logging of the operating system nub 16, and the management of the symmetric key used to protect the operating system nub's secrets.
  • the processor nub 18 may also provide application programming interface (API) abstractions to low-level security services provided by other hardware.
  • the processor nub 18 may also be distributed by the original equipment manufacturer (OEM) or operating system vendor (OSV) via a boot disk.
  • OEM original equipment manufacturer
  • OSV operating system vendor
  • the mass storage device 170 stores archive information such as code (e.g., processor nub 18), programs, files, data, applications (e.g., applications 421 to 42 N ), applets (e.g., applets 46 ⁇ to 46 ⁇ ) and operating systems.
  • the mass storage device 170 may include compact disk (CD) ROM 172, floppy diskettes 174, and hard drive 176, and any other magnetic or optic storage devices.
  • the mass storage device 170 provides a mechanism to read machine-readable media.
  • I/O devices 175 may include any I/O devices to perform I/O functions. Examples of I/O devices 175 include controller for input devices (e.g., keyboard, mouse, trackball, pointing device), media card (e.g., audio, video, graphics), network card, and any other peripheral controllers.
  • the token bus 180 provides an interface between the ICH 150 and various tokens in the system.
  • a token is a device that performs dedicated input/output functions with security functionalities.
  • a token has characteristics similar to a smart card, including at least one reserved-purpose public/private key pair and the ability to sign data with the private key. Examples of tokens connected to the token bus 180 include a motherboard token 182, a token reader 184, and other portable tokens 186 (e.g., smart card).
  • the token bus interface 159 in the ICH 150 connects through the token bus 180 to the ICH 150 and ensures that when commanded to prove the state of the isolated execution, the corresponding token (e.g., the motherboard token 182, the token 186) signs only valid isolated digest information. For purposes of security, the token should be connected to the digest memory.
  • the elements of the present invention are the code segments to perform the necessary tasks.
  • the program or code segments can be stored in a machine readable medium, such as a processor readable medium, or transmitted by a computer data signal embodied in a carrier wave, or a signal modulated by a carrier, over a transmission medium.
  • the "processor readable medium” may include any medium that can store or transfer information. Examples of the processor readable medium include an electronic circuit, a semiconductor memory device, a ROM, a flash memory, an erasable programmable ROM (EPROM), a floppy diskette, a compact disk CD-ROM, an optical disk, a hard disk, a fiber optic medium, a radio frequency (RF) link, etc.
  • the computer data signal may include any signal that can propagate over a transmission medium such as electronic network channels, optical fibers, air, electromagnetic, RF links, etc.
  • the code segments may be downloaded via computer networks such as the Internet, Intranet, etc.
  • the present invention is a method, apparatus, and system to control memory accesses to multiple isolated memories 71, as shown in Figure 1C, in an isolated execution environment.
  • Figure 2A is a diagram illustrating the isolated execution circuit 115 shown in Figure IF according to one embodiment of the invention.
  • the isolated execution circuit 115 includes a core execution circuit 205, an access manager 220, and a cache memory manager 230.
  • the core execution unit 205 includes an instruction decoder and execution unit 210 and a translation lookaside buffer (TLB) 218.
  • the instruction decoder and execution unit 210 receives an instruction stream 215 from an instruction fetch unit.
  • the instruction stream 215 includes a number of instructions.
  • the instruction decoder and execution unit 210 decodes the instructions and executes the decoded instructions. These instructions may be at the micro- or macro- level.
  • the instruction decoder and execution unit 210 may be a physical circuit or an abstraction of a process of decoding and execution of instructions. In addition, the instructions may include isolated instructions and non- isolated instructions.
  • the instruction decoder and execution unit 210 generates a virtual address 212 when there is an access transaction.
  • the TLB 218 translates the virtual address 212 into a physical address 99.
  • the TLB 218 includes a cache 219 of the Memory Ownership Page Table (MOPT) 77.
  • the TLB 218 first looks in the cache 219 to find the physical address that matches the virtual address 212 and an associated page table entry. If the physical address is not in the cache 219 the TLB 218 then searches the MOPT 77 itself.
  • the TLB 218 uses the base of the MOPT 221 to search for the physical address. Referring also to Figure IE, starting with base of the MOPT 221 and the page table component 91 of the virtual address 212, the TLB 218 finds the page table entry 93 for the virtual address 212.
  • each page table entry 93 includes the base of the page 95 and an attribute 96 (isolated or non-isolated) for the page.
  • the TLB 218 can find the physical address 99 corresponding to the virtual address. It should be appreciated that the translation of virtual addresses to physical addresses utilizing a TLB is well known in the art.
  • the attribute 96 (isolated or non-isolated) for the page is important in configuring an access transaction for isolated execution.
  • the core execution circuit 205 interfaces with the access manager 220 via control/status information 222, operand 224, and access information 226.
  • the control/status information 222 includes control bits to manipulate various elements in the isolated bus cycle generator 220 and status data from the access manager 220.
  • the operand 224 includes data to be written to and read from the access manager 220.
  • the access information 226 includes address information (e.g., the physical address provided by the TLB 218), read/write, and access type information.
  • the access manager 220 receives and provides the control/status information 222, receives and provides operand 224 information, receives the access information 226 from the core execution circuit 205 as a result of instruction execution, receives a cache access signal 235 (e.g. a cache hit) and an attribute 96 (isolated or non-isolated) from the cache memory manager 230.
  • the access manager 220 also receives an external isolated access signal 278 and a front side bus (FSB) address information signal 228 from another processor in the system.
  • the external isolated access signal 278 is asserted when another processor in the system attempts to access one of the isolated memory areas.
  • the access manager 220 generates an isolated access signal 272, an access grant signal 274, and a processor snoop access signal 276.
  • the isolated access signal 272 may be used to generate an isolated bus cycle 230 sent to devices (e.g., chipsets) external to the processor 110 to indicate that the processor 110 is executing an isolated mode instruction.
  • the processor snoop access signal 276 may be used by other devices or chipsets to determine if a snoop access is a hit or a miss.
  • the isolated access signal 272, the access grant signal 274, and the processor snoop access signal 276 may also be used internally by the processor 110 to control and monitor other isolated or non-isolated activities.
  • the cache memory manager 230 receives the access information 226 from the core execution circuit 205 and generates the cache access signal 235 to the access manager 220.
  • the cache memory manager 230 includes a cache memory 232 to store cache information and other circuits to manage cache transactions as known by one skilled in the art.
  • the cache access signal 235 indicates the result of the cache access.
  • the cache access signal 235 is a cache hit signal that is asserted when there is a cache hit from a cache access.
  • FIG. 2B is a diagram illustrating the access manager shown in Figure 2A according to one embodiment of the invention.
  • the access manager 220 includes a configuration storage 250 and an access checking circuit 270.
  • the access manager 220 exchanges operand 224 information with and receives the access information 226 from the core execution circuit 205 shown in Figure 2A.
  • the operand 224 information includes the attribute 96 (isolated or non-isolated) for the page associated with the physical address 99.
  • the access manager 220 also receives the cache access signal 235 from the cache manager 230 and the external isolated access signal 278 and the FSB address information 228 from another processor as shown in Figure 2A.
  • the access manager 220 further receives an attribute 96 (isolated or non-isolated) from the cache manager 230.
  • the attribute is on a per cache line basis.
  • the access information 226 includes a physical address 99, a read/write (RD/WR#) signal 284 and an access type 286.
  • the access information 226 is generated during an access transaction by the processor 110.
  • the access type 286 indicates a type of access, including a memory reference, an input/output (I/O) reference, and a logical processor access.
  • the logical processor access includes a logical processor entry to an isolated enabled state, and a logical processor withdrawal from an isolated enabled state.
  • the configuration storage 250 contains configuration parameters to configure an access transaction generated by the processor 110.
  • the processor 110 has a normal execution mode and an isolated execution mode.
  • the access transaction has access information.
  • the configuration storage 250 receives the operand 224 information from the instruction decoder and execution unit 210 ( Figure 2A).
  • the configuration storage 250 includes an attribute register for a page 251 and a processor control register 252.
  • the attribute register 251 contains the attribute 96 for the page associated with the physical address set to either isolated or non-isolated.
  • the processor control register 252 contains an execution mode word 253.
  • the execution mode word 253 is asserted when the processor 110 is configured in the isolated execution mode.
  • the execution mode word 253 is a single bit indicating if the processor 110 is in the isolated execution mode.
  • the access checking circuit 270 checks the access transaction using at least one of the configuration parameters (e.g. the execution mode word 253 and the attribute 96) and the access information 226.
  • the access checking circuit 270 generates the processor isolated access signal 272, the access grant signal 274, and the processor snoop access signal 276 using at least one of the parameters in the configuration storage 250, the access information 226 in a transaction generated by the processor 110, and the FSB address information 228.
  • the FSB address information 228 is typically provided by another processor and is snooped on the FSB.
  • the isolated access signal 272 is asserted when the processor 110 is configured in the isolated execution mode.
  • the access grant signal 274 is used to indicate that an access has been granted.
  • the processor snoop access signal 276 is used to determine if an access from another processor results in a hit or a miss.
  • FIG. 3A is a diagram illustrating the access checking circuit 270 according to one embodiment of the invention.
  • the access checking circuit 270 includes a TLB access checking circuit 310 and an FSB snoop checking circuit 330.
  • the TLB access checking circuit 310 receives the attribute 96 and the execution mode word 253 to generate an access grant signal 274.
  • the access grant signal 274 to the isolated area is asserted when the attribute 96 is set to isolated and the execution mode word 253 is asserted indicating that an isolated access is valid or allowed as configured.
  • the TLB access checking circuit 310 performs a logical "Exclusive- Nor" operation. Thus, when a processor requests a physical address of an isolated area, only if the processor is operating in the isolated execution mode and the attribute for the page associated with the physical address is set to isolated, will the access transaction be granted.
  • the FSB snoop checking circuit 330 performs a similar function to the TLB access checking circuit 310.
  • the FSB snoop checking circuit 330 generates the processor snoop access signal 276 by combining the cache access signal 235, the external isolated access signal 278, and the attribute 96.
  • the FSB snoop checking circuit 330 includes a first combiner 342 and a second combiner 344.
  • the first combiner 342 receives the attribute 96 (isolated or non-isolated) for the line to be snooped, from the cache memory manager 230, and the external isolated access signal 278 from another processor doing the snooping.
  • the attribute is on a per cache line basis.
  • the first combiner 342 performs a logical "Exclusive-Nor" operation.
  • the second combiner 344 combines the result of the first combiner 342 with the cache access signal 235 (e.g. cache hit).
  • the second combiner 344 performs a logical AND operation.
  • the FSB snoop checking circuit 330 ensures proper functionality in a multiprocessor system when not all the processors have been initialized for isolated memory area accesses.
  • the X-NOR element 342 ensures that a snoop hit can only occur from a processor that has been allowed for isolated access. If one processor is not yet participating in the isolated memory area accesses, it will not be able to snoop a line out of another processor that is participating in the isolated memory area accesses. Similarly, a processor that has been enabled for isolated accesses will not inadvertently snoop a line out of another processor that has not yet been enabled.
  • the processor snoop access signal 276 for an isolated area is asserted indicating there is an access hit when the cache access signal 235 is asserted indicating there is a cache hit and when the external isolated access signal 278 is asserted and the attribute 96 is set to isolated.
  • Figure 3B is a diagram illustrating the access checking circuit 270 to manage process logical processor operations according to another embodiment of the invention.
  • the access checking circuit 270 includes a logical processor manager 360.
  • a physical processor may have a number of logical processors. Each logical processor may enter or exit a isolated processor state, referred to as a logical processor access. A logical processor access is typically generated when the corresponding logical processor executes an isolated instruction, such as isolated enter (iso_enter) and isolated_exit (iso_exit).
  • the logical processor manager 360 manages a logical processor operation caused by the logical processor access. Essentially, the logical processor manager 360 keeps track of the number of enabled logical processors in the processor.
  • the logical processor manager 360 includes a logical processor register 370, a logical processor state enabler 382, a logical processor updater 380, a minimum detector 374, and a maximum detector 376.
  • the logical processor register 370 store a logical processor count 372 to indicate a number of logical processors currently enabled.
  • the logical processor state enabler 382 enables a logical processor state when the logical processor access is valid.
  • the logical processor updater 380 updates the logical processor count 372 according to the logical processor access.
  • the logical processor updater 380 is enabled by the enabled logical processor state.
  • the logical processor register 370 and the logical processor updater 380 are implemented as an up/down counter with enable.
  • the minimum detector 374 determines if the logical processor count 372 is equal to a minimum logical processor value (e.g., zero).
  • the maximum detector 376 determines if the logical processor count 372 exceeds a maximum logical processor value.
  • the maximum logical processor value is a number indicating the maximum number of logical processors that can be supported by the isolated execution mode in the processor 110.
  • the logical processor updater 380 initializes the logical processor register 370 at system reset.
  • the logical processor updater 380 updates the logical processor count 372 in a first direction (e.g., incrementing) when the access transaction corresponds to the logical processor entry.
  • the logical processor updater 380 updates the logical processor count 372 in a second direction opposite to the first direction (e.g., decrementing) when the access transaction corresponds to the logical processor exit or a logical processor withdrawal.
  • the logical processor manager 360 causes the processor 110 to clear the cache memory 232 ( Figure 2A) by writing it back to main memory and the isolated setting register ( Figure 2A) from all isolated information to restore the initial conditions in these storage elements.
  • the logical processor manager 360 causes the processor 110 to generate a failure or fault condition because the total number of logical processors exceed the maximum number of logical processors that can be supported in the processor.
  • Figure 4 is a flowchart illustrating a process 400 to generate an access grant signal for isolated execution according to one embodiment of the invention.
  • the process 400 distributes pages to multiple isolated memory areas
  • the process 400 asserts the execution mode word in the processor control register to configure the processor in the isolated execution mode (Block 420).
  • the process 400 receives access information from an access transaction from a processor (Block 425).
  • the access information includes a physical address (as provided by the TLB), an attribute (isolated/non-isolated) for the page, and an access type.
  • the process 400 determines if the attribute is set to isolated and the execution mode word is asserted (indicating set to isolated) (Block 430). If not, the process 400 generates a failure or fault condition (Block 435) and is then terminated. Otherwise, the process 400 asserts the access grant signal (Block 440). Then the process 400 is terminated.
  • Figure 5 is a flowchart illustrating a process 500 to manage process logical processor operations for isolated execution according to one embodiment of the invention.
  • the process 500 Upon START, the process 500 initializes the logical processor register when there is no enabled logical processor (Block 510). Then the process 500 executes a logical processor access instruction (e.g., iso_enter, iso_exit). The logical processor access instruction asserts the execution mode word. Next, the process 500 enables the logical processor state (Block 525). Then, the process 500 determines the logical processor access type (Block 530).
  • a logical processor access instruction e.g., iso_enter, iso_exit
  • the logical processor access instruction asserts the execution mode word.
  • the process 500 enables the logical processor state (Block 525). Then, the process 500 determines the logical processor access type (Block 530).
  • the process 500 updates the logical processor count in a first direction (e.g., incrementing) (Block 540). Then, the process 500 determines if the logical processor count exceeds the maximum logical processor value (Block 550). If not, the process 500 goes to block 570. Otherwise, the process 500 generates a failure or fault condition (Block 560) and is then terminated.
  • a first direction e.g., incrementing
  • the process 500 updates the logical processor count in a second direction opposite to the first direction (e.g., decrementing) (Block 545). Then, the process 500 determines if the logical processor count is equal to the minimum value (e.g., zero) (Block 555). If not, the process 500 goes to block 570. Otherwise, the process 500 initializes the cache memory and the isolated setting register from all the isolated information (Block 565).
  • the minimum value e.g., zero
  • the process 500 returns to block 520 to execute a logical processor access instruction. If there is no more logical processor access, the process 500 is terminated.
  • the above description refers to the isolated execution process in the processor 110. Accesses to the multiple isolated memory areas 71, shown in Figure 1C, are further controlled by the MCH 130 ( Figure IF). Referring to Figure IF, the processor 110 views the MCH 130 as an input/output device mapped into an address location. To have accesses to the isolated memory area 70, and particularly the multiple isolated memory areas 71 ( Figure 1C), the processor 110 needs to configure the memory configuration storage in the MCH 130 accordingly.
  • the MCH 130 also includes control functions to allow the processor 110 to access the memory 140 in the multiple non-isolated memory areas 83 ( Figure 1C) as well.
  • the MCH 130 receives signals from the processor 110 via the host bus 120, such as the isolated access signal, or the bus cycle information.
  • the MCH 130 is shown external to the processor 110. However, it is possible for the MCH 130 to be included inside the processor 110. In this case, a write cycle to the registers in the MCH 130 is externalized to allow any external cache to participate for cache coherency.
  • the access controller in the MCH 130 performs a similar function as the access checking circuit 270 shown in Figure 3A. By maintaining access consistency in both processor 110 and MCH 130, accessing memory can be tightly controlled.
  • the access controller in the MCH 130 determines if an access transaction from the processor 110 is valid. If it is, the access controller returns an access grant signal to allow completion of the access transaction. Otherwise, a failure or fault condition is generated.
  • the access controller in the MCH 130 also protects any intentional or accidental writing to its own configuration and control storage. Since the MCH 130 is directly interfaced to the memoiy 140, the access controller also provides for the initializing of the contents of the isolated memory areas and its own internal storage upon reset.
  • FIG 6 is a diagram illustrating the isolated area access controller 135 in the memory controller hub (MCH) 130 shown in Figure IF according to one embodiment of the invention.
  • the access controller 135 includes a configuration storage 610, a configuration controller 640, and an MCH access checking circuit 810.
  • the configuration storage 610 configures an access transaction generated by the processor 110 shown in Figure IF.
  • the processor 110 has a normal execution mode and an isolated execution mode.
  • the access transaction has access information 660.
  • the access information 660 is carried over the host bus 120 ( Figure IF) and includes address information and an isolated access state.
  • the address information is represented by a physical address 662.
  • the isolated access state is represented by the isolated access signal 664.
  • the isolated access signal 664 is essentially equivalent to the processor isolated access signal 272 shown in Figure 2A.
  • the isolated access signal 664 is asserted when the processor 110 generates a valid reference to one of the multiple isolated memory areas 71 (shown in Figure 1C).
  • the configuration storage 610 includes a cache 660 of the Memory Ownership Page Table (MOPT) 77.
  • the configuration storage 610 performs a look up for the physical address 662 in the cache 660 to find the physical address and an associated page table entry. If the physical address is not in the cache 219 the configuration storage 610 then performs a look up for the physical address 662 in the MOPT 77 ( Figure IE) itself.
  • the configuration storage 610 uses the base of the MOPT 221 to search for the physical address 662 in the MOPT 77. Referring also to Figure IE, starting with base of the MOPT 221 the configuration storage 610 performs a look up into the MOPT 77 and finds the page table entry 93 associated with the physical address 662.
  • the configuration storage can search the physical addresses of the pages 98 to locate the page table entry 93 associated with the physical address.
  • Each page table entry 93 includes an attribute 96 (isolated or non-isolated) for the page associated with the physical address that is important for configuring an access transaction for the MCH 130. It should be appreciated that the performing a look up into a page table to locate a physical address and an associated page table entry is well known in the art and that other methods of performing the look up are well within the knowledge of one skilled in the art.
  • the configuration storage 250 also contains configuration parameters to configure an access transaction generated by the MCH 130.
  • the configuration storage includes an attribute register 611 that contains the attribute 96 for the page associated with the physical address set to either isolated or non-isolated found by the look up. As discussed earlier, the isolated memory area 71 is only accessible to the processor 110 in the isolated execution mode.
  • the configuration controller 640 controls access to the configuration storage 610 and provides some control functions to the memory 140.
  • the MCH access checking circuit 810 generates an access grant signal 652 using the access information 660, the attribute 96, the isolated access signal 664, and the isolated memory priority 736.
  • the access grant signal 652 indicates if the access transaction is valid.
  • the access grant signal 652 may be used by the processor 110 or other chipsets or peripheral devices to determine if an attempt to access the isolated memory area 71 is granted.
  • Figure 7 is a diagram illustrating the MCH access checking circuit 810 shown in Figure 6 according to one embodiment of the invention.
  • the MCH access checking circuit 810 generates an access grant signal 652 based upon the attribute 96 and the isolated access signal 664.
  • the access grant signal 652 indicates if the access transaction is valid.
  • the MCH access checking circuit 810 receives the attribute 96 and the isolated access signal 664 to generate an access grant signal 652.
  • the access grant signal 652 to the isolated area is asserted when the attribute 96 is set to isolated and the isolated access signal 664 is asserted indicating that an isolated access is valid or allowed as configured.
  • the MCH access checking circuit 810 performs a logical "Exclusive-Nor" operation. Thus, when a processor requests a physical address of an isolated area, only if the processor is operating in the isolated execution mode and the attribute for the page associated with the physical address is set to isolated, will the access transaction be granted.
  • Figure 8 is a flowchart illustrating a process 800 to generate an access grant signal for isolated execution for an MCH according to one embodiment of the invention.
  • the process 800 configures an access transaction for the MCH (Block 810). Then, process 800 receives access information from an access transaction (Block 820). The access information includes a physical address, an isolated access signal, and an attribute (isolated/non-isolated) for the page. Next, the process 800 determines if the attribute is set to isolated and if the isolated access signal is asserted (Block 830). If not, the process 800 generates a failure or fault condition (Block 835) and is then terminated. Otherwise, the process 800 asserts the access grant signal (Block 840). Then the process 800 is terminated.

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Abstract

La présente invention concerne un procédé, un appareil et un système permettant de commander des accès mémoire à de multiples zones de mémoire isolées dans un environnement d'exécution isolé. On utilise un gestionnaire de page pour distribuer une pluralité de pages à une pluralité de zones différentes d'une mémoire, respectivement. La mémoire est divisée en zones non isolées et en zones isolées. Le gestionnaire de page est localisé dans une zone isolée de mémoire. De plus, une table de pages propriétaire de mémoire décrit chaque page de mémoire et cette table est également localisée dans une zone isolée de mémoire. Le gestionnaire de page affecte un attribut isolé à une page si cette page est distribuée à une zone isolée de mémoire. D'autre part, ce gestionnaire de page affecte un attribut non isolé à une page si cette page est distribuée à une zone non isolée de mémoire. La table de pages propriétaire de mémoire enregistre l'attribut de chaque page. Dans un mode de réalisation de l'invention, un processeur possédant un mode d'exécution normal et un mode d'exécution isolé génère une transaction d'accès. Cette transaction d'accès est configurée grâce à un stockage de configurations qui contient des paramètres de configuration relatifs à une page et des informations d'accès. Un circuit de vérification d'accès couplé aux paramètres de configuration et aux informations d'accès génère un signal d'octroi d'accès si la transaction d'accès est valable.
PCT/US2001/022027 2000-07-18 2001-07-13 Commande d'acces a de multiples memoires isolees dans un environnement d'execution isole WO2002006929A2 (fr)

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DE10196440T DE10196440B4 (de) 2000-07-18 2001-07-13 Steuern des Zugriffs auf mehrere isolierte Speicher in einer isolierten Ausführungsumgebung
JP2002512776A JP3982687B2 (ja) 2000-07-18 2001-07-13 分離実行環境での複数の分離メモリへのアクセスの制御
AU2001271996A AU2001271996A1 (en) 2000-07-18 2001-07-13 Controlling access to multiple isolated memories in an isolated execution environment
GB0303644A GB2381626B (en) 2000-07-18 2001-07-13 Controlling access to multiple isolated memories in an isolated execution environment
HK03104417.4A HK1052237B (zh) 2000-07-18 2003-06-19 在一個分離執行環境中控制多重分離記憶體的存取

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US09/618,738 US6678825B1 (en) 2000-03-31 2000-07-18 Controlling access to multiple isolated memories in an isolated execution environment
US09/618,738 2000-07-18

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AU2001271996A1 (en) 2002-01-30
CN1459059A (zh) 2003-11-26
JP2004504663A (ja) 2004-02-12
DE10196440T5 (de) 2004-04-29
JP3982687B2 (ja) 2007-09-26
GB0303644D0 (en) 2003-03-19
CN1252597C (zh) 2006-04-19
HK1052237A1 (en) 2003-09-05
GB2381626A (en) 2003-05-07
HK1052237B (zh) 2005-06-03
WO2002006929A3 (en) 2002-04-25
TW526416B (en) 2003-04-01
DE10196440B4 (de) 2006-03-23
GB2381626B (en) 2005-02-09

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