WO2002003559A1

WO2002003559A1 - Analog interface in systems using time-division-duplex

Info

Publication number: WO2002003559A1
Application number: PCT/EP2001/007097
Authority: WO
Inventors: Antonius Martinus Jacobus Daanen; Mark John Naylor
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2000-06-30
Filing date: 2001-06-22
Publication date: 2002-01-10
Also published as: TW546940B

Abstract

DECT terminal using a DAC for performing a digital to analog conversion in the transmit path of a DECT terminal, and using the same DAC in a successive approximation analog to digital converter in the receive path. The invention concerns a Radio telephone using Time Division Duplex to separate receive and transmit data, the reception using a receive path and the transmission using a transmit path, the telephone comprising a same digital to analog converter for performing a digital to analog conversion in the transmit path and for performing an analog to digital conversion by successive approximations in the receive path. Application / Use: DECT, US-ISM and PHS terminals.

Description

Analog interface in systems using time-division-duplex

FIELD OF THE INVENTION

The invention relates to an analog interface in systems using Time-Division Duplex, i.e. the transmission and reception are not performed at the same time. More particularly, the invention concerns a possible architecture for the Radio Frequency (RF) analog interface on base-band chips for use in cordless and cellular telephony applications. It uses the Time-Division-Duplex (TDD) technique to separate, receive and transmit data. DECT (Digital Enhanced Cordless Telephone) and PHS (Personal Handly System, which is used in Japan) are examples of standards using TDD.

BACKGROUND ART

In known systems, the CMOS base-band circuit of a telecommunication apparatus comprises separate analog blocks dedicated to the receive part and the transmit part respectively. The transmit hardware is not used during the receive time of TDD, and vice versa.

SUMMARY OF THE INVENTION

It is an object of the invention to provide a low cost radio telephone terminal. An advantage of the invention is that it simplifies and reduces analog functions on the CMOS chip by shifting this functionality into digital hardware or software. The use of standard and "simple" analog blocks eases design, shrinks process and reduces testing time.

In accordance with the invention, it is provided a radio telephone wherein which most of the hardware is used during both receive and transmit times. In this respect, a radio telephone according to the invention, using TDD to separate, receive and transmit data is described. Using a receive path in reception and using a transmit path in transmission, the telephone comprises a same digital to analog converter DAC for performing a digital to analog conversion in the transmit path and for performing an analog to digital conversion by successive approximations in the receive path. BRIEF DESCRIPTION OF THE DRAWINGS

The invention and additional features, which may be optionally used to implement the invention, are apparent from and will be elucidated with reference to the drawings described hereinafter.

Fig. 1 is a block diagram illustrating a telecommunication terminal.

Figs. 2 is a block diagram illustrating a telecommunication terminal according to the invention.

Fig. 3 is a block diagram illustrating a telecommunication terminal according to a preferred embodiment of the invention.

DETAILED DESCRIPTION OF THE DRAWINGS

The invention is described both in DECT and US-ISM applications (United States - Industrial Scientific Medical : this refers to the 900MHz Industrial, Scientific & Medical frequency band as allocated in the US). But the invention is applicable to any TDD standard, such as DECT, PHS, PACS (Personal Access Communications System ), ISM, BlueTooth, etc.

In TDD communication systems, the receive and transmit data is compressed in time, allowing to access the channel in each direction separately, such that the receive data does not interfere with the transmit data. Normally, a terminal hardware at either end of the channel has a receive part and a transmit part, which are physically different pieces of hardware. Given the separate use in time of the hardware, due to TDD, it is proposed, in accordance with the invention, to re-use parts of the hardware for both receive and transmit times. The invention describes how the analog blocks on a CMOS chip, being in the receive and transmit paths, can be merged, in order to save chip area and at least one Analog-to- Digital Converter (ADC).

The position of the analog hardware that is to be merged is located in the receive and transmit part on the CMOS base-band circuit, whose place within a telecommunication device is depicted with reference numeral 14 in Fig. 1. The CMOS baseband circuit comprises a base-band reception bloc B-RX, a base-band transmission bloc B- TX and a Data processing and Voice coding / decoding bloc DPVC. The telecommunication terminal comprises a radio part 12, which is connected to an antenna 16 and to the base-band circuit 14. The base-band-circuit 14 receives speech data from a microphone 19 and delivers speech data to the user via an earpiece / earphone 18. The following description is based on the hardware realization that can be used both in DECT and US-ISM. However the same principle can be used in PHS, etc.

Fig. 2 shows a very simple CMOS base-band circuit according to the invention. It comprises a comparator 21, a DAC (Digital to Analog converter) circuit 22, two switches 23 and 24 and a Data Processing and Voice Coding / decoding bloc DPVC. A switch 23 is connected to an input R_DATA of the base-band circuit and to the + input of the comparator 21. The other switch 24 is connected to an output T_DATA of the base-band circuit, on the one hand, and to the output of the DAC 22 and the minus input of the comparator 21 on the other hand. The output of the comparator is connected to an input of the DPVC. The output of the DPVC is connected to the input of the DAC.

It is assumed that (in DECT, US-ISM and any other TDD cordless/wireless telephone system) the receive and transmit functions never do overlap. So the same hardware can be used both for reception and transmission functions. During transmission slots the DAC is used as a real DAC and during reception slots, the DAC with the comparator 21 form an ADC by successive approximations, controlled by a digital logic control block, in the DPVC.

The switches 23, 24 are used to decouple the DAC output changes during an AD (Analog to Digital) conversion from the connected radio circuitry and to multiplex different signals to the ADC (Analog to Digital Conversion) comparator inputs. The signal R_DATA represents the received data from the sender. This data is typically speech data that has gone through ADPCM (Adaptive Differential Pulse Code Modulation) conversion, error coding, interleaving and scrambling. The signal at this point is an analogue signal of about lOOmv from peak to peak in the worst case. It needs to be squared up to digital levels for decoding by the BMP. The signal T_DATA represents the data transmitted towards the user. At this point the signal is an analog signal, which has been converted from digital to analog by the DAC 22.

Fig.3 shows the CMOS base-band circuit 14 in a preferred embodiment. It includes four analog blocs : two identical DACs 32, 35 and two identical comparators 31, 36. A few switches are used to decouple the DAC output changes during an ADC conversion from the connected radio circuitry or to multiplex different signals to the ADC comparator inputs.

The preferred solution uses two 8-bit DACs capable of running at 13.824 MHz, and two comparators. During transmit slots the DACs are used as I/Q (In Phase / in Quadrature) modulators (e.g. for use in US-ISM systems) or GFSK (Gaussian Frequency Shift Keying) modulators (e.g. for use in DECT systems), and during receive slots, the DACs with the comparators form two successive approximation ADCs. These ADCs replace the known solution comprising a bit slicer comparator and filter, an analog block doing both Fast Antenna Diversity and RSSI peak detection and hold, followed by an AD conversion.

A digital control logic block DRFL + BMP is provided to perform two different functions. It may actually comprise two blocks. One of which is closely integrated with the analogue circuits and is directly responsible for controlling the analogue block. It is called the DRFL (Digital Radio Frequency Logic). The second block is called the BMP (Burst Mode Processor). The BMP determines the exact timing of the system. It also creates the blocks to be sent. It realizes the bit interleaving, coding and scrambling. It also recovers the incoming data.

The BMP is controlled by an advanced RISC (Reduced Instruction Set Computer) machine microcontroller ARM. The BMP is itself to a degree programmable. As it is required to do the exact bit timing it is not possible to have such a function under software control. The BMP is a kind of programmable state machine that is first given reference values in order to be set running.

The BMP does not have exact knowledge of the workings of the analogue part. A separate block is required to this end. The BMP drives the DRFL and the DRFL drives the analogue components.

A REAL DSP is used for voice processing functions. It performs the ADPCM, echo cancel and other important functions, but does not determine the timing for the RF.

The ARM is the master for the whole system, it "initiates" all of the functions carried out by the various blocks, but does not carry out these functions itself. The BMP is useful, as the ARM is not fast enough to give exact bit timing. The REAL DSP is useful, as the ARM is not powerful enough to carry out all the speech-processing algorithms and also the system control functions.

With the help of the BMP, the ARM does set up calls, end calls and performs hand over between base stations. All user functions, i.e. dialing, using the keypad and the display are carried out through the ARM.

The R_DATA signal may contain not exclusively speech data. It can also contain control data which are transmitted between a handset and a base station ; handshaking essentially. DECT and other TDD system can also carry digital data for modem applications. It is required (in a DECT system at least) to do an RSSI (Received Signal Strength Indication) measurement to determine what sort of activity there is on the RF channels at any one time, i.e. if a channel is blocked or used by another, or is quiet (i.e. has no activity). The system sweeps all available RF channels (in frequency and time) to determine the amount of activity. The RSSI signal thus represents a measure of the RF channel activity. The RSSI is a "raw" power measurement. The RSSI signal is an analogue signal passed by the RF chips. An ADC is needed to this end. In the base-band an ADC conversion takes place and the data is digitized. The ADC is created from the I/Q DAC and one of its buffers is used as a comparator. As explained above, bit correlation is done in the BMP. The output of the bit slicer goes directly to the BMP. The bit slicer is needed as the input is a small analogue signal and the BMP is a digital circuit.

The outputs of the I/Q modulator go to the RF chip where the signals are taken up to a higher frequency. Functionally the carrier to 1.9GHz multiplies them, then they are added together and sent to the power amplifier, which is in turn connected to the antenna. The circuit could be simplified a little if it was destined to DECT only. For example, DECT systems do not require an I/Q modulator. Typically a DECT system has a single output. Other systems may also allow a simplification over DECT. An RSSI is required by DECT. In other systems it is very useful, but not essential. With this concept the following functions can be realized :

• US-ISM transmit slot: Both DACs 32, 35 output the I and Q output signals generated in the digital block. The bit rate is 0.1152 Mb/s and the DAC conversion rate 1.3824 Msamples/s. The two comparators 31, 36 are not used.

• DECT transmit slot: Only one DAC output is used for GFSK modulation. The bit rate is 1.152 Mb/s and the DAC conversion rate is 13.824 Msamples/s. The two comparators are not used.

• Receive slot: The DACs are used in a successive approximation ADC together with the comparator. One ADC is used in the receive data path R_DATA, the other ADC handles the RSSI signal for Fast Antenna Diversity followed by Peak Detection. - Receive slot R DATA: The ADC converts the analog signal and presents the digital signal to a bit correlator, which is done in the BMP (hardware or software). This bit correlator can perform the bit slicing function and extract values "1" and "0", but it can also determine other data stream parameters like DC value, long term quality, etc. With this information the receiver performance could be improved. The bit frequency is 0.1152MHz in US-ISM and 1.152MHz in DECT. At least 2 samples per period must be taken (Nyquist), so with a clock rate of 13.824 MHz there are in DECT 12 DAC conversions possible. This means that a successive approximation resolution of 6 bits can be reached. However, exactly 2 samples are not enough, as it is possible that only the zero-crossings are sampled for e.g. a preamble signal. Therefore as least 3 samples will be taken, and the resolution decreases to 4 bits. For US-ISM the accuracy can be 8 bits at 15 ADC conversions per bit period corresponding to a bit bit frequency of 0.1152MHz. If the bit correlation function is not used/needed then the DAC can be used to generate a DC level as the slice_control circuit does now with a switchable RC filter.

- Receive slot R DATA with undersampling: Another possibility that can be used by the RF interface is undersampling of the receive data signal. Sampling of signals, which have a frequency greater than one half of the ADC conversion rate is possible under an extended/generalized version of the Nyquist Theorem. This is where the signal of interest, although at a higher frequency, is band limited to less than half the ADC sampling rate. In this application the ADC with in addition a sample and hold amplifier in front may sample a first intermediate frequency (first IF). Signal processing in a DSP or microcontroller may later process this sampled data and re- construct the band-limited first IF signal. For an US-ISM solution with a data rate of

115.2 Kbit/s and a typical first IF of 100MHz where the RF signal was band limited to 100MHz + /-57kHz a sampling rate of 230.4kHz would give fifteen 8-bit samples per period, similar to the description in "receive slot R_DATA" above.

- Receive slot RSSI: For Fast Antenna Diversity during the (eventually prolonged) preamble the ADC could make one or more conversions per bit-time (for DECT, eight 13.824MHz clocks per conversion for 8 bits resolution, thus 3 ADC conversions (24/13.824M) fit into 2 bit-times (2/1.152M)). The digital values can than be handled in the digital logic block (e.g. software), to choose the better antenna. When the Fast Antenna Diversity is ready, the ADC can be used for RSSI Peak Detection during the rest of the receive slot. For DECT the ADC must sample faster than the required filtering with a filter time constant tau of lOus minimum. The DAC and comparator must not be a successive approximation ADC anymore, but can be of the track-and- hold type, thereby implementing a Peak Detection ADC. In this case a ramp with 8 bits resolution must be made within 3 times tau (for settling to better than 99%) thus the minimum DAC conversion rate is 2 =256 conversions per 3*10us, which is 8.5Msamples/s. - Inactive slot (no receive, no transmit : Of course it is possible to use the same ADC function for additional analog AD conversions (temperature measurement, battery measurement, charge current measurement, etc.) on pins SIGNAL__1 or SIGNAL_2.

Claims

CLAIMS:

1. A radio telephone using Time Division Duplex to separate, receive and transmit data, the reception using a receive path and the transmission using a transmit path, the telephone comprising a same digital to analog converter DAC for performing a digital to analog conversion in the transmit path and for performing an analog to digital conversion by successive approximations in the receive path.

2. A radio telephone as claimed in claim 1, comprising a comparator for use in the analog to digital conversion by successive approximations.

3. A radio telephone as claimed in claim 2, comprising switching means for switching from the receive path to the transmit path.

4. A radio telephone as claimed in claim 2, comprising a digital control logic block for controlling the successive approximation analog to digital conversion.

5. A base-band circuit for use in a telecommunication apparatus using Time Division Duplex to separate, receive and transmit data, the reception using a receive path and the transmission using a transmit path, the circuit comprising a same digital to analog converter DAC for performing a digital to analog conversion in the transmit path and for performing an analog to digital conversion by successive approximations in the receive path.

6. A base-band circuit as claimed in claim 5, comprising a comparator for use in the analog to digital conversion by successive approximations.

7. A base-band circuit as claimed in claim 6, comprising switching means for switching from the receive path to the transmit path.

8. A base-band circuit as claimed in claim 6, comprising a digital control logic block for controlling the successive approximation analog to digital conversion.