WO2002002842A2

WO2002002842A2 - Low temperature cvd bst deposition

Info

Publication number: WO2002002842A2
Application number: PCT/US2001/020223
Authority: WO
Inventors: Xioliang Jin; Lee Luo; Jun Zhao; Charles Dornfest; Xian Zhi Tao; Shreyas Kher; Annabel Nickles; Sandeep Nijhavian; Yaxin Wang
Original assignee: Applied Materials, Inc.
Priority date: 2000-06-29
Filing date: 2001-06-25
Publication date: 2002-01-10
Also published as: WO2002002842A3

Abstract

A process and apparatus is provided for the vaporization of liquid precursors and deposition of a layer at a temperature of less than or equal to about 480 °C on a suitable substrate. Particularly contemplated is a process for CVD deposition of a metal-oxide layer, such as a barium, strontium, titanium oxide (BST) layer, on a silicon substrate to make integrated circuit capacitors useful in high capacity dynamic memory modules. The process allows for depositing smooth, conformal BST layers having high dielectric constants and consistent layer compositions. In one aspect of the invention, a method is provided to deposit BST layers by introducing a precursor reactant gas comprising barium, strontium, and titanium, to a processing chamber, introducing an oxidizing gas to the processing chamber, and reacting the precursor reactant gas in the presence of the oxidizing gas at a substrate temperature of less than or equal to about 480 °C to deposit the oxide layer. The oxide layer may be further annealed to recrystallize the layer to improve dielectric properties and reduce leakage current.

Description

LOW TEMPERATURE CVD BST DEPOSITION

BACKGROUND OF THE INVENTION

This application is a continuation-in-part of co-pending U.S. Patent Application Serial No. 09/052,766, which was filed March 31, 1999. Field of the Invention The invention relates to a process for the vaporization of liquid precursors and deposition of a film on a substrate. Particularly contemplated is a process for the deposition of a metal-oxide film, such as a barium strontium titanate (BST) film, on a substrate to fabricate capacitors useful in high capacity dynamic memory modules. Background of the Invention Dynamic random-access memory (DRAM) integrated circuits are commonly used for storing data in a digital computer. Currently available DRAMs may contain over 16 million memory cells fabricated on a single silicon chip, and each memory cell generally comprises a single transistor connected to a micron or sub-micron sized capacitor. In operation, each capacitor may be individually charged or discharged in order to "store" one bit of information. A DRAM is dynamic in the sense that charged memory cells must be refreshed or recharged periodically to maintain data integrity, otherwise, charged memory cells may quickly discharge through leakage.

The increasing density of integrated circuits (ICs) is driving the need for materials with high dielectric constants to be used in electrical devices such as capacitors for forming 256 Mbit and 1 Gbit DRAMs. To facilitate construction of 64 Mbit, 256 Mbit, 1 Gbit, and larger DRAMs with correspondingly smaller memory cells, capacitor structures and materials which can store the necessary charge in less chip space are needed. One of the most promising avenues of research is in the area of high dielectric constant (HDC) materials. Capacitors containing high-dielectric-constant materials usually have much larger capacitance densities than the standard SiO2-Si3N4-SiO2 stack capacitors. Thus, HDC materials are becoming the choice of materials for use in IC fabrication.

One high dielectric constant material of increasing interest for use in ultra large scale integrated (ULSI) DRAMs is perovskite, Ba . _x]Sr_[x]TiO₃ (BST). Deposition techniques used in the past to deposit BST include RF magnetron sputtering, laser ablation, sol-gel processing, and chemical vapor deposition (CVD) of metal organic materials.

CVD is a particularly attractive method for forming BST layers because it is readily scaled up to production runs and because the electronics industry has wide experience and an established equipment base in the use of CVD technology which can be applied to new CVD processes. In general, because of the control of key variables, such as stoichiometry and film thickness, the coating of a wide variety of substrate geometries is possible with CVD. Forming thin BST films by CVD will permit the integration of BST materials into existing device production technologies. In the practice of CVD, a source reagent vapor mixture, which may comprise one or more precursor reagents in admixture with oxidant and/or carrier species, is delivered to a CVD locus, for CVD of selected component(s) of the precursor reagent(s) on a substrate.

If the BST material is provided from a liquid source, the CVD process generally entails atomizing a BST compound, vaporizing the atomized BST compound, depositing the vaporized BST compound on a heated substrate, and annealing the deposited film. This process requires control over the liquid precursors and gases from introduction from an ampoule into a liquid delivery system through vaporization and ultimately to deposition on the surface of the substrate. The goal is to achieve a repeatable process which deposits a film of uniform thickness in a controlled temperature and pressure environment. The goal has not been satisfactorily achieved because the precursors are difficult to process and the deposition equipment requires a complex design.

Specifically, in order to form a thin film having a high dielectric constant, the film must have a crystal structure of the perovskite type which requires a film composition having a substantially stoichiometric composition, i.e., within about 10% of the stoichiometric composition. Thus, the stoichiometry of the deposited film in the CVD system typically must be rigorously controlled for the manufacture of thin film layers having the desired composition and uniform thickness. If the deposited film deviates from the desired stoichiometry or thickness uniformity requirements, the resulting device, such as the DRAM, may be deficient or even unsuitable for its intended purpose. One avenue for depositing a film having high dielectric constants, such as BST, is to control the film composition by changing the precursor source or sources. However, controlling the composition of the deposited BST film by changing the proportions of the precursors is not very practical, because it would be necessary to provide a separate source for each precursor component or the processing may have to be stopped to replace the precursor source each time a change in composition is desired. Additionally, a repeatable process would be difficult to achieve if the composition of the deposited BST film is highly variable. Thus, much effort has been devoted to understanding the effect on the composition of the deposited film when processing conditions other than precursor source composition are changed.

Temperature is one processing condition that has been observed to affect BST film formation and to affect the characteristics of the film's surface. At higher temperatures (i.e. > 480°C) the gas phase reaction of the precursors is increased, thus, reducing the amount of raw material reaching the surface of the substrate and changing the composition of the deposited material. The deposition of BST material on the substrate surface appears to be limited by the mass transport conditions where the raw materials react as soon as they reach the surface without expanding over the surface of the substrate. Although deposition at such high temperatures provides excellent control of the amount of BST introduced to the CVD system, this type of deposition may lead to a film surface having irregular smoothness, variable film composition, and adversely affects the capacitance density of the deposited film. Additionally, at higher temperatures the thermal budgets of some processes and materials, such as titanium nitride (TiN), can be reached or exceeded, thereby limiting the application of the use of BST films. Higher operating temperatures have also been observed to increase operating and maintenance costs.

Therefore, there is a need for a deposition process which can deposit BST precursors as an oxide film having a substantially stoichiometric composition, high capacitance, a smooth film surface, with reduced leakage current, and which may be regularly and reproducibly formed on a substrate. Summary of the Invention

A method is provided for depositing BST and other materials which method includes vaporization at reduced processing temperatures. The method allows for depositing conformal, smooth, and high capacitance layers having a substantially stoichiometric composition, a high degree of crystallinity, and reduced leakage current from vaporized precursors. In one aspect, the invention provides a method for depositing a metal oxide layer, comprising introducing one or more precursors comprising barium, strontium, and titanium, to a processing chamber, and oxidizing the one or more precursors at a substrate temperature of less than or equal to about 480°C to deposit the oxide layer. The metal oxide layer is a BST layer having a titanium concentration of between about 50 mol% and about 53 mol%. The metal oxide layer may be further annealed to recrystallize the layer, thereby reducing leakage current.

In another aspect of the invention, a method for forming a semi-conductor device using a metal oxide layer is provided. The method comprises depositing a first electrode, depositing a metal oxide layer on the first electrode, and then depositing a second electrode on the metal oxide layer. The metal oxide layer is deposited by introducing one or more precursors comprising barium, strontium, and titanium, to a processing chamber, and oxidizing the one or more precursors at a substrate temperature of less than or equal to about 480°C to deposit the metal oxide layer. The substrate may be annealed after depositing the metal oxide layer or after depositing the second electrode to improve the crystallinity of the metal oxide layer.

A BST metal oxide layer is deposited from a precursor reactant gas comprising between about 2.5 mol% and about 15 mol% barium (Ba), between about 2.5 mol% and about 15 mol% strontium (Sr), and between about 70 mol% and about 95 mol% titanium (Ti). The first and second electrodes comprise a material selected from the group of platinum, ruthenium, ruthenium oxide, iridium, iridium oxide, and combinations thereof, and may be deposited by chemical vapor deposition or physical vapor deposition. Brief Description of the Figures Figure 1 is a cross sectional view of a chamber for depositing a metal oxide layer;

Figure 2 is a top view of a lid for the chamber of Figure 1;

Figure 3 is a schematic of a liquid delivery system;

Figure 4 is a perspective view of a zero dead volume valve;

Figure 5 is a cross sectional view of a zero dead volume valve; Figure 6 is cross sectional view of a PVD chamber;

Figures 7-8 are graphical representations of characteristics of a preferred CVD BST 200 mm process;

Figure 9 is a schematic cross section view of one embodiment of a DRAM device having a "cup" structure with transistor disposed below the capacitor; and Figure 10 is a cross sectional view of another embodiment of a DRAM device having a trench capacitor. Detailed Description of the Preferred Embodiment

Exemplary metal-oxide layers which can be deposited using the process of the invention may include tantalum pentoxide (Ta₂O₅), zirconate titanate (ZrxTiyOz), strontium titanate (SrTiO₃), barium strontium titanate (BST), lead zirconate titanate (PZT), lanthanum-doped PZT, bismuth titanate (Bi₄Ti₃O|₂), barium titanate (BaTiO₃), or the like. Other materials which can be deposited include those materials having a narrow temperature range between vaporization and decomposition. The process of the invention also has particular application with other liquid precursors which are volatile as well as materials comprising copper.

Substrates used in the present invention include primarily P-type and N-type silicon substrates. Depending on the particular process chemistry and desired end product, other substrate materials may be used, including other semiconductors, such as GaAs, InP, Si/Ge, SiC, and ceramics. Devices that can be made with the present system include, but are not limited to, 64Mbit, 256Mbit, 1Gbit and 4Gbit DRAMs.

While the process of the invention can be practiced using a wide variety of CVD equipment, the following description provides an example of equipment that can be used to successfully deposit a BST layer on a substrate according to a process of the invention. A detailed description of the equipment briefly described below is provided in co-pending U.S. Patent Application Serial No. 08/927,700, entitled "Vaporization and Deposition Apparatus and Process," filed September 11, 1997, hereby incorporated by reference in its entirety to the extent not inconsistent with the invention. The BST Deposition Chamber

Figure 1 is a cross sectional view of one embodiment of a deposition chamber showing the chamber body 12 supporting a heated lid assembly 14. The chamber body 12 defines an inner annular processing region 20 defined on the perimeter by an inner wall 22. A chamber liner 28 is preferably disposed adjacent the inner wall 22 of the chamber to provide a removable surface within the chamber which can be easily cleaned and/or replaced. A substrate support member 24 extends through the bottom of the chamber and defines the lower end of the processing region 20. A gas distribution plate 26 mounted on the lid forms the upper limit of the processing region 20. The chamber body 12 and the lid assembly 14 are preferably made of a rigid material such as aluminum, stainless steel or combinations thereof. The chamber body 12 also defines a pumping port for purging the remains of the deposition vapor once it has been delivered over the substrate.

The substrate support member 24 may comprise a metal, such as aluminum, with a resistive heating element (not shown) attached thereto or embedded therein. In an alternative embodiment, the support member 24 may comprise a ceramic block and embedded ground plate which generates heat when subjected to RF energy emitted by an adjacent electrode. A suitable substrate support member and related lift assembly is shown and described in co-pending U.S. Patent Application No. 08/892,612, entitled "Self Aligning Lift Mechanism," filed on July 14, 1997, and is incorporated herein by reference to the extent not inconsistent with the invention. This substrate support member is available from Applied Materials, Inc. of Santa Clara, California under the model name CxZ Heater.

The substrate support member 24 generally is movable up and down on a central elevator shaft 30 to move a substrate between a deposition position adjacent the gas distribution plate 26 and a substrate insertion/removal position below a slit valve formed through the chamber body 12. The entry point of the shaft 30 into the chamber is sealed with a collapsible bellows (not shown). The substrate is lifted from or placed on a robot blade by a set of lifting pins 32 slidably retained in a set of four passageways 34 extending through the substrate support member 24. Directly below each of the pins 32 is a lifting plate 36 which moves the pins 32 vertically within the chamber to allow a substrate to be lifted off or placed on a robot blade (not shown) which is moved into the chamber through the slit valve opening (not shown).

The chamber body 12 defines one or more passages 38 for receiving a heated gas delivery feedthrough 40 having an inlet 42 and an outlet 44 to deliver one or more precursor gases into the gas distribution plate 26 mounted on the lid assembly 14. The passage 38 defines an upper and a lower end of differing diameters to form a shoulder 58 where the upper and lower ends meet. The gas outlet 44 is fluidically connected to a mixing gas manifold 46 which includes at least a first gas passage 48 to deliver a gas(es) into the gas distribution plate 26. An O-ring seal 50, preferably made of Teflon® polymer with a stainless steel c-spring, is located around the outlet 44 on the upper chamber wall to provide a sealing connection between the gas delivery feedthrough 40 and the gas manifold 46.

Figure 2 is a top view of a lid assembly showing the mixing gas manifold in phantom. One or more oxidizer gas passages 52, similar to passage 38, are also formed in the chamber body 12 adjacent the passage 38 for receiving an oxidizer gas delivery feedthrough which can be heated if desired to deliver one or more oxidizer gases through the chamber wall to the mixing gas manifold 46. A gas passage 54 is formed in the mixing gas manifold 46 to deliver the oxidizer gas to a mixing point 56 located in the gas manifold adjacent the entry port into the gas distribution plate 26. A restrictive passage 37 connects the end of the oxidizer gas passage 54 to the end of the vaporized gas passage 48 to provide high velocity delivery as well as mixing of the gas mixture upstream from the gas distribution plate 26. Liquid Delivery System

Figure 3 is a schematic view showing a liquid delivery system 200 of the present invention. The liquid delivery system generally includes a liquid precursor module 202, a solvent module 204, and a vaporizer module 206. In one embodiment, the liquid precursor module 202 includes two pressurized ampoules 208, 210 and a liquid delivery line 212 connected to each ampoule. Valves are disposed along the length of the liquid delivery lines to control flow of liquid from the ampoules to a mixing port and then into the vaporizer. Preferably, zero dead volume valves, which are described below, are used to prevent collection of precursor therein which can compromise the valves as well as negatively affect process stabilization and/or repeatability. The zero dead volume valves enable rapid flushing of precursor from the lines using solvent. Solvent is plumbed to the liquid delivery line 212 to flush the system during maintenance. Additionally, a purge gas line is plumbed to the liquid delivery line to rapidly purge solvent from the line so that the system, including the ampoules, valves and/or LFCs, can be prepared for maintenance in ten (10) to thirty (30) minutes. The valving is designed so that when necessary, solvent can be introduced into the liquid delivery line upstream form the mixing port to flush the line through a bypass line 218 and out through a recovery system which includes a cold trap and exhaust manifold.

The ampoules 208, 210 are designed to deliver the liquid precursors at high pressure, for example, up to 500 psi, without having to rely on high pressure pumps, and no high cycle mechanical pump with rubbing parts exposed to precursors. To provide the pressure, an inert gas such as argon is charged into the ampoules 208, 210 at a pressure of about 90 psi through line 220. A liquid outlet line 222 is disposed in each ampoule 208, 210 so that as the inert gas, e.g., argon, is delivered to the ampoule 208, 210 and the appropriate valves are opened, the liquid is forced out through the liquid outlet line 222 through a suitable valve and into the liquid delivery line 220.

The delivery line 212 is connected from each ampoule 208, 210 to the vaporizer 120. A first zero dead volume valve is disposed on the outlet of the ampoule to control delivery of the liquid to the delivery line 212. The valve is preferably a three-way valve connecting the bypass line 218 and the liquid delivery line 212. The bypass line 218 in turn is connected to a cold trap 250 and an exhaust manifold (not shown). A high pressure gauge 224 and a LFC 226 are disposed downstream from a valve 228 introducing the solvent and the purge gas. The LFC controls delivery of the liquid to the mixing port 230 connected between the liquid precursor delivery lines. A low pressure gauge 232 is disposed on the inert gas line 232 to monitor pressure.

The liquid precursor delivery lines 212 deliver liquid precursors into the mixing port 230 upstream from the vaporizer 120. A solvent delivery line 234 also delivers a solvent into the liquid delivery line 212 downstream from the mixing port 230 where the liquid precursors and the solvent are mixed and delivered into the vaporizer 120. At the vaporizer 120, a carrier gas line 236 delivers a carrier gas into the delivery line 212 to carry the liquid precursors and the solvent into the vaporizer 120 through the capillary tube or nozzle. In addition, a concentric carrier gas line 238 delivers a carrier gas around the nozzle or injection tip to ensure that even a small amount of liquid is delivered to the vaporizing surfaces. The delivery line from the mixing port 230 and into the vaporizer 120 is preferably made of a material having a low coefficient of friction, such as Teflon® polymer, which does not impede or inhibit the flow rate of the fluid. This feature assists in the delivery of small volumes of liquid precursor. The solvent module 204 includes one or more chargeable ampoules similar to the liquid precursor ampoules. Preferably, there are two solvent ampoules 240, 242 and two liquid precursor ampoules 208, 210. The liquid precursor ampoules 240, 242 can deliver two separate precursors which can be mixed at the mixing port 230 or can deliver the same precursor together or alternatively. The liquid precursor ampoules 240, 242 are designed with a slotted sculptured bottom to draw the liquid downwardly in each ampoule 240, 242 so that the liquid may (1) be detected at very low levels and (2) be drawn out of each ampoule 240, 242 even at low levels. This is particularly important in dealing with expensive liquids which are preferably not wasted. In addition, the ampoules 240, 242 include an ultrasonic detector for discerning the volume of liquid in each ampoule 240, 242 even at low levels so that continuous processing may be achieved.

Figure 4 is a perspective view of a zero dead volume valve. The valve includes a liquid precursor inlet 252 and a solvent inlet 254 and a single outlet 256. The solvent is routed through the solvent inlet 254 through a solvent control actuator 258 and into the liquid precursor control actuator 260. A plunger 262 controls entry of the solvent into and consequently out of the solvent control actuator 258 as shown in Figure 5. The liquid precursor is routed through the precursor inlet 252 and into precursor control actuator 260 when the plunger 264 in the actuator is in the open position. When the plunger 262 is in the closed position, the precursor is prevented from entering the actuator and is flushed out of the valve by the plunger 262 and by flow of solvent through the valve. The solvent is able to enter the precursor control actuator 260 whether the plunger 262 is in the open or closed position to enable solvent purge of the valve as shown in Figure 5. The plunger 262 is contoured to seal the liquid precursor inlet while enabling solvent flow into the actuator. Continuous solvent flow allows the system to be continuously purged with solvent when the liquid precursors are shut off.

Additionally, a single actuator valve is disposed on the outlets of the ampoules to control delivery of liquid precursor and to prevent clogging in the actuator. Also, the two way valves are preferably disposed on the downstream side of the liquid flow controllers in the vaporizer panel.

The delivery tubes are preferably made of a material such as Teflon® polymer to promote frictionless fluid flow therein to prevent clogging and deposition along the path of the tubes. It has been learned that Teflon® polymer provides a better conduit for materials such as the barium, strontium and titanium precursor liquids used in the deposition of BST and other precursors and materials used in the deposition of tantalum pentoxide (Ta₂O₅), zirconate titanate (ZrxTiyOz), strontium titanate (SrTiO₃), lead zirconate titanate (PZT), lanthanum-doped PZT, bismuth titanate (Bi₄Ti₃O₁₂), barium titanate (BaTiO₃), platinum, iridium, and ruthenium among others. The plumbing system is designed to enable rapid flushing of the lines and valves during routine maintenance. Additionally, the system is adapted to enable sequential shutdown of each of the valves as well as to deliver an automatic flush of a controlled amount of solvent through the vaporizer 120 and the delivery lines in case of a power outage. This safety feature ensures that during uncontrolled power outages, the system will not be subject to clogging.

The delivery system may also comprise a bubbler system. A carrier gas such as argon can be bubbled through a solvent to suppress premature solvent evaporation from the precursor Thereby ensuring the precursor liquid will not be dried out en route to the vaporizer 120.

In situ liquid flow controllers and piezoelectric control valves are also used to maintain heightened control over the system. The high pressure gauges present on precursor and solvent lines as well as vacuum gauges on the vacuum manifolds are used to measure whether chemicals remain in the lines. These gauges are also used for on board leak integrity measurements.

One embodiment of the present invention includes a liquid CVD component delivery system. The system having two pressurized ampoules of liquid CVD component and a related LFC, such as a needle valve, which operates without sliding seals and can be used at pressures of less than 250 psi. Two solvent ampoules deliver solvent into the liquid delivery lines for cleaning and maintenance as well as into the mixing port during processing. PVD Deposition Chamber Figure 6 is cross sectional view of a PVD chamber for depositing conductive materials used in the fabrication of semi-conductor devices using a dielectric layer described herein. The PVD chamber 301 generally comprises a chamber enclosure 302, a target 304, a substrate support 306, a gas inlet 308 and a gas exhaust 310. The chamber enclosure 302 includes a chamber bottom 312 and a chamber side wall 314. A slit valve 315 is disposed on a chamber side wall 314 to facilitate transfer of a substrate 316 into and out of the PVD chamber 301. The substrate support 306 is disposed on a substrate support lift assembly 318 through the chamber bottom 312. Typically, a temperature control element (not shown), such as a heater, is incorporated within the substrate support 306 to control the temperature of the substrate 316 during processing. Preferably, the substrate support 306 is made of stainless steel, and the temperature control element comprises a platinum/rhodium heater coil. The substrate support lift assembly 318 moves the substrate support 306 vertically between a substrate transfer position and a substrate processing position. A lift pin assembly 320 lifts the substrate 316 off the substrate support 306 to facilitate transfer of the substrate 316 between the chamber and a robot blade (not shown) used to transfer the substrate 316 into and out of the chamber 301.

The target 304 is disposed in the top portion of the chamber enclosure 302. Preferably, the target 304 is positioned directly above the substrate support 306. The target 304 generally comprises a backing plate 322 supporting a plate 324 of sputterable material. Target materials used for forming conductive layers such as electrode layers can include platinum, ruthenium, iridium, as well as copper, titanium, aluminum and other metals. Target materials may also include combinations of these metals as well as other materials used for other PVD processes, such as reactive sputtering, wherein the sputtered material reacts with other materials or gases in the process cavity to form the deposited layer. The backing plate 322 includes a flange portion 326 that is secured to the chamber enclosure 302. Preferably, a seal 328, such as an O-ring, is provided between the flange portion 326 of the backing plate 322 and the chamber enclosure 302 to establish and maintain a vacuum environment in the chamber during processing. A magnet assembly 330 is disposed above the backing plate 322 to provide magnetic field enhancement that attracts ions from the plasma toward the target sputtering surface to enhance sputtering of the target material.

A lower shield 332 is disposed in the chamber to shield the interior surfaces of the chamber enclosure 302 from deposition. The lower shield 332 extends from the upper portion of the chamber side wall 314 to a peripheral edge of the substrate support 306 in the processing position. A clamp ring 334 may be used and is removably disposed on an inner terminus 336 of the lower shield 332. When the substrate support 306 moves into the processing position, the inner terminus 336 surrounds the substrate support 306, and a peripheral portion 338 of the substrate 316 engages an inner terminus 333 of the clamp ring 334 and lifts the clamp ring 334 off the inner terminus 336 of the lower shield 332. The clamp ring 334 serves to clamp or hold the substrate 316 as well as shield the peripheral portion 338 of the substrate 316 during the deposition process. Alternatively, instead of a clamp ring 334, a shield cover ring (not shown) is disposed above an inner terminus of the lower shield 332. When the substrate support 306 moves into the processing position, the inner terminus of the clamp ring 334 positioned immediately above the peripheral portion of the substrate 316 to shield the peripheral portion of the substrate 316 from deposition.

Preferably, an upper shield 340 is disposed within an upper portion of the lower shield 332 and extends from the upper portion of the chamber side wall 314 to a peripheral edge 342 of the clamp ring 334. Preferably, the upper shield 340 comprises a material that is similar to the materials that comprise the target 304. The upper shield 340 is preferably a floating-ground upper shield that provides an increased ionization of the plasma compared to a grounded upper shield. The increased ionization provides more ions to impact the target 304 leading to a greater deposition rate because of the increased sputtering from the target 304. Alternatively, the upper shield 340 can be grounded during the deposition process.

A gas inlet 308 disposed at the top portion of the chamber enclosure 302 between the target 304 and the upper shield 340 introduces a processing gas into a process cavity 346. The process cavity 346 is defined by the target 304, the substrate 316 disposed on the substrate support 306 in the processing position and the upper shield 340. Typically, argon is introduced through the gas inlet 308 as the process gas source for the plasma. A gas exhaust 310 is disposed on the chamber side wall 314 to evacuate the chamber prior to the deposition process, as well as control the chamber pressure during the deposition process. Preferably, the gas exhaust 310 includes an exhaust valve 356 and an exhaust pump 358. The exhaust valve 356 controls the conductance between the interior of the chamber 301 and the exhaust pump 358.

To supply a bias to the target 304, a power source 352 is electrically connected to the target 304. The power source 352 may include an RF generator and an RF matching network coupled to the target 304. The power source 352 supplies the energy to the process cavity to strike and maintain a plasma of the processing gas in the process cavity during the deposition process.

A gas exhaust 310 is disposed on the chamber side wall 314 to evacuate the chamber 301 prior to the deposition process, as well as control the chamber pressure during the deposition process. Preferably, the gas exhaust 310 includes an exhaust valve 356 and an exhaust pump 358. The exhaust valve 356 controls the conductance between the interior of the chamber 301 and the exhaust pump 358. The exhaust pump 358 preferably comprises a turbomolecular pump in conjunction with a cryopump to minimize the pump down time of the chamber 301. Alternatively, the exhaust pump 358 comprises a low pressure, a high pressure pump or a combination of low pressure and high pressure pumps.

Other types of sputtering can be used, such as an IMP-PVD process using an IMP Vectra™ chamber, available from Applied Materials, Inc. of Santa Clara, California. The IMP chamber additionally contains power supply coupled to the substrate to create a bias and a coil disposed between the target and the substrate, the coil being coupled to a third power supply. The coil is used to densify the plasma and the biased substrate to attract the sputtered particles in a substantially perpendicular direction to the substrate surface. BST Process

The invention provides a reduced temperature CVD process for the deposition of BST layers from vaporized precursors. The process further provides for depositing conformal, smooth layers having a consistent composition, a high degree of crystallinity, high capacitance, and reduced leakage current.

The BST process reacts the vaporized liquid precursors of the three components with an oxidizing gas such as oxygen, N₂O, O₃ or combinations thereof, and an inert gas, such as argon, at a temperature above the vaporization temperature of the precursors and below a temperature of less than or about 480°C. The temperature range of less than or about 480°C is below the decomposition temperature of the component precursors, and at a temperature wherein the deposition is said to be kinetically controlled. That is, the rate of layer formation is limited by the reaction at the surface of the substrate. Under this temperature regime, the raw materials reaching the surface expand over a large area prior to decomposition, and form a more uniform and conformal layer having a smooth surface even when the surface of the underlying substrate comprises irregular features such as trenches or vias.

Preferably, the delivery lines which carry the component precursors from the vaporizer to the chamber are maintained at a temperature corresponding to the average of the preferred temperatures of the three component precursors in the mixture. The preferred temperature for each component precursor is preferably within a window defined by condensation and decomposition temperatures of the component precursor.

The precursor vapor composition for use in the deposition process is a mix of vaporized liquid precursors combined in predetermined mass or molar proportions. Both a single precursor source or two or more precursor sources can be used. For use in deposition of BST, the first liquid precursor source is preferably a mixture of Ba and Sr polyamine compounds in a suitable solvent such as tetrahydrofuran (THF).

Examples of barium precursors used in the method described herein include bis(tetra methyl heptanedionato) barium, commonly known as Ba (tmhd)₂, bis(tetra methyl heptanedionato) barium penta methyl diethylene triamine, commonly known as Ba PMDET (tmhd)₂, bis(tetra methyl heptanedionato) barium tetraglyme, commonly known as Ba (tmhd)₂ tetraglyme, and combinations thereof. Examples of strontium precursors used in the method described herein include bis(tetra methyl heptanedionato) strontium, commonly known as Sr (tmhd)₂, bis(tetra methyl heptanedionato) strontium penta methyl diethylene triamine, commonly known as Sr PMDET (tmhd)₂, bis(tetra methyl heptanedionato) strintium tetraglyme, commonly known as Sr (tmhd)₂ tetraglyme, and combinations thereof. Precursors, such as bis(tetra methyl heptanedionato) barium and bis(tetra methyl heptanedionato) strontium, without adducts, such as penta methyl diethylene triamine (PMDET ) are preferably used in the deposition method described herein. In one embodiment, the mixtures include combining Ba(tmhd)₂ and Sr(tmhd)₂, combining Ba PMDET (tmhd)₂ and Sr PMDET (tmhd)₂, or in the alternative, Ba (tmhd)₂ tetraglyme and Sr (tmhd)₂ tetraglyme. A preferred molar ration between the barium and strontium precursors (Ba:Sr) is between about 1 : 1 and about 2:1. The second liquid precursor source is preferably bis(tetra methyl heptanedionato) bis isopropanide titanium, commonly known as Ti (I-Pr-O)(tmhd)₂, or other titanium metal organic sources, such as Ti(tBuO)₂(tmhd)₂, in a suitable solvent such as tetrahydrofuran (THF).

In one embodiment, a solution of precursors for the deposition of a BST layer comprises bis(tetra methyl heptanedionato) barium (Ba(tmhd)₂), bis(tetra methyl heptanedionato) strontium (Sr(tmhd)₂), and bis(tetra methyl heptanedionato) bis isopropanide titanium (Ti (I-Pr-O)(tmhd)₂). Varying the proportions of the mixed precursors provides certain flexibility in controlling the composition of the deposited BST layer. The molar ratio between the combined metals in the liquid precursors is preferably between about 1 :1:38 (or about 2.5 mol%: about 2.5 mol%: about 95 mol%) and about 1: 1:4.7 (or about 15 mol%: about 15 mol%: about 70 mol%) barium: strontium: titanium (Ba:Sr:Ti), The molar ratio may vary based upon the requirements of the layer composition and the restriction of the total solubility in the solvent. The barium, strontium, and titanium precursors are preferably vaporized in an inert carrier gas, such as argon, having a flow rate to the chamber of between about 100 seem and about 400 seem, which is referred to as Ar-A herein.

The process is very sensitive to changes in the temperature of the substrate. It has been found that substrate temperatures at or below about 480°C, result in the deposition of uniform layers having a controllable layer composition. Preferably, the conformal BST layer is deposited at a temperature of between about 470°C and about 480°C to provide a consistent layer composition at a commercially acceptable deposition rate. Additionally, the sensitivity of the deposition rate of the Ba, Sr, and Ti precursors to temperature is generally the same at temperatures at or below about 480°C. This property reduces the temperature sensitivity of the BST layer composition at or below about 480°C, and provides a more uniform deposition and increased composition consistency in the deposited material. Generally, due to heat dissipation in the space between the heater and the substrate during the deposition of the BST layer, the heater must be maintained at a temperature between about 30°C and about 100°C higher than the desired substrate temperature.

It has been discovered that the process described herein allows deposition of BST layers having excellent physical properties by maintaining the pressure within the chamber between about 2 Torr and about 8 Torr to avoid gas phase reactions. In one embodiment the chamber pressure is maintained between about 2 Torr and about 4 Torr during the deposition process. In one embodiment, a pressure of about 4 Torr has been used to avoid gas phase reactions. By avoiding gas phase reactions, enhanced control of the composition of the deposited layer can be achieved by increasing the amount of raw material reaching the surface of the substrate. It has been observed that BST layers deposited under the above described processing conditions, and further illustrated in the Examples below, produce an oxide layer comprising a titanium molar fraction of between about 50 mol% and about 53 mol% at a temperature at or below about 480°C and at a pressure of between about 2 Torr and about 8 Torr. The BST layer also comprises from between about 15 mol% and about 33 mol% barium and between about 15 mol% and about 33 mol% strontium. The BST layer has been observed to comprises about 24 mol% barium and about 24 mol% strontium, when the barium and strontium precursors have about a 1:1 Ba:Sr molar ratio.

Particularly, it has been found that the process of the invention allows for the deposition of BST layers having high capacitance, for example, of greater than about 60 /F/μm², preferably greater than about 100 /F/μm², and a reduced leakage current of less than about 5xl0^"8 A/cm². It is contemplated that the dielectric constants of high dielectric constant (HDC) material is increased by increasing the crystallinity of the deposited HDC material. Preferably, the BST layer is subsequently annealed to produce a BST layer with an improved degree of crystallinity. In particular, annealing temperatures between about 600°C and about 750°C for the BST layer deposited under the processing temperatures stated above, will improve the crystallinity of the perovskite phase of the BST layer, thereby leading to a layer with improved capacitance and capacitance density. The BST layer is preferably annealed in a separate chamber, such as a RTP XEplus Centura® available from Applied Materials, Inc., Santa Clara, California.

The chemical and physical properties of the deposited BST layer can also be controlled by selectively supplying one or more oxidizers or varying the flow rate of the oxidizers. While the process described herein is suitable for use with a wide variety OF oxidizers, such as O₂, N₂O and O₃, it has now been found that the process also allows for the deposition of BST layers having high capacitance when O₂ is used as the primary or sole oxidizer. The oxidizing gas flow rate is preferably between about 300 seem and about 3000 seem. The invention also provides a second carrier gas flow, preferably a second argon flow having a passageway concentric with the passageway of a primary gas flow carrying the precursors or solvent to the vaporizer. The secondary gas flow, referred to as argon B flow, allows reduction or total elimination of liquids in the gas flow downstream from the vaporizer by capturing liquid droplets that may condense at the edge of the passageway of the first carrier gas flow, referred to as argon A (Ar-A) flow, upstream from the vaporizer.

The secondary gas flow, preferably of argon, has a preferred flow rate of between about

200 seem and about 1000 seem, and is referenced as argon B (Ar-B) herein. The vaporized precursor is then directed to the CVD reactor for deposition of a BST layer.

Stabilizing the vaporization of the precursors allows more efficient use of the precursors and reduces material deposition on the chamber components, thus minimizing the need for repeated servicing of the deposition reactor.

The invention also provides a heater spacing from the substrate for depositing the BST layer. The heater spacing allows for establishing and maintaining a temperature at which the precursors can decompose to deposit the layer thereby influencing the deposition rate as a higher decomposition temperature, i.e. a closer heater spacing, promotes an increased rate of layer deposition. The heater spacing has a preferred spacing of equal to or less than about 18 millimeters (mm), which corresponds to a preferred spacing of equal to or less than about 700 thousands of an inch (mils), for depositing a BST layer from the respective precursors on a 200 mm substrate. Preferably, the heater spacing is between about 7 mm (about 300 mils) and about 18 mm (about 700 mils).

An example of a preferred process regime for the deposition of a BST film provides a solution of Ba(tmhd)₂, Sr(tmhd)₂, and Ti (I-Pr-O)(tmhd)₂ precursors for the deposition of a BST layer in an argon carrier gas (Ar-A) at a flow rate of about 130 seem with an oxidizing gas flow rate of oxygen or nitrous oxide of about 500 seem, and a secondary gas of argon at a flow rate of about 230 seem. The processing gases are introduced into a processing chamber maintained at a pressure of about 4 Torr and a substrate temperature between about 470°C and about 480°C. The deposited BST layer comprises between about 50 mol% and about 53 mol% of titanium. The heater is spaced at about 14 mm. The above described processing regime deposits the layer at a rate between about 20 A/min and about 100 A/min. In one embodiment, the above described processing regime produced a deposition rate between about 40 A/min and about 50 A/min. Once deposited, the BST layer was annealed at a temperature of about 750°C for about 3 minutes.

Figure 7 is a graph of the deposition rate and titanium concentration of the deposited BST layer versus heater temperature in a 200 mm substrate process of one embodiment of the invention. An increase in heater temperature provides an increased deposition rate without substantial degradation of the precursors. An increase in heater temperature will also increase the titanium concentration (mol%) in the deposited layer. The heater temperature can vary from about 500°C and about 510°C to produce a titanium concentration of between about 50 mol% and about 53 mol% under the embodiment.

The first precursor was a mixture of Ba(tmhd)₂, Sr(tmhd)₂, and Ti (I-pr-o) (tmhd)₂ in THF solvent acetate which provides a molar ratio of Ba:Sr:Ti of about 1:1:8. A plantinum layer was disposed on the substrate prior to being exposed to the precursors. A deposition rate of between about 45 A/minute and about 48 A/minute was achieved at a heater temperature of between about 500°C and about 510°C, which gives a substrate temperature between about 470°C and about 480°C, using a total liquid flow rate of the precursors of about 120 mg/m and a process gas flow rate of about 2000 seem. A vaporizer according to the present invention was also used, wherein the vaporizer lines for the precursors were maintained at about 240°C.

As shown by Figure 7, the deposition rate increases an average of about 0.45 A/min for about each 1°C increase in the heater temperature at about 480°C, showing that the deposition rate has a strong sensitivity to temperature. The titanium concentration (mol%) in the deposited BST layer increases an average of about 0.36 A/min for about each 1°C increase in the heater temperature at about 480°C, showing that the titanium concentration has a strong sensitivity to temperature. The BST film deposited with the above described deposition parameters can provide a high quality layer having good uniformity within the substrate and from substrate to substrate. A heater temperature between about 500°C and about 510°C provided a substrate temperature between about 470°C and about 480°C and a deposition rate of about 45 A/minute. Electrical properties of capacitance densities (C/A) of greater than or equal to about 60 /F/μm² and a leakage current of less than about 5xl0^"8 amps/cm² have been obtained with layers deposited under these parameters. In one embodiment, capacitance densities (C/A) of greater than or equal to about 100 /F/μm² and a leakage current of less than about 5xl0^"8 amps/cm² were observed for some layers deposited under these parameters

Figure 8 is a graph of the composition sensitivity of Ti and deposition rate to the total mass flow rate of the BST precursors in the CVD BST process described for Figure 7. The concentration (mole %) of Ti is plotted versus total BST flow rate in milligrams/minute (mgm). The Ti concentration of the deposited layer does not substantially change over the range of the BST flow rate. This property illustrates that the concentration of the layer is not sensitive to mass flow rates and therefore confirms that the deposition process is kinetically controlled and not controlled by gas phase reactions. Further, the deposition rate increases with total BST flow rate, therefore illustrating that the rate of layer formation is limited by the reaction of available materials at the surface of the substrate.

In one embodiment of the invention, the BST layer may be used in processing a substrate to fabricate of a semi-conductor device, such as a D-RAM structure shown in Figure 9. The substrate is processed by depositing a first electrode, depositing an oxide layer on the first electrode, and then depositing a second electrode on the oxide layer. Depositing the oxide layer comprises introducing a precursor reactant gas comprising barium, strontium, and titanium, to a processing chamber, introducing an oxidizing gas to the processing chamber, and reacting the precursor reactant gas in the presence of the oxidizing gas at a substrate temperature of less than or equal to about 480°C to deposit the oxide layer. The substrate may be annealed after depositing the oxide layer or after depositing the second electrode to improve the crystallinity of the layer.

Figure 9 is a schematic cross sectional view of a simplified DRAM having a "cup" structure. The DRAM device 400 is formed on a silicon substrate 410 and generally comprises a transistor 420 disposed below a capacitor 430. The inventors contemplate a variety of DRAM designs in addition to the DRAM design shown for illustrative purposes in Figure 9, such as the DRAM device having a trench capacitor as shown in Figure 10 and described below.

As shown in Figure 9, the access transistor 420 for the DRAM device 400 is positioned below the trench capacitor 430. Preferably, the transistor 420 comprises a n-p- n transistor having a N+ doped material source region, a P- doped gate region disposed adjacent the source region, and N+ doped drain region disposed adjacent the gate region and opposite the source region (not shown). Preferably, the transistor comprises p-doped polysilicon in contact with the capacitor 430. The transistor 420 of the DRAM device is formed as described above using techniques generally known in the art.

Preferably, the transistor 420 is connected to an electrode of the capacitor 430 through a barrier layer 425. The barrier layer 425 comprises a conducting material, such as titanium nitride (TiN) to prevent interlayer diffusion from the conductive material of the electrodes into the polysilicon material of the transistor 420. Conductive barrier materials including tantalum (Ta), tantalum nitride (TaN), tungsten (W), and tungsten nitride (WN) among others, that provide for good adhesion between the transistor 420 and capacitor 430 may be used for the barrier layer 425.

The capacitor 430 generally comprises a first electrode 450, a second electrode 470, and a dielectric material 460 disposed therebetween. The capacitor 430 is generally formed in a high aspect ratio feature 435 (i.e., aspect ratios of 4: 1 or greater) etched in a dielectric material 440 such as silicon dioxide.

Once the feature 435 has been etched in the dielectric material 440, the first electrode 450 is deposited as a thin, conformal layer on the surfaces within the feature 435. The first electrode 450 generally comprises a conductive material, such as platinum, ruthenium, ruthenium oxide, iridium, or iridium oxide, which may be deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD). The conductive material of the first electrode 450 described herein has a resistivity, p, less than about 500 μΩ-cm, and even more preferably, less than about 250 μΩ-cm. Preferably, the conductive material of the first electrode 450 is platinum deposited by a PVD method. It is also contemplated that the first electrode 450 improves adhesion between the dielectric material 460 and the surrounding dielectric material 440 formed on the substrate and the transistor 420. An exemplary processing regime for sputter depositing the platinum material comprises introducing an inert gas, such as argon or helium, into a processing chamber at a rate sufficient to produce a chamber pressure between about 5 mTorr and about 100 mTorr, preferably between about 20 mTorr and about 50 mTorr and most preferably at about 30 mTorr. The power supply 352 delivers a power density between about 0.6 watts (W)/cm² and about 19 W/cm² to a platinum target, such as target 304 shown in Figure 5. The power density provides a power level between about 200 watts and about 6000 W for a 200 mm substrate. A power level between about 750 Watts and about 1500 W is preferred used to sputter the platinum target. The bias between the target and the substrate creates a plasma of ionized ions therebetween. The ions are attracted to the relatively negative biased target 304, impact the target 304 and dislodge sputtered particles of platinum from the target 304. Some of the sputtered particles are directed toward the substrate 316 and are deposited thereon. The substrate 316 is maintained at a temperature between about 10°C and about 400°C. Preferably a temperature below about 300°C is used during the deposition process. In one embodiment, platinum is deposited on the substrate to a thickness of between about 5θA and about 50θA for a 0.13μm feature having an aspect ration of about 5:1.

Referring to Figure 9, after the first electrode 450 has been deposited over the surfaces of the feature 435, the dielectric layer 460 is deposited over the first electrode 450. The dielectric layer 460 comprises a high dielectric metal oxide, preferably the BST layer described herein deposited by chemical vapor deposition.

One exemplary process for CVD BST on a 200 mm substrate mounted on a heated substrate holder is described below. The deposition occurs between about 2 Torr and about 8 Torr and preferably between about 2 Torr and about 4 Torr. The substrate is maintained at a temperature equal to or less than about 480°C, and preferably between about 470°C and about 480°C. Vaporized liquid precursors comprising a solution of Ba(tmhd)₂, Sr(tmhd)₂, and Ti (I-Pr-O)(tmhd)₂, suspended in an inert carrier gas, preferably an argon gas (Ar-A), are introduced into the processing chamber at a flow rate of about 500 seem, or between about 60 mg/m and about 120 mg/m. The Ba PMDET (tmhd)₂ and Sr PMDET (tmhd)₂ solution is formed by disposing the precursor in a liquid solvent, such as tetrahydrofuran (THF), at a molar ratio of Ba:Sr of between about 1: 1 and about 2:1.

The argon carrier gas has a flow rate of between about 100 seem and about 3000 seem. In one embodiment, the argon carrier gas has a flow rate between about 400 seem and about 800 seem. An oxidizing gas, such as oxygen, having a flow rate between about 100 seem and about 3000 is introduced into the processing chamber to react with the vaporized precursors to deposit the BST layer. An oxidizing gas flow rate between about 300 seem and about 800 seem is preferably used during the deposition process. A secondary carrier gas of argon is provided at a flow rate of between about 100 seem and about 3000 seem to ensure sufficient vaporization of the liquid precursor for efficient deposition of the BST layer. A secondary carrier gas of argon at a flow rate between about 400 seem and about 800 seem is preferably used. A spacing between the heater/showerhead and the substrate is between about 7 mm (about 300 mils) and about 18 mm (about 700 mils). A spacing between the heater/showerhead and the substrate is preferably about 14 mm. The dielectric layer 622 is preferably deposited to a thickness between about 5θA and about 50θA. A thickness between about 200A and about 30θA is preferably used in the described D-RAM structure.

The deposited BST CVD layer is then annealed at a temperature between about 600°C and about 750°C for between about 0.5 minutes and about 10 minutes to improve the crystallinity of the perovskite phase of the BST layer, thereby leading to a layer with improved capacitance and capacitance density. The inventors contemplate the use of annealing processes and apparatus known in the art, such as a oxygen plasma anneal process, to produce the invention. In another embodiment of the invention, the dielectric layer 622 is deposited by depositing an initial, or first dielectric layer of BST, by the processing regime described above to a thickness of about lOOA, and then annealing the first BST layer by the annealing embodiments described above. After depositing the first BST layer, a second BST layer is deposited by the processing regime described above to a thickness of about 15θA to form the dielectric layer 622. The second BST layer may then be annealed by the annealing embodiments described above.

The second electrode 470 is then deposited over the dielectric layer 460. Preferably, the second electrode 470 comprises the same material as the first electrode 450 (discussed above) and is deposited using the same PVD deposition techniques as described for the first electrode 624. After deposition of the second electrode 470, the substrate is annealed at a temperature between about 400°C and about 600°C for between about 1 minute and about 10 minutes to improve the interface between the BST CVD layer and the PVD Pt second electrode. The improved interface between the dielectric material 460 and the second electrode is believed to improve adhesion and provide improved electrical properties including improved capacitance and capacitance density of the layers. It is believed that the first and second electrodes 450, 470 further prevent interlayer diffusion of material into the dielectric layer 460 during a substrate anneal processes used to increase the dielectric constant of the dielectric layer 622 and further processing of the substrate. The inventors contemplate the use of annealing processes and apparatus known in the art, such as a oxygen plasma anneal process, to produce the invention. After deposition, the substrate may then be further process, such as planarization, if necessary, and/or further deposition of materials such as dielectric materials and conductive materials for subsequent metallization.

The anneal processes described above can be performed in a variety of anneal chambers, including conventional furnace anneal chambers and rapid thermal anneal chambers. Anneal chambers in general are well known and commercially available. An example of an anneal chamber is the RTP XEplus Centura® thermal processor available from Applied Materials, Inc., Santa Clara, California. The inventors also contemplate using other commercially available thermal processors. In one embodiment of the invention, the dielectric layer 460 is annealed at a temperature of between about 700°C and about 800°C for between about 30 seconds and about 300 seconds in a rapid thermal anneal process furnace. The second electrode 470 can be annealed at a temperature between about 400°C and about 600°C for between about 1 minute and about 10 minutes.

Figure 10 is a cross sectional view of another embodiment of a DRAM device having a trench capacitor formed using the methods of the invention. The DRAM device

610 is formed on a silicon substrate and generally comprises an access transistor 612 and a trench capacitor 618. The inventors contemplate application of the trench capacitor according to the invention in a variety of DRAM designs in addition to the DRAM design shown for illustrative purposes in Figure 10. For example, in one DRAM design, the access transistor is disposed at a location directly above the trench capacitor.

As shown in Figure 10, the access transistor 612 for the DRAM device 610 is positioned adjacent a top portion of the trench capacitor 618. Preferably, the access transistor 612 comprises an n-p-n transistor having a source region 615, a gate region 614 and a drain region 616. The gate region 614 comprises a P- doped silicon epi-layer disposed over the P+ substrate. The source region 615 of the access transistor 612 comprises an N+ doped material disposed on a first side of the gate region 614, and the drain region 616 comprises an N+ doped material disposed on a second side of the gate region 614, opposite the source region 615. The source region 615 is connected to an electrode of the trench capacitor.

The trench capacitor 618 generally comprises a first electrode, a second electrode and a dielectric material disposed therebetween. The P+ substrate 619 generally serves as a first electrode of the trench capacitor 618 and is connected to a ground connection. A trench 623 is formed in the P+ substrate 619 and filled with a heavily doped N+ polysilicon 621 which serves as the second electrode of the trench capacitor 618. The dielectric material 622 is disposed between the P+ substrate 619 and the N+ polysilicon 621. Conductive materials may be deposited inside the trench 623 between the P+ substrate 619 and the N+ polysilicon 621, encapsulating the dielectric material 622, to form the first and second electrodes of the DRAM structure. The conductive materials are generally deposited as first and second electrodes 624, 625.

According to the invention, the trench capacitor 618 includes a first electrode 624 disposed between the dielectric material 622 and the P+ substrate 619. Preferably, a second electrode 625 is also disposed between the dielectric material 622 and the N+ polysilicon 621. The trench capacitor 618 is formed in a high aspect ratio trench structure.

The high aspect ratio trench 623 is formed by etching the doped P+ substrate 619. Once the trench structure 623 has been etched on the P+ substrate 619, the first electrode 624 is deposited over the surfaces of the trench structure 623. The first electrode 624 also improves adhesion of the dielectric material 622 to the P+ substrate 619. The first and second electrodes 624, 625 are deposited to form thin, conformal layers on the surfaces within high aspect ratio features. The electrodes 624, 625 generally comprise a conductive materials, such as platinum, ruthenium, ruthenium oxide, iridium, or iridium oxide, which may be deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD). Preferably the conductive material of the first and second electrodes 624, 625 is platinum deposited by the PVD method described above for the first and second electrodes 450 and 470 of DRAM structure 400.

In one embodiment, platinum is deposited on the substrate to a thickness of between about 5θA and about 50θA for a 0.13μm trench having an aspect ration of about 5:1. In another embodiment, platinum is deposited on the substrate to a thickness of about 200 A. For example, the first electrode 624 can be deposited to a thickness of about 300 A for a feature having dimensions of about 0.25μm wide and about 2.5μm deep. The conductive material of the first electrode 624 described herein has a resistivity, p, less than about 500 μΩ-cm, and even more preferably, less than about 250 μΩ-cm.

Referring to Figure 10, after the first electrode 624 has been deposited over the surfaces of the trench structure 623, the dielectric layer 622 is deposited over the first electrode 624. Preferably, the dielectric layer 622 comprises a high dielectric metal oxide, preferably the BST layer described herein deposited by the chemical vapor deposition describe above for the dielectric layer 460 of DRAM structure 400.

The deposited BST CVD layer is then annealed at a temperature between about 600°C and about 750°C for between about 0.5 minutes and about 10 minutes to improve the crystallinity of the perovskite phase of the BST layer, thereby leading to a layer with improved capacitance and capacitance density. The inventors contemplate the use of annealing processes and apparatus known in the art, such as a oxygen plasma anneal process, to produce the invention.

In another embodiment of the invention, the dielectric layer 622 is deposited by depositing an initial, or first dielectric layer of BST, by the processing regime described above to a thickness of about lOOA, and then annealing the first BST layer by the annealing embodiments described above. After depositing the first BST layer, a second BST layer is deposited by the processing regime described above to a thickness of about 15θA to form the dielectric layer 622. The second BST layer may then be annealed by the annealing embodiments described above.

The second electrode 625 is deposited over the dielectric layer 622. Preferably, the second electrode 625 comprises the same material as the first electrode 624 (discussed above) and is deposited using the same PVD deposition techniques as described for the first electrode 624. The deposited PVD Pt layer is then annealed at a temperature between about 400°C and about 600°C for between about 1 minute and about 10 minutes to improve the interface between the BST CVD layer and the PVD Pt layer to improve adhesion and provide improved electrical properties including capacitance and capacitance density of the layers. The inventors contemplate the use of annealing processes and apparatus known in the art, such as a oxygen plasma anneal process, to produce the invention.

To complete the trench capacitor 618, the N+ polysilicon 621 is formed over the second electrode 625 formed in the trench structure 623. The material of the N+ polysilicon 621 fills the trench structure 623 and is connected to the source region 615 of the access transistor of the DRAM device. To complete the DRAM device, the access transistor 612 of the DRAM device is formed above or adjacent a top portion of the trench capacitor using techniques generally known in the art.

The first and second electrodes 624, 625 further prevent interlayer diffusion of material into the dielectric layer 622 during a subsequent substrate anneal process used to increase the dielectric constant of the dielectric layer 622. The anneal process can be performed in a variety of anneal chambers, including conventional furnace anneal chambers and rapid thermal anneal chambers. Anneal chambers in general are well known and commercially available. An example of an anneal chamber is the RTP XEplus Centura® thermal processor available from Applied Materials, Inc., Santa Clara, California. The inventors also contemplate using other commercially available thermal processors. Preferably, the dielectric layer 622 is annealed at a temperature of between about 700°C and about 800°C for between about 30 seconds and 300 seconds in a rapid thermal anneal process furnace. The top electrode can be annealed at a temperature between about 400°C and about 600°C for between about 1 minute and about 10 minutes. While the foregoing is directed to a preferred embodiment of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims which follow.

Claims

Claims 1. A method of depositing an oxide layer on a substrate, comprising: introducing one or more precursors comprising barium, strontium, and titanium, to a processing chamber; and oxidizing the one or more precursors at a substrate temperature of less than or equal to about 480°C to deposit the oxide layer.

2. The method of claim 1, wherein the one or more precursors comprise between about 2.5 mol% and about 15 mol% barium (Ba), between about 2.5 mol% and about 15 mol% strontium (Sr), and between about 70 mol% and about 95 mol% titanium (Ti).

3. The method of claim 1, wherein the one or more precursors comprise one or more barium containing precursors selected from the group of bis(tetra methyl heptanedionato) barium (Ba(tmhd)₂), bis(tetra methyl heptanedionato) barium penta methyl diethylene triamine (Ba PMDET (tmhd)₂), bis(tetra methyl heptanedionato) barium tetraglyme (Ba (tmhd)₂ tetraglyme), and combinations thereof.

4. The method of claim 1, wherein the one or more precursors comprise one or more strontium containing precursors selected from the group of bis(tetra methyl heptanedionato) strontium (Sr(tmhd)₂), bis(tetra methyl heptanedionato) strontium penta methyl diethylene triamine (Sr PMDET (tmhd)₂), and bis(tetra methyl heptanedionato) strontium tetraglyme (Sr (tmhd)₂ tetraglyme), and combinations thereof.

5. The method of claim 1, wherein the one or more precursors comprise one or more titanium containing precursors selected from the group of bis(tetra methyl heptanedionato) bis isopropanide titanium (Ti (I-Pr-O)₂(tmhd)₂), Ti(tBuO)₂(tmhd)₂, and combinations thereof.

6. The method of claim 1, wherein the substrate is position between about 7 mm and about 18 mm from a heater.

7. The method of claim 1, wherein the processing chamber is maintained at a pressure between about 2 Torr and about 8 Torr.

8. The method of claim 1, wherein the reactant gas comprises about 24 mol% barium, about 24 mol% strontium, and about 52 mol% titanium.

9. The method of claim 1, wherein the oxide layer has a titanium composition of between about 50 mol% and about 53 mol%.

10. The method of claim 1, wherein a mixture of Ba(tmhd)₂, Sr(tmhd)₂ and Ti (I-Pr-O)₂(tmhd)₂ is introduced into the processing chamber maintained at a pressure of about 4 Torr and a faceplate of a gas distribution plate spaced about 14 mm from a substrate producing a substrate surface temperature of between about 470°C and about 480°C, where the mixture is thermally reacted with oxygen gas to deposit an oxidized barium strontium titanate layer having a titanium composition of between about 50 mol% and about 53 mol%.

11. The method of claim 10, wherein the molar ratio of Ba(tmhd)₂ to Sr(tmhd)₂ (Ba:Sr) is between about 1 : 1 and about 2:1.

12. The method of claim 1, further comprising annealing the oxide layer.

13. The method of claim 12, wherein the oxide layer is annealed at a temperature between about 600°C and about 750°C.

14. A method for processing a substrate, comprising: depositing a first electrode; depositing an oxide layer on the first electrode, comprising: introducing one or more precursors comprising barium, strontium, and titanium, to a processing chamber; oxidizing the one or more precursors in the presence of an oxidizing gas at a substrate temperature of less than or equal to about 480°C to deposit the oxide layer; and depositing a second electrode on the oxide layer.

15. The method of claim 14, wherein the one or more precursors comprise between about 2.5 mol% and about 15 mol% barium (Ba), between about 2.5 mol% and about 15 mol% strontium (Sr), and between about 70 mol% and about 95 mol% titanium (Ti).

16. The method of claim 14, wherein the substrate is position between about 7 and about 18 mm from the faceplate of a gas distribution plate.

17. The method of claim 14, wherein the processing chamber is maintained at a pressure between about 2 Torr and about 8 Torr.

18. The method of claim 14, wherein the one or more precursors comprise about 24 mol% barium, about 24 mol% strontium, and about 52 mol% titanium.

19. The method of claim 14, wherein the oxide layer has a titanium composition of between about 50 mol% and about 53 mol%.

20. The method of claim 14, further comprising annealing the oxide layer prior to depositing the second electrode.

21. The method of claim 20, wherein the oxide layer is annealed at a temperature between about 600°C and about 750°C.

22. The method of claim 14, further comprising annealing the substrate at a temperature between about 500°C and about 550°C.

23. The method of claim 14, wherein the first electrode comprises a material selected from the group of platinum, ruthenium, ruthenium oxide, iridium, iridium oxide, and combinations thereof.

24. The method of claim 14, wherein the first electrode is deposited by chemical vapor deposition or physical vapor deposition.

25. The method of claim 23, wherein the first electrode comprises platinum deposited by physical vapor deposition.

26. The method of claim 14, wherein the second electrode comprises a material selected from the group of platinum, ruthenium, ruthenium oxide, iridium, iridium oxide, and combinations thereof.

27. The method of claim 14, wherein the second electrode is deposited by chemical vapor deposition or physical vapor deposition.

28. The method of claim 27, wherein the second first electrode comprises platinum deposited by physical vapor deposition.

29. A method for processing a substrate, comprising: depositing a first electrode; depositing a first oxide layer on the first electrode by a process comprising: introducing first precursors comprising barium, strontium, and titanium, to a processing chamber; oxidizing the first precursors in the presence of an oxidizing gas at a substrate temperature of less than or equal to about 480°C, and annealing the first oxide layer; depositing a second oxide layer on the first oxide layer by a process comprising: introducing second precursors comprising barium, strontium, and titanium, to a processing chamber; oxidizing the second precursors in the presence of an oxidizing gas at a substrate temperature of less than or equal to about 480°C; and depositing a second electrode on the second oxide layer.

30. The method of claim 29, wherein the first oxide layer is annealed at a temperature between about 600°C and about 750°C.

31. The method of claim 29, further comprising annealing the second oxide layer prior to depositing the second electrode.

32. The method of claim 31, wherein the second oxide layer is annealed at a temperature between about 600°C and about 750°C.