WO2002001425A2

WO2002001425A2 - Method for remotely utilizing configurable hardware

Info

Publication number: WO2002001425A2
Application number: PCT/US2001/006689
Authority: WO
Inventors: Prasanna Sundararajan; Steven A. Guccione
Original assignee: Xilinx, Inc.
Priority date: 2000-06-23
Filing date: 2001-03-01
Publication date: 2002-01-03
Also published as: WO2002001425A3

Abstract

A system and method for providing the use of configurable hardware devices to a user over a network is disclosed. The user of the hardware device generates a device design and an associated configuration file using conventional tools on the user's machine. The user then logs into a server having connections to the hardware device. The desired hardware device is chosen by the user. The user then tests the device design by configuring the hardware device and using testing tools to test the hardware device. As a result, the user beneficially receives the use of the hardware device without needing to purchase the hardware device or even have the hardware device at the user's location. The use of the hardware device may be provided on a pay-per-session basis.

Description

METHOD FOR REMOTELY UTILIZING CONFIGURABLE HARDWARE

FIELD OF THE INVENTION

The present invention relates to PLD design testing and verification over a network, and particularly to design testing on remotely located hardware.

BACKGROUND OF THE INVENTION

Programmable logic devices (PLDs) are general-purpose integrated circuits that include both user-configurable circuitry and a configuration memory array that stores user-generated configuration data, which is typically transmitted in a bitstream into the configuration memory array. The user-configurable circuitry typically includes logic elements and associated interconnect resources that are connected to the memory cells of the configuration memory array, and are programmed (configured) by the configuration data stored in the configuration memory array to implement user-defined logic operations (that is, a user's circuit). Examples of PLDs include complex programmable logic devices (CPLDs) , such as the XC9500 family of CPLDs produced by Xilinx, Inc. of San Jose, CA, and field programmable gate arrays (FPGAs) , such as the Virtex™ family of FPGAs produced by Xilinx, Inc.

Fig. 1 is a block diagram illustrating a system 100 used to develop a logic design (i.e., configuration data) that configures a particular (target) PLD to perform a specific logic operation that involves several steps. The development process is performed on a computer or work station (user platform) 101. First, a graphical or functional description of the logic operation is entered into user platform 101 using well-known schematic capture or hardware description language (HDL) tools 102. Next, using a well-known "place-and-route" software tool 103, the graphical/functional description is converted into configuration data 104. Configuration data 104 is then converted into a bitstream for transmission into the configuration memory array of the target PLD. As an optional final step, the validity of the logic design is tested by loading configuration data 104 onto an actual (test) PLD 110, and then running a test program 105 during which test data values are applied to the pins of PLD 110, and output signals received from PLD 110 are analyzed to confirm that the logic design is properly implemented in PLD 110.

Some PLDs now support dynamic reconfiguration. Dynamic reconfiguration (i.e., run-time reconfiguration, on-the-fly reconfiguration, or in-circuit reconfiguration) allows modifications of the system configuration during normal PLD operation. There is no need to reset the remaining circuitry or to remove reconfigurable elements from a host system for programming. Dynamically reconfigurable logic includes dynamically reconfigurable FPGAs (chip-level dynamic reconfiguration) , dynamically reconfigurable boards with FPGAs (board-level dynamic reconfiguration) , or any other logic circuits capable of dynamic reconfiguration. . A dynamically reconfigurable FPGA may support partial reconfiguration or may be programmed in a full reconfiguration. Partial reconfiguration is a form of reconfiguration that allows only a portion of a reconfigurable system to be reconfigured. A partial reconfiguration can be non- disruptive (the portions of the system that are not being reconfigured remain fully operational during the entire reconfiguration cycle) , or disruptive (the partial reconfiguration affects other portions of the system) . Reconfiguration of a PLD while the PLD is on and functioning necessarily requires the PLD to be programmed and functioning prior to reconfiguration. For these reasons, a company desiring to use a reconfigurable PLD requires the use of at least one PLD to test reconfigurable designs during the design verification phase.

PLDs are constantly improving. These improvements make PLDs more powerful and flexible, but the increased capability and complexity of the improvements also cause these PLDs to be more expensive. Some testing boards containing extremely complicated PLDs, such as the Virtex family of FPGAs produced by Xilinx, Inc., can cost as much as $10,000 each. A designer testing a prototypical design on one or many PLDs may not have the resources to purchase such expensive equipment. However, proper design verification requires the PLD configuration data to be tested in-circuit on the PLD hardware. Additionally, reconfigurable designs are not adequately tested by only software. As a result, test program 105 requires the use of the PLD hardware. Therefore, there is a need to make resources available to users to prevent the requirement of equipment purchase for testing.

SUMMARY OF THE INVENTION

Accordingly, the present invention provides a system and method for providing the use of configurable hardware over a network. A configurable hardware device is made available for use by coupling it to a central server connected to a network. Configuration data and test data are received by the central server via the network from a user. Test data may include a clocking signal. Thus, the test data may operate to step the configurable hardware device. The central server transmits the configuration data and the test data to the configurable hardware device. As a result, the configuration data configures the configurable hardware device and the test data is applied to the configured hardware device to generate output data values . These output data values are transmitted to the user via the central server and the network.

In a first embodiment, one of a plurality of configurable hardware devices coupled to a server terminal is chosen for configuration and testing. In a variation of the first embodiment, each configurable hardware device is coupled to one of a plurality of different server terminals . BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a conventional PLD design process flow;

Figure 2A is a block diagram of a usage-based system in accordance with the present invention; Figure 2B is a process flow of a usage-based method in accordance with the present invention;

Figure 3 is a block diagram of a first embodiment of the present invention; and

Figure 4 is a block diagram of a second embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Figure 2A is a block diagram of a usage-based configurable hardware system 200 in accordance with the present invention. As used herein, the term "configurable hardware" refers to integrated circuits or systems that are at least partially configurable using configuration data to perform desired logic functions. For example, a configurable hardware device may include a logic circuit that is controlled by configuration data stored in configuration memory to perform either a logic AND function or a logic OR function on a pair of input data values. A user "configures" such a configurable hardware device by writing selected configuration data into the configuration memory, thereby causing the configurable hardware device to perform the desired logic function (AND or OR) on subsequently-provided input (e.g., test) data values. Configurable hardware includes, but is not limited to, programmable logic devices (PLDs) and systems including one or more PLDs. However, although the present invention is described with specific reference to PLDs, the present invention is also intended to cover other types of configurable hardware, such as hybrid "system-on- a-chip" devices currently under development that include both programmable circuitry and a microprocessor.

Usage-based configurable hardware system 200 includes user platform 201, login platform 203, hardware platforms 208, and configurable hardware devices 210. User platform 201 includes programming files 202 having configuration data 202A and test data 202B. Login platform 203 includes security and access features 204, payment methods 205 and testing features 206. Hardware platforms 208 include hardware interfaces 209, which provide access to configurable hardware devices 210. In one embodiment, configurable hardware devices 210 are PLDs (e.g., Virtex family of FPGAs) .

Each configurable hardware device 210 is coupled to a hardware platform 208. Hardware interfaces 209 provide means for hardware platforms 208 to communicate with a specific configurable hardware device 210.

As described above with respect to Figure 1, configuration data 202A is created for a target configuration hardware device 210. During in-circuit verification, configuration data 202A is downloaded to the target configuration hardware device (e.g., configuration hardware device 210B) for verification. Because target configuration hardware device 210B is remote from user platform 201, the target configuration hardware device 210B must be accessed through a network. As a result, the user of user computer platform 201 must access login platform 203 through a network.

Login platform 203 controls access to configuration hardware devices 210. This access is controlled by implementing security and access features 204. Security and access features 204 handle such tasks as user identification and data encryption. Access to configuration hardware devices 210 is also controlled by payment methods 205. Authorized users are allowed various access options including free access and pre-paid access for a given period of time. Pre-paid access may be made by various methods including credit card payment, on-line fund transfer, and deposit account withdrawal. Access to a specific configuration hardware device 210 is made through testing features 206. Testing features 206 may include a choice of configuration hardware devices 210. In one embodiment, one configuration hardware device 210 is chosen from a list displayed by testing features 206. Unavailable configuration hardware devices 210 may be indicated by color or other means. The estimated time for a presently unavailable configuration hardware device 210 to become available may be indicated by testing features 206, as well. In another embodiment, testing features 206 may display a subset of available configuration hardware devices 210 based on user identification or other feature.

In one embodiment, testing features 206 includes a remote application (e.g., a Java applet) used in the verification process. In another embodiment, testing features 206 includes a client application resident on user platform 201 that is used in the verification process .

Hardware platforms 208 are coupled to configuration hardware devices 210. After the login procedures, the chosen configuration hardware device is accessed through its associated hardware platform. For example, if configuration hardware device 210B is chosen, then user platform 201 is connected to hardware platform 208A, thereby allowing access to configuration hardware device 210B through hardware interface 209B.

It is understood that this invention is not limited to the embodiment disclosed, but is capable of various modifications which would be apparent to one skilled in the art. For example, hardware platforms 208 may be co- located on a single hardware platform. Similarly, login platform 203 may be integrated with each of hardware platforms 208.

Figure 2B is a process flow of the usage based method in accordance with the embodiment of Figure 2A. Figure 2B shows the method starting with a created bitstream (i.e., configuration data) in step 221. Login step 222 may include a userna e/password or other account verification. Step 223 enables a user to encrypt communications (e.g., -encrypt the bitstream prior to download) or to enter a more secure information exchange relationship. The desired configuration hardware device is chosen in step 225. As described above, step 225 may include choosing a configuration hardware device from a list of available devices. Step 225 may also include information as to presently unavailable configuration hardware devices . The estimated duration of configuration hardware device use is entered in step 226. Step 226 provides a definite time period both for billing purposes and for configuration hardware device usage estimates for other users. A payment method is chosen in step 227 and the payment information obtained in step 228. For example, a credit card or debit card number may be used to provide payment for the estimated duration of device use.

Similarly, a deposit account or a free account may be used with or without an estimated duration of device use. In another embodiment, the payment is tied to the username/account to automate payment steps 227-228. Testing tools are started in step 229, thereby allowing interaction with the chosen configuration hardware device. Examples of such testing tools are described in Guccione, U.S. Patent No. 5,995,744 entitled "Network Configuration of Programmable Circuits". The bitstream is checked for validity (e.g., to prevent contentions in the configuration hardware device) in step 230 and the bitstream is downloaded to the configuration hardware device in step 231. Testing and verification step 232 encompasses the actual testing use of the configuration hardware device.

The duration of use may be monitored in step 233 and an option to extend the duration of use presented to a user at a pre-defined time in step 234. After the testing session ends in step 235 the contents of the configuration hardware device are cleared in step 236. The clearing of the contents of the configuration hardware device may take place at the direction of the user or automatically at the close of the session. To conclude the transaction, the user disconnects from the system in step 237. Figure 3 is a block diagram of a first variation of the present invention. Figure 3 shows the use of one of FPGA boards 310 by a remote user platform 301. System 300 includes user platform 301, server 307 and FPGA boards 310. User platform 301 includes data files 302 (including, e.g., a configuration data file). Server 307 includes security and access procedures 304, payment methods 305, testing features 306 and Xilinx Hardware Interface (XHWIF) server 308. XHWIF server 308 includes multiple XHWIFs 309. Each XHWIF 309 is coupled to one FPGA board 310. XHWIFs 309 are described in more detail in the paper "JBits: Java Based Interface for Reconfigurable Computing" by Steve Guccione, et al . , published on CD-ROM in September, 1999, in "MAPLD 1999

Proceedings", the proceedings of the 2nd Annual Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD) .

To initiate hardware verification, user platform 301 connects to server 307 over a network 303 using known techniques. Server 308 requires completion of the requirements of security and access features 304 and payment method 305 prior to accessing testing features 306. In one embodiment, testing features 306 include Java applet testing tools, thereby enabling use over a network such as the internet. Note that application testing tools may also be used, thereby requiring the testing tools to reside on user platform 301.

Testing features 306 allow the choice of one FPGA board 310 (e.g., FPGA board 310C) for verification use. Testing features 306 provide for the download of the configuration data within data files 302 into chosen FPGA board 310C. Testing features 306 also allow user platform 301 to run various testing procedures on FPGA board 310C through testing tools to verify the implementation of the configuration. Such testing procedures may include, for example, downloading the design into the chosen FPGA or stepping the clock and verifying the FPGA function by reading back the output data. Figure 4 is a block diagram of a second variation of the present invention. System 400 is similar to system 300 of Figure 3, but differs in that testing application 403 is included on user platform 401 with a network hardware interface (XHWIFNET) 407, rather than being included as a Java applet with testing features 306 as in system 300.

Although the invention has been described in connection with the present embodiment, it is understood that this invention is not limited to the embodiment disclosed, but is capable of various modifications which would be apparent to a person skilled in the art. For example, the present invention applies to configurable logic devices other than PLDs. Thus, the invention is limited only by the following claims.

Claims

CLAIMSWe Claim:

1. A method for facilitating remote utilization of a first configurable hardware device, comprising: coupling the first configurable hardware device to a first server connected to a network; receiving configuration data and test data from a first user via the network; transmitting the configuration data and the test data from the first server to the first configurable hardware device such that the configuration data is utilized to configure the first configurable hardware device, and the test data is applied to the first configurable hardware device to generate output data values; and transmitting the output data values to the first user via the network.

2. The method of Claim 1, further comprising the step of coupling a second configurable hardware device to the first server.

3. The method of Claim 2, further comprising the step of receiving configuration data and test data from a second user via the network.

4. The method of Claim 1, further comprising the step of coupling a second configurable hardware device to a second server connected to the network.

5. The method of Claim 4, further comprising the step of receiving configuration data and test data from a second user via the network.

6. The method of Claim 1, further comprising the step of requiring the first user to access a specific account on the first server.

7. The method of Claim 1, further comprising the step of requiring the first user to pay for accessing the first ■ configurable hardware device.

8. The method of Claim 1, wherein the first configurable hardware device includes a PLD.

9. The method of Claim 8, wherein the PLD is an FPGA.

10. An apparatus for facilitating remote utilization of a configurable hardware device over a network, the apparatus comprising a first server coupled between the network and the configurable hardware device, the first server including: means for receiving configuration data and test data from a user via the network; means for transmitting the configuration data and the test data from the first server to the configurable hardware device such that the configuration data is utilized to configure the configurable hardware device, and the test data is applied to the configurable hardware device to generate output data values; and means for transmitting the output data values to the user via the network.